arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <mach/dma-register.h>
  34 #include <mach/hardware.h>
  35 #include <mach/irqs.h>
  36 #include <mach/sh73a0.h>
  37 #include <mach/common.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/time.h>
  42
  43 static struct map_desc sh73a0_io_desc[] __initdata = {
  44         /* create a 1:1 entity map for 0xe6xxxxxx
  45          * used by CPGA, INTC and PFC.
  46          */
  47         {
  48                 .virtual        = 0xe6000000,
  49                 .pfn            = __phys_to_pfn(0xe6000000),
  50                 .length         = 256 << 20,
  51                 .type           = MT_DEVICE_NONSHARED
  52         },
  53 };
  54
  55 void __init sh73a0_map_io(void)
  56 {
  57         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  58 }
  59
  60 static struct plat_sci_port scif0_platform_data = {
  61         .mapbase        = 0xe6c40000,
  62         .flags          = UPF_BOOT_AUTOCONF,
  63         .scscr          = SCSCR_RE | SCSCR_TE,
  64         .scbrr_algo_id  = SCBRR_ALGO_4,
  65         .type           = PORT_SCIFA,
  66         .irqs           = { gic_spi(72), gic_spi(72),
  67                             gic_spi(72), gic_spi(72) },
  68 };
  69
  70 static struct platform_device scif0_device = {
  71         .name           = "sh-sci",
  72         .id             = 0,
  73         .dev            = {
  74                 .platform_data  = &scif0_platform_data,
  75         },
  76 };
  77
  78 static struct plat_sci_port scif1_platform_data = {
  79         .mapbase        = 0xe6c50000,
  80         .flags          = UPF_BOOT_AUTOCONF,
  81         .scscr          = SCSCR_RE | SCSCR_TE,
  82         .scbrr_algo_id  = SCBRR_ALGO_4,
  83         .type           = PORT_SCIFA,
  84         .irqs           = { gic_spi(73), gic_spi(73),
  85                             gic_spi(73), gic_spi(73) },
  86 };
  87
  88 static struct platform_device scif1_device = {
  89         .name           = "sh-sci",
  90         .id             = 1,
  91         .dev            = {
  92                 .platform_data  = &scif1_platform_data,
  93         },
  94 };
  95
  96 static struct plat_sci_port scif2_platform_data = {
  97         .mapbase        = 0xe6c60000,
  98         .flags          = UPF_BOOT_AUTOCONF,
  99         .scscr          = SCSCR_RE | SCSCR_TE,
 100         .scbrr_algo_id  = SCBRR_ALGO_4,
 101         .type           = PORT_SCIFA,
 102         .irqs           = { gic_spi(74), gic_spi(74),
 103                             gic_spi(74), gic_spi(74) },
 104 };
 105
 106 static struct platform_device scif2_device = {
 107         .name           = "sh-sci",
 108         .id             = 2,
 109         .dev            = {
 110                 .platform_data  = &scif2_platform_data,
 111         },
 112 };
 113
 114 static struct plat_sci_port scif3_platform_data = {
 115         .mapbase        = 0xe6c70000,
 116         .flags          = UPF_BOOT_AUTOCONF,
 117         .scscr          = SCSCR_RE | SCSCR_TE,
 118         .scbrr_algo_id  = SCBRR_ALGO_4,
 119         .type           = PORT_SCIFA,
 120         .irqs           = { gic_spi(75), gic_spi(75),
 121                             gic_spi(75), gic_spi(75) },
 122 };
 123
 124 static struct platform_device scif3_device = {
 125         .name           = "sh-sci",
 126         .id             = 3,
 127         .dev            = {
 128                 .platform_data  = &scif3_platform_data,
 129         },
 130 };
 131
 132 static struct plat_sci_port scif4_platform_data = {
 133         .mapbase        = 0xe6c80000,
 134         .flags          = UPF_BOOT_AUTOCONF,
 135         .scscr          = SCSCR_RE | SCSCR_TE,
 136         .scbrr_algo_id  = SCBRR_ALGO_4,
 137         .type           = PORT_SCIFA,
 138         .irqs           = { gic_spi(78), gic_spi(78),
 139                             gic_spi(78), gic_spi(78) },
 140 };
 141
 142 static struct platform_device scif4_device = {
 143         .name           = "sh-sci",
 144         .id             = 4,
 145         .dev            = {
 146                 .platform_data  = &scif4_platform_data,
 147         },
 148 };
 149
 150 static struct plat_sci_port scif5_platform_data = {
 151         .mapbase        = 0xe6cb0000,
 152         .flags          = UPF_BOOT_AUTOCONF,
 153         .scscr          = SCSCR_RE | SCSCR_TE,
 154         .scbrr_algo_id  = SCBRR_ALGO_4,
 155         .type           = PORT_SCIFA,
 156         .irqs           = { gic_spi(79), gic_spi(79),
 157                             gic_spi(79), gic_spi(79) },
 158 };
 159
 160 static struct platform_device scif5_device = {
 161         .name           = "sh-sci",
 162         .id             = 5,
 163         .dev            = {
 164                 .platform_data  = &scif5_platform_data,
 165         },
 166 };
 167
 168 static struct plat_sci_port scif6_platform_data = {
 169         .mapbase        = 0xe6cc0000,
 170         .flags          = UPF_BOOT_AUTOCONF,
 171         .scscr          = SCSCR_RE | SCSCR_TE,
 172         .scbrr_algo_id  = SCBRR_ALGO_4,
 173         .type           = PORT_SCIFA,
 174         .irqs           = { gic_spi(156), gic_spi(156),
 175                             gic_spi(156), gic_spi(156) },
 176 };
 177
 178 static struct platform_device scif6_device = {
 179         .name           = "sh-sci",
 180         .id             = 6,
 181         .dev            = {
 182                 .platform_data  = &scif6_platform_data,
 183         },
 184 };
 185
 186 static struct plat_sci_port scif7_platform_data = {
 187         .mapbase        = 0xe6cd0000,
 188         .flags          = UPF_BOOT_AUTOCONF,
 189         .scscr          = SCSCR_RE | SCSCR_TE,
 190         .scbrr_algo_id  = SCBRR_ALGO_4,
 191         .type           = PORT_SCIFA,
 192         .irqs           = { gic_spi(143), gic_spi(143),
 193                             gic_spi(143), gic_spi(143) },
 194 };
 195
 196 static struct platform_device scif7_device = {
 197         .name           = "sh-sci",
 198         .id             = 7,
 199         .dev            = {
 200                 .platform_data  = &scif7_platform_data,
 201         },
 202 };
 203
 204 static struct plat_sci_port scif8_platform_data = {
 205         .mapbase        = 0xe6c30000,
 206         .flags          = UPF_BOOT_AUTOCONF,
 207         .scscr          = SCSCR_RE | SCSCR_TE,
 208         .scbrr_algo_id  = SCBRR_ALGO_4,
 209         .type           = PORT_SCIFB,
 210         .irqs           = { gic_spi(80), gic_spi(80),
 211                             gic_spi(80), gic_spi(80) },
 212 };
 213
 214 static struct platform_device scif8_device = {
 215         .name           = "sh-sci",
 216         .id             = 8,
 217         .dev            = {
 218                 .platform_data  = &scif8_platform_data,
 219         },
 220 };
 221
 222 static struct sh_timer_config cmt10_platform_data = {
 223         .name = "CMT10",
 224         .channel_offset = 0x10,
 225         .timer_bit = 0,
 226         .clockevent_rating = 125,
 227         .clocksource_rating = 125,
 228 };
 229
 230 static struct resource cmt10_resources[] = {
 231         [0] = {
 232                 .name   = "CMT10",
 233                 .start  = 0xe6138010,
 234                 .end    = 0xe613801b,
 235                 .flags  = IORESOURCE_MEM,
 236         },
 237         [1] = {
 238                 .start  = gic_spi(65),
 239                 .flags  = IORESOURCE_IRQ,
 240         },
 241 };
 242
 243 static struct platform_device cmt10_device = {
 244         .name           = "sh_cmt",
 245         .id             = 10,
 246         .dev = {
 247                 .platform_data  = &cmt10_platform_data,
 248         },
 249         .resource       = cmt10_resources,
 250         .num_resources  = ARRAY_SIZE(cmt10_resources),
 251 };
 252
 253 /* TMU */
 254 static struct sh_timer_config tmu00_platform_data = {
 255         .name = "TMU00",
 256         .channel_offset = 0x4,
 257         .timer_bit = 0,
 258         .clockevent_rating = 200,
 259 };
 260
 261 static struct resource tmu00_resources[] = {
 262         [0] = {
 263                 .name   = "TMU00",
 264                 .start  = 0xfff60008,
 265                 .end    = 0xfff60013,
 266                 .flags  = IORESOURCE_MEM,
 267         },
 268         [1] = {
 269                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 270                 .flags  = IORESOURCE_IRQ,
 271         },
 272 };
 273
 274 static struct platform_device tmu00_device = {
 275         .name           = "sh_tmu",
 276         .id             = 0,
 277         .dev = {
 278                 .platform_data  = &tmu00_platform_data,
 279         },
 280         .resource       = tmu00_resources,
 281         .num_resources  = ARRAY_SIZE(tmu00_resources),
 282 };
 283
 284 static struct sh_timer_config tmu01_platform_data = {
 285         .name = "TMU01",
 286         .channel_offset = 0x10,
 287         .timer_bit = 1,
 288         .clocksource_rating = 200,
 289 };
 290
 291 static struct resource tmu01_resources[] = {
 292         [0] = {
 293                 .name   = "TMU01",
 294                 .start  = 0xfff60014,
 295                 .end    = 0xfff6001f,
 296                 .flags  = IORESOURCE_MEM,
 297         },
 298         [1] = {
 299                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 300                 .flags  = IORESOURCE_IRQ,
 301         },
 302 };
 303
 304 static struct platform_device tmu01_device = {
 305         .name           = "sh_tmu",
 306         .id             = 1,
 307         .dev = {
 308                 .platform_data  = &tmu01_platform_data,
 309         },
 310         .resource       = tmu01_resources,
 311         .num_resources  = ARRAY_SIZE(tmu01_resources),
 312 };
 313
 314 static struct resource i2c0_resources[] = {
 315         [0] = {
 316                 .name   = "IIC0",
 317                 .start  = 0xe6820000,
 318                 .end    = 0xe6820425 - 1,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321         [1] = {
 322                 .start  = gic_spi(167),
 323                 .end    = gic_spi(170),
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 static struct resource i2c1_resources[] = {
 329         [0] = {
 330                 .name   = "IIC1",
 331                 .start  = 0xe6822000,
 332                 .end    = 0xe6822425 - 1,
 333                 .flags  = IORESOURCE_MEM,
 334         },
 335         [1] = {
 336                 .start  = gic_spi(51),
 337                 .end    = gic_spi(54),
 338                 .flags  = IORESOURCE_IRQ,
 339         },
 340 };
 341
 342 static struct resource i2c2_resources[] = {
 343         [0] = {
 344                 .name   = "IIC2",
 345                 .start  = 0xe6824000,
 346                 .end    = 0xe6824425 - 1,
 347                 .flags  = IORESOURCE_MEM,
 348         },
 349         [1] = {
 350                 .start  = gic_spi(171),
 351                 .end    = gic_spi(174),
 352                 .flags  = IORESOURCE_IRQ,
 353         },
 354 };
 355
 356 static struct resource i2c3_resources[] = {
 357         [0] = {
 358                 .name   = "IIC3",
 359                 .start  = 0xe6826000,
 360                 .end    = 0xe6826425 - 1,
 361                 .flags  = IORESOURCE_MEM,
 362         },
 363         [1] = {
 364                 .start  = gic_spi(183),
 365                 .end    = gic_spi(186),
 366                 .flags  = IORESOURCE_IRQ,
 367         },
 368 };
 369
 370 static struct resource i2c4_resources[] = {
 371         [0] = {
 372                 .name   = "IIC4",
 373                 .start  = 0xe6828000,
 374                 .end    = 0xe6828425 - 1,
 375                 .flags  = IORESOURCE_MEM,
 376         },
 377         [1] = {
 378                 .start  = gic_spi(187),
 379                 .end    = gic_spi(190),
 380                 .flags  = IORESOURCE_IRQ,
 381         },
 382 };
 383
 384 static struct platform_device i2c0_device = {
 385         .name           = "i2c-sh_mobile",
 386         .id             = 0,
 387         .resource       = i2c0_resources,
 388         .num_resources  = ARRAY_SIZE(i2c0_resources),
 389 };
 390
 391 static struct platform_device i2c1_device = {
 392         .name           = "i2c-sh_mobile",
 393         .id             = 1,
 394         .resource       = i2c1_resources,
 395         .num_resources  = ARRAY_SIZE(i2c1_resources),
 396 };
 397
 398 static struct platform_device i2c2_device = {
 399         .name           = "i2c-sh_mobile",
 400         .id             = 2,
 401         .resource       = i2c2_resources,
 402         .num_resources  = ARRAY_SIZE(i2c2_resources),
 403 };
 404
 405 static struct platform_device i2c3_device = {
 406         .name           = "i2c-sh_mobile",
 407         .id             = 3,
 408         .resource       = i2c3_resources,
 409         .num_resources  = ARRAY_SIZE(i2c3_resources),
 410 };
 411
 412 static struct platform_device i2c4_device = {
 413         .name           = "i2c-sh_mobile",
 414         .id             = 4,
 415         .resource       = i2c4_resources,
 416         .num_resources  = ARRAY_SIZE(i2c4_resources),
 417 };
 418
 419 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 420         {
 421                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 422                 .addr           = 0xe6c40020,
 423                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 424                 .mid_rid        = 0x21,
 425         }, {
 426                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 427                 .addr           = 0xe6c40024,
 428                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 429                 .mid_rid        = 0x22,
 430         }, {
 431                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 432                 .addr           = 0xe6c50020,
 433                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 434                 .mid_rid        = 0x25,
 435         }, {
 436                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 437                 .addr           = 0xe6c50024,
 438                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 439                 .mid_rid        = 0x26,
 440         }, {
 441                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 442                 .addr           = 0xe6c60020,
 443                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 444                 .mid_rid        = 0x29,
 445         }, {
 446                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 447                 .addr           = 0xe6c60024,
 448                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 449                 .mid_rid        = 0x2a,
 450         }, {
 451                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 452                 .addr           = 0xe6c70020,
 453                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 454                 .mid_rid        = 0x2d,
 455         }, {
 456                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 457                 .addr           = 0xe6c70024,
 458                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 459                 .mid_rid        = 0x2e,
 460         }, {
 461                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 462                 .addr           = 0xe6c80020,
 463                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 464                 .mid_rid        = 0x39,
 465         }, {
 466                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 467                 .addr           = 0xe6c80024,
 468                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 469                 .mid_rid        = 0x3a,
 470         }, {
 471                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 472                 .addr           = 0xe6cb0020,
 473                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 474                 .mid_rid        = 0x35,
 475         }, {
 476                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 477                 .addr           = 0xe6cb0024,
 478                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 479                 .mid_rid        = 0x36,
 480         }, {
 481                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 482                 .addr           = 0xe6cc0020,
 483                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 484                 .mid_rid        = 0x1d,
 485         }, {
 486                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 487                 .addr           = 0xe6cc0024,
 488                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 489                 .mid_rid        = 0x1e,
 490         }, {
 491                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 492                 .addr           = 0xe6cd0020,
 493                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 494                 .mid_rid        = 0x19,
 495         }, {
 496                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 497                 .addr           = 0xe6cd0024,
 498                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 499                 .mid_rid        = 0x1a,
 500         }, {
 501                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 502                 .addr           = 0xe6c30040,
 503                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 504                 .mid_rid        = 0x3d,
 505         }, {
 506                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 507                 .addr           = 0xe6c30060,
 508                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 509                 .mid_rid        = 0x3e,
 510         }, {
 511                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 512                 .addr           = 0xee100030,
 513                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 514                 .mid_rid        = 0xc1,
 515         }, {
 516                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 517                 .addr           = 0xee100030,
 518                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 519                 .mid_rid        = 0xc2,
 520         }, {
 521                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 522                 .addr           = 0xee120030,
 523                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 524                 .mid_rid        = 0xc9,
 525         }, {
 526                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 527                 .addr           = 0xee120030,
 528                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 529                 .mid_rid        = 0xca,
 530         }, {
 531                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 532                 .addr           = 0xee140030,
 533                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 534                 .mid_rid        = 0xcd,
 535         }, {
 536                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 537                 .addr           = 0xee140030,
 538                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 539                 .mid_rid        = 0xce,
 540         }, {
 541                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 542                 .addr           = 0xe6bd0034,
 543                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 544                 .mid_rid        = 0xd1,
 545         }, {
 546                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 547                 .addr           = 0xe6bd0034,
 548                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 549                 .mid_rid        = 0xd2,
 550         },
 551 };
 552
 553 #define DMAE_CHANNEL(_offset)                                   \
 554         {                                                       \
 555                 .offset         = _offset - 0x20,               \
 556                 .dmars          = _offset - 0x20 + 0x40,        \
 557         }
 558
 559 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 560         DMAE_CHANNEL(0x8000),
 561         DMAE_CHANNEL(0x8080),
 562         DMAE_CHANNEL(0x8100),
 563         DMAE_CHANNEL(0x8180),
 564         DMAE_CHANNEL(0x8200),
 565         DMAE_CHANNEL(0x8280),
 566         DMAE_CHANNEL(0x8300),
 567         DMAE_CHANNEL(0x8380),
 568         DMAE_CHANNEL(0x8400),
 569         DMAE_CHANNEL(0x8480),
 570         DMAE_CHANNEL(0x8500),
 571         DMAE_CHANNEL(0x8580),
 572         DMAE_CHANNEL(0x8600),
 573         DMAE_CHANNEL(0x8680),
 574         DMAE_CHANNEL(0x8700),
 575         DMAE_CHANNEL(0x8780),
 576         DMAE_CHANNEL(0x8800),
 577         DMAE_CHANNEL(0x8880),
 578         DMAE_CHANNEL(0x8900),
 579         DMAE_CHANNEL(0x8980),
 580 };
 581
 582 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 583         .slave          = sh73a0_dmae_slaves,
 584         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 585         .channel        = sh73a0_dmae_channels,
 586         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 587         .ts_low_shift   = TS_LOW_SHIFT,
 588         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 589         .ts_high_shift  = TS_HI_SHIFT,
 590         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 591         .ts_shift       = dma_ts_shift,
 592         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 593         .dmaor_init     = DMAOR_DME,
 594 };
 595
 596 static struct resource sh73a0_dmae_resources[] = {
 597         {
 598                 /* Registers including DMAOR and channels including DMARSx */
 599                 .start  = 0xfe000020,
 600                 .end    = 0xfe008a00 - 1,
 601                 .flags  = IORESOURCE_MEM,
 602         },
 603         {
 604                 .name   = "error_irq",
 605                 .start  = gic_spi(129),
 606                 .end    = gic_spi(129),
 607                 .flags  = IORESOURCE_IRQ,
 608         },
 609         {
 610                 /* IRQ for channels 0-19 */
 611                 .start  = gic_spi(109),
 612                 .end    = gic_spi(128),
 613                 .flags  = IORESOURCE_IRQ,
 614         },
 615 };
 616
 617 static struct platform_device dma0_device = {
 618         .name           = "sh-dma-engine",
 619         .id             = 0,
 620         .resource       = sh73a0_dmae_resources,
 621         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 622         .dev            = {
 623                 .platform_data  = &sh73a0_dmae_platform_data,
 624         },
 625 };
 626
 627 /* MPDMAC */
 628 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
 629         {
 630                 .slave_id       = SHDMA_SLAVE_FSI2A_RX,
 631                 .addr           = 0xec230020,
 632                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 633                 .mid_rid        = 0xd6, /* CHECK ME */
 634         }, {
 635                 .slave_id       = SHDMA_SLAVE_FSI2A_TX,
 636                 .addr           = 0xec230024,
 637                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 638                 .mid_rid        = 0xd5, /* CHECK ME */
 639         }, {
 640                 .slave_id       = SHDMA_SLAVE_FSI2C_RX,
 641                 .addr           = 0xec230060,
 642                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 643                 .mid_rid        = 0xda, /* CHECK ME */
 644         }, {
 645                 .slave_id       = SHDMA_SLAVE_FSI2C_TX,
 646                 .addr           = 0xec230064,
 647                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 648                 .mid_rid        = 0xd9, /* CHECK ME */
 649         }, {
 650                 .slave_id       = SHDMA_SLAVE_FSI2B_RX,
 651                 .addr           = 0xec240020,
 652                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 653                 .mid_rid        = 0x8e, /* CHECK ME */
 654         }, {
 655                 .slave_id       = SHDMA_SLAVE_FSI2B_TX,
 656                 .addr           = 0xec240024,
 657                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 658                 .mid_rid        = 0x8d, /* CHECK ME */
 659         }, {
 660                 .slave_id       = SHDMA_SLAVE_FSI2D_RX,
 661                 .addr           =  0xec240060,
 662                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 663                 .mid_rid        = 0x9a, /* CHECK ME */
 664         },
 665 };
 666
 667 #define MPDMA_CHANNEL(a, b, c)                  \
 668 {                                               \
 669         .offset         = a,                    \
 670         .dmars          = b,                    \
 671         .dmars_bit      = c,                    \
 672         .chclr_offset   = (0x220 - 0x20) + a    \
 673 }
 674
 675 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
 676         MPDMA_CHANNEL(0x00, 0, 0),
 677         MPDMA_CHANNEL(0x10, 0, 8),
 678         MPDMA_CHANNEL(0x20, 4, 0),
 679         MPDMA_CHANNEL(0x30, 4, 8),
 680         MPDMA_CHANNEL(0x50, 8, 0),
 681         MPDMA_CHANNEL(0x70, 8, 8),
 682 };
 683
 684 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 685         .slave          = sh73a0_mpdma_slaves,
 686         .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
 687         .channel        = sh73a0_mpdma_channels,
 688         .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
 689         .ts_low_shift   = TS_LOW_SHIFT,
 690         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 691         .ts_high_shift  = TS_HI_SHIFT,
 692         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 693         .ts_shift       = dma_ts_shift,
 694         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 695         .dmaor_init     = DMAOR_DME,
 696         .chclr_present  = 1,
 697 };
 698
 699 /* Resource order important! */
 700 static struct resource sh73a0_mpdma_resources[] = {
 701         {
 702                 /* Channel registers and DMAOR */
 703                 .start  = 0xec618020,
 704                 .end    = 0xec61828f,
 705                 .flags  = IORESOURCE_MEM,
 706         },
 707         {
 708                 /* DMARSx */
 709                 .start  = 0xec619000,
 710                 .end    = 0xec61900b,
 711                 .flags  = IORESOURCE_MEM,
 712         },
 713         {
 714                 .name   = "error_irq",
 715                 .start  = gic_spi(181),
 716                 .end    = gic_spi(181),
 717                 .flags  = IORESOURCE_IRQ,
 718         },
 719         {
 720                 /* IRQ for channels 0-5 */
 721                 .start  = gic_spi(175),
 722                 .end    = gic_spi(180),
 723                 .flags  = IORESOURCE_IRQ,
 724         },
 725 };
 726
 727 static struct platform_device mpdma0_device = {
 728         .name           = "sh-dma-engine",
 729         .id             = 1,
 730         .resource       = sh73a0_mpdma_resources,
 731         .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
 732         .dev            = {
 733                 .platform_data  = &sh73a0_mpdma_platform_data,
 734         },
 735 };
 736
 737 static struct resource pmu_resources[] = {
 738         [0] = {
 739                 .start  = gic_spi(55),
 740                 .end    = gic_spi(55),
 741                 .flags  = IORESOURCE_IRQ,
 742         },
 743         [1] = {
 744                 .start  = gic_spi(56),
 745                 .end    = gic_spi(56),
 746                 .flags  = IORESOURCE_IRQ,
 747         },
 748 };
 749
 750 static struct platform_device pmu_device = {
 751         .name           = "arm-pmu",
 752         .id             = -1,
 753         .num_resources  = ARRAY_SIZE(pmu_resources),
 754         .resource       = pmu_resources,
 755 };
 756
 757 static struct platform_device *sh73a0_early_devices[] __initdata = {
 758         &scif0_device,
 759         &scif1_device,
 760         &scif2_device,
 761         &scif3_device,
 762         &scif4_device,
 763         &scif5_device,
 764         &scif6_device,
 765         &scif7_device,
 766         &scif8_device,
 767         &cmt10_device,
 768         &tmu00_device,
 769         &tmu01_device,
 770 };
 771
 772 static struct platform_device *sh73a0_late_devices[] __initdata = {
 773         &i2c0_device,
 774         &i2c1_device,
 775         &i2c2_device,
 776         &i2c3_device,
 777         &i2c4_device,
 778         &dma0_device,
 779         &mpdma0_device,
 780         &pmu_device,
 781 };
 782
 783 #define SRCR2          IOMEM(0xe61580b0)
 784
 785 void __init sh73a0_add_standard_devices(void)
 786 {
 787         /* Clear software reset bit on SY-DMAC module */
 788         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 789
 790         platform_add_devices(sh73a0_early_devices,
 791                             ARRAY_SIZE(sh73a0_early_devices));
 792         platform_add_devices(sh73a0_late_devices,
 793                             ARRAY_SIZE(sh73a0_late_devices));
 794 }
 795
 796 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 797 void __init __weak sh73a0_register_twd(void) { }
 798
 799 static void __init sh73a0_earlytimer_init(void)
 800 {
 801         sh73a0_clock_init();
 802         shmobile_earlytimer_init();
 803         sh73a0_register_twd();
 804 }
 805
 806 void __init sh73a0_add_early_devices(void)
 807 {
 808         early_platform_add_devices(sh73a0_early_devices,
 809                                    ARRAY_SIZE(sh73a0_early_devices));
 810
 811         /* setup early console here as well */
 812         shmobile_setup_console();
 813
 814         /* override timer setup with soc-specific code */
 815         shmobile_timer.init = sh73a0_earlytimer_init;
 816 }