| blob | 3a3c015f8d5c33cb99357995b6d35790037e7f94 |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
24 #else
25 #include "proc-v7-2level.S"
26 #endif
28 ENTRY(cpu_v7_proc_init)
29 mov pc, lr
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
37 mov pc, lr
38 ENDPROC(cpu_v7_proc_fin)
40 /*
41 * cpu_v7_reset(loc)
42 *
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
46 *
47 * - loc - location to jump to for soft reset
48 *
49 * This code must be executed using a flat identity mapping with
50 * caches disabled.
51 */
52 .align 5
53 .pushsection .idmap.text, "ax"
54 ENTRY(cpu_v7_reset)
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
59 isb
60 bx r0
61 ENDPROC(cpu_v7_reset)
62 .popsection
64 /*
65 * cpu_v7_do_idle()
66 *
67 * Idle the processor (eg, wait for interrupt).
68 *
69 * IRQs are already disabled.
70 */
71 ENTRY(cpu_v7_do_idle)
72 dsb @ WFI may enter a low-power mode
73 wfi
74 mov pc, lr
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 #ifndef TLB_CAN_READ_FROM_L1_CACHE
79 dcache_line_size r2, r3
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
81 add r0, r0, r2
82 subs r1, r1, r2
83 bhi 1b
84 dsb
85 #endif
86 mov pc, lr
87 ENDPROC(cpu_v7_dcache_clean_area)
89 string cpu_v7_name, "ARMv7 Processor"
90 .align
92 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
93 .globl cpu_v7_suspend_size
94 .equ cpu_v7_suspend_size, 4 * 8
95 #ifdef CONFIG_ARM_CPU_SUSPEND
96 ENTRY(cpu_v7_do_suspend)
97 stmfd sp!, {r4 - r10, lr}
98 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
99 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
100 stmia r0!, {r4 - r5}
101 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
102 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
103 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
104 mrc p15, 0, r8, c1, c0, 0 @ Control register
105 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
106 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
107 stmia r0, {r6 - r11}
108 ldmfd sp!, {r4 - r10, pc}
109 ENDPROC(cpu_v7_do_suspend)
111 ENTRY(cpu_v7_do_resume)
112 mov ip, #0
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
114 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
116 ldmia r0!, {r4 - r5}
117 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
118 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
119 ldmia r0, {r6 - r11}
120 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
121 #ifndef CONFIG_ARM_LPAE
122 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
123 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
124 #endif
125 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
126 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
127 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
128 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
129 teq r4, r9 @ Is it already set?
130 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
131 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
132 ldr r4, =PRRR @ PRRR
133 ldr r5, =NMRR @ NMRR
134 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
135 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
136 isb
137 dsb
138 mov r0, r8 @ control register
139 b cpu_resume_mmu
140 ENDPROC(cpu_v7_do_resume)
141 #endif
143 __CPUINIT
145 /*
146 * __v7_setup
147 *
148 * Initialise TLB, Caches, and MMU state ready to switch the MMU
149 * on. Return in r0 the new CP15 C1 control register setting.
150 *
151 * This should be able to cover all ARMv7 cores.
152 *
153 * It is assumed that:
154 * - cache type register is implemented
155 */
156 __v7_ca5mp_setup:
157 __v7_ca9mp_setup:
158 mov r10, #(1 << 0) @ TLB ops broadcasting
159 b 1f
160 __v7_ca7mp_setup:
161 __v7_ca15mp_setup:
162 mov r10, #0
163 1:
164 #ifdef CONFIG_SMP
165 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
166 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
167 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
168 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
169 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
170 mcreq p15, 0, r0, c1, c0, 1
171 #endif
172 b __v7_setup
174 __v7_pj4b_setup:
175 #ifdef CONFIG_CPU_PJ4B
177 /* Auxiliary Debug Modes Control 1 Register */
178 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
179 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
180 #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
181 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
183 /* Auxiliary Debug Modes Control 2 Register */
184 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
185 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
186 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
187 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
188 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
189 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
190 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
192 /* Auxiliary Functional Modes Control Register 0 */
193 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
194 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
195 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
197 /* Auxiliary Debug Modes Control 0 Register */
198 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
200 /* Auxiliary Debug Modes Control 1 Register */
201 mrc p15, 1, r0, c15, c1, 1
202 orr r0, r0, #PJ4B_CLEAN_LINE
203 orr r0, r0, #PJ4B_BCK_OFF_STREX
204 orr r0, r0, #PJ4B_INTER_PARITY
205 bic r0, r0, #PJ4B_STATIC_BP
206 mcr p15, 1, r0, c15, c1, 1
208 /* Auxiliary Debug Modes Control 2 Register */
209 mrc p15, 1, r0, c15, c1, 2
210 bic r0, r0, #PJ4B_FAST_LDR
211 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
212 mcr p15, 1, r0, c15, c1, 2
214 /* Auxiliary Functional Modes Control Register 0 */
215 mrc p15, 1, r0, c15, c2, 0
216 #ifdef CONFIG_SMP
217 orr r0, r0, #PJ4B_SMP_CFB
218 #endif
219 orr r0, r0, #PJ4B_L1_PAR_CHK
220 orr r0, r0, #PJ4B_BROADCAST_CACHE
221 mcr p15, 1, r0, c15, c2, 0
223 /* Auxiliary Debug Modes Control 0 Register */
224 mrc p15, 1, r0, c15, c1, 0
225 orr r0, r0, #PJ4B_WFI_WFE
226 mcr p15, 1, r0, c15, c1, 0
228 #endif /* CONFIG_CPU_PJ4B */
230 __v7_setup:
231 adr r12, __v7_setup_stack @ the local stack
232 stmia r12, {r0-r5, r7, r9, r11, lr}
233 bl v7_flush_dcache_louis
234 ldmia r12, {r0-r5, r7, r9, r11, lr}
236 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
237 and r10, r0, #0xff000000 @ ARM?
238 teq r10, #0x41000000
239 bne 3f
240 and r5, r0, #0x00f00000 @ variant
241 and r6, r0, #0x0000000f @ revision
242 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
243 ubfx r0, r0, #4, #12 @ primary part number
245 /* Cortex-A8 Errata */
246 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
247 teq r0, r10
248 bne 2f
249 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
251 teq r5, #0x00100000 @ only present in r1p*
252 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
253 orreq r10, r10, #(1 << 6) @ set IBE to 1
254 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
255 #endif
256 #ifdef CONFIG_ARM_ERRATA_458693
257 teq r6, #0x20 @ only present in r2p0
258 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
259 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
260 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
261 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
262 #endif
263 #ifdef CONFIG_ARM_ERRATA_460075
264 teq r6, #0x20 @ only present in r2p0
265 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
266 tsteq r10, #1 << 22
267 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
268 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
269 #endif
270 b 3f
272 /* Cortex-A9 Errata */
273 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
274 teq r0, r10
275 bne 3f
276 #ifdef CONFIG_ARM_ERRATA_742230
277 cmp r6, #0x22 @ only present up to r2p2
278 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
279 orrle r10, r10, #1 << 4 @ set bit #4
280 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
281 #endif
282 #ifdef CONFIG_ARM_ERRATA_742231
283 teq r6, #0x20 @ present in r2p0
284 teqne r6, #0x21 @ present in r2p1
285 teqne r6, #0x22 @ present in r2p2
286 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
287 orreq r10, r10, #1 << 12 @ set bit #12
288 orreq r10, r10, #1 << 22 @ set bit #22
289 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
290 #endif
291 #ifdef CONFIG_ARM_ERRATA_743622
292 teq r5, #0x00200000 @ only present in r2p*
293 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
294 orreq r10, r10, #1 << 6 @ set bit #6
295 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
296 #endif
297 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
298 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
299 ALT_UP_B(1f)
300 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
301 orrlt r10, r10, #1 << 11 @ set bit #11
302 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
303 1:
304 #endif
306 3: mov r10, #0
307 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
308 dsb
309 #ifdef CONFIG_MMU
310 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
311 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
312 ldr r5, =PRRR @ PRRR
313 ldr r6, =NMRR @ NMRR
314 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
315 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
316 #endif
317 #ifndef CONFIG_ARM_THUMBEE
318 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
319 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
320 teq r0, #(1 << 12) @ check if ThumbEE is present
321 bne 1f
322 mov r5, #0
323 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
324 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
325 orr r0, r0, #1 @ set the 1st bit in order to
326 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
327 1:
328 #endif
329 adr r5, v7_crval
330 ldmia r5, {r5, r6}
331 #ifdef CONFIG_CPU_ENDIAN_BE8
332 orr r6, r6, #1 << 25 @ big-endian page tables
333 #endif
334 #ifdef CONFIG_SWP_EMULATE
335 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
336 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
337 #endif
338 mrc p15, 0, r0, c1, c0, 0 @ read control register
339 bic r0, r0, r5 @ clear bits them
340 orr r0, r0, r6 @ set them
341 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
342 mov pc, lr @ return to head.S:__ret
343 ENDPROC(__v7_setup)
345 .align 2
346 __v7_setup_stack:
347 .space 4 * 11 @ 11 registers
349 __INITDATA
351 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
352 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
354 .section ".rodata"
356 string cpu_arch_name, "armv7"
357 string cpu_elf_name, "v7"
358 .align
360 .section ".proc.info.init", #alloc, #execinstr
362 /*
363 * Standard v7 proc info content
364 */
365 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
366 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
367 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
368 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
369 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
370 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
371 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
372 W(b) \initfunc
373 .long cpu_arch_name
374 .long cpu_elf_name
375 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
376 HWCAP_EDSP | HWCAP_TLS | \hwcaps
377 .long cpu_v7_name
378 .long v7_processor_functions
379 .long v7wbi_tlb_fns
380 .long v6_user_fns
381 .long v7_cache_fns
382 .endm
384 #ifndef CONFIG_ARM_LPAE
385 /*
386 * ARM Ltd. Cortex A5 processor.
387 */
388 .type __v7_ca5mp_proc_info, #object
389 __v7_ca5mp_proc_info:
390 .long 0x410fc050
391 .long 0xff0ffff0
392 __v7_proc __v7_ca5mp_setup
393 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
395 /*
396 * ARM Ltd. Cortex A9 processor.
397 */
398 .type __v7_ca9mp_proc_info, #object
399 __v7_ca9mp_proc_info:
400 .long 0x410fc090
401 .long 0xff0ffff0
402 __v7_proc __v7_ca9mp_setup
403 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
405 /*
406 * Marvell PJ4B processor.
407 */
408 .type __v7_pj4b_proc_info, #object
409 __v7_pj4b_proc_info:
410 .long 0x562f5840
411 .long 0xfffffff0
412 __v7_proc __v7_pj4b_setup
413 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
414 #endif /* CONFIG_ARM_LPAE */
416 /*
417 * ARM Ltd. Cortex A7 processor.
418 */
419 .type __v7_ca7mp_proc_info, #object
420 __v7_ca7mp_proc_info:
421 .long 0x410fc070
422 .long 0xff0ffff0
423 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
424 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
426 /*
427 * ARM Ltd. Cortex A15 processor.
428 */
429 .type __v7_ca15mp_proc_info, #object
430 __v7_ca15mp_proc_info:
431 .long 0x410fc0f0
432 .long 0xff0ffff0
433 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
434 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
436 /*
437 * Match any ARMv7 processor core.
438 */
439 .type __v7_proc_info, #object
440 __v7_proc_info:
441 .long 0x000f0000 @ Required ID value
442 .long 0x000f0000 @ Mask for ID
443 __v7_proc __v7_setup
444 .size __v7_proc_info, . - __v7_proc_info