arch/m68k/platform/coldfire/m525x.c

   1 /***************************************************************************/
   2
   3 /*
   4  *      525x.c
   5  *
   6  *      Copyright (C) 2012, Steven King <sfking@fdwdc.com>
   7  */
   8
   9 /***************************************************************************/
  10
  11 #include <linux/kernel.h>
  12 #include <linux/param.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/platform_device.h>
  16 #include <asm/machdep.h>
  17 #include <asm/coldfire.h>
  18 #include <asm/mcfsim.h>
  19 #include <asm/mcfclk.h>
  20
  21 /***************************************************************************/
  22
  23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
  24 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  25 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
  26 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
  27 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  28 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  29
  30 struct clk *mcf_clks[] = {
  31         &clk_pll,
  32         &clk_sys,
  33         &clk_mcftmr0,
  34         &clk_mcftmr1,
  35         &clk_mcfuart0,
  36         &clk_mcfuart1,
  37         NULL
  38 };
  39
  40 /***************************************************************************/
  41
  42 static void __init m525x_qspi_init(void)
  43 {
  44 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  45         /* set the GPIO function for the qspi cs gpios */
  46         /* FIXME: replace with pinmux/pinctl support */
  47         u32 f = readl(MCFSIM2_GPIOFUNC);
  48         f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
  49         writel(f, MCFSIM2_GPIOFUNC);
  50
  51         /* QSPI irq setup */
  52         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
  53                MCFSIM_QSPIICR);
  54         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
  55 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  56 }
  57
  58 static void __init m525x_i2c_init(void)
  59 {
  60 #if IS_ENABLED(CONFIG_I2C_COLDFIRE)
  61         u32 r;
  62
  63         /* first I2C controller uses regular irq setup */
  64         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
  65                 MCFSIM_I2CICR);
  66         mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
  67
  68         /* second I2C controller is completely different */
  69         r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  70         r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
  71         r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
  72         writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  73 #endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
  74 }
  75
  76 /***************************************************************************/
  77
  78 void __init config_BSP(char *commandp, int size)
  79 {
  80         mach_sched_init = hw_timer_init;
  81
  82         m525x_qspi_init();
  83         m525x_i2c_init();
  84 }
  85
  86 /***************************************************************************/