arch/m68k/platform/coldfire/m527x.c

   1 /***************************************************************************/
   2
   3 /*
   4  *      linux/arch/m68knommu/platform/527x/config.c
   5  *
   6  *      Sub-architcture dependent initialization code for the Freescale
   7  *      5270/5271 CPUs.
   8  *
   9  *      Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
  10  *      Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
  11  */
  12
  13 /***************************************************************************/
  14
  15 #include <linux/kernel.h>
  16 #include <linux/param.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <asm/machdep.h>
  20 #include <asm/coldfire.h>
  21 #include <asm/mcfsim.h>
  22 #include <asm/mcfuart.h>
  23 #include <asm/mcfclk.h>
  24
  25 /***************************************************************************/
  26
  27 DEFINE_CLK(pll, "pll.0", MCF_CLK);
  28 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  29 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
  30 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
  31 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
  32 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
  33 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  34 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  35 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
  36 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
  37 DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
  38
  39 struct clk *mcf_clks[] = {
  40         &clk_pll,
  41         &clk_sys,
  42         &clk_mcfpit0,
  43         &clk_mcfpit1,
  44         &clk_mcfpit2,
  45         &clk_mcfpit3,
  46         &clk_mcfuart0,
  47         &clk_mcfuart1,
  48         &clk_mcfuart2,
  49         &clk_fec0,
  50         &clk_fec1,
  51         NULL
  52 };
  53
  54 /***************************************************************************/
  55
  56 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  57
  58 static void __init m527x_qspi_init(void)
  59 {
  60 #if defined(CONFIG_M5271)
  61         u16 par;
  62
  63         /* setup QSPS pins for QSPI with gpio CS control */
  64         writeb(0x1f, MCFGPIO_PAR_QSPI);
  65         /* and CS2 & CS3 as gpio */
  66         par = readw(MCFGPIO_PAR_TIMER);
  67         par &= 0x3f3f;
  68         writew(par, MCFGPIO_PAR_TIMER);
  69 #elif defined(CONFIG_M5275)
  70         /* setup QSPS pins for QSPI with gpio CS control */
  71         writew(0x003e, MCFGPIO_PAR_QSPI);
  72 #endif
  73 }
  74
  75 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  76
  77 /***************************************************************************/
  78
  79 static void __init m527x_uarts_init(void)
  80 {
  81         u16 sepmask;
  82
  83         /*
  84          * External Pin Mask Setting & Enable External Pin for Interface
  85          */
  86         sepmask = readw(MCFGPIO_PAR_UART);
  87         sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
  88         writew(sepmask, MCFGPIO_PAR_UART);
  89 }
  90
  91 /***************************************************************************/
  92
  93 static void __init m527x_fec_init(void)
  94 {
  95         u16 par;
  96         u8 v;
  97
  98         /* Set multi-function pins to ethernet mode for fec0 */
  99 #if defined(CONFIG_M5271)
 100         v = readb(MCFGPIO_PAR_FECI2C);
 101         writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
 102 #else
 103         par = readw(MCFGPIO_PAR_FECI2C);
 104         writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
 105         v = readb(MCFGPIO_PAR_FEC0HL);
 106         writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
 107
 108         /* Set multi-function pins to ethernet mode for fec1 */
 109         par = readw(MCFGPIO_PAR_FECI2C);
 110         writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
 111         v = readb(MCFGPIO_PAR_FEC1HL);
 112         writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
 113 #endif
 114 }
 115
 116 /***************************************************************************/
 117
 118 void __init config_BSP(char *commandp, int size)
 119 {
 120         mach_sched_init = hw_timer_init;
 121         m527x_uarts_init();
 122         m527x_fec_init();
 123 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 124         m527x_qspi_init();
 125 #endif
 126 }
 127
 128 /***************************************************************************/