2 * pci.c -- PCI bus support for ColdFire processors
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <asm/coldfire.h>
21 #include <asm/mcfsim.h>
22 #include <asm/m54xxpci.h>
25 * Memory and IO mappings. We use a 1:1 mapping for local host memory to
26 * PCI bus memory (no reason not to really). IO space doesn't matter, we
27 * always use access functions for that. The device configuration space is
28 * mapped over the IO map space when we enable it in the PCICAR register.
30 #define PCI_MEM_PA 0xf0000000 /* Host physical address */
31 #define PCI_MEM_BA 0xf0000000 /* Bus physical address */
32 #define PCI_MEM_SIZE 0x08000000 /* 128 MB */
33 #define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
35 #define PCI_IO_PA 0xf8000000 /* Host physical address */
36 #define PCI_IO_BA 0x00000000 /* Bus physical address */
37 #define PCI_IO_SIZE 0x00010000 /* 64k */
38 #define PCI_IO_MASK (PCI_IO_SIZE - 1)
40 static struct pci_bus
*rootbus
;
41 static unsigned long iospace
;
44 * We need to be carefull probing on bus 0 (directly connected to host
45 * bridge). We should only acccess the well defined possible devices in
46 * use, ignore aliases and the like.
48 static unsigned char mcf_host_slot2sid
[32] = {
49 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0,
51 0, 1, 2, 0, 3, 4, 0, 0,
52 0, 0, 0, 0, 0, 0, 0, 0,
55 static unsigned char mcf_host_irq
[] = {
60 static inline void syncio(void)
62 /* The ColdFire "nop" instruction waits for all bus IO to complete */
63 __asm__
__volatile__ ("nop");
67 * Configuration space access functions. Configuration space access is
68 * through the IO mapping window, enabling it via the PCICAR register.
70 static unsigned long mcf_mk_pcicar(int bus
, unsigned int devfn
, int where
)
72 return (bus
<< PCICAR_BUSN
) | (devfn
<< PCICAR_DEVFNN
) | (where
& 0xfc);
75 static int mcf_pci_readconfig(struct pci_bus
*bus
, unsigned int devfn
,
76 int where
, int size
, u32
*value
)
82 if (bus
->number
== 0) {
83 if (mcf_host_slot2sid
[PCI_SLOT(devfn
)] == 0)
84 return PCIBIOS_SUCCESSFUL
;
88 addr
= mcf_mk_pcicar(bus
->number
, devfn
, where
);
89 __raw_writel(PCICAR_E
| addr
, PCICAR
);
90 addr
= iospace
+ (where
& 0x3);
94 *value
= __raw_readb(addr
);
97 *value
= le16_to_cpu(__raw_readw(addr
));
100 *value
= le32_to_cpu(__raw_readl(addr
));
105 __raw_writel(0, PCICAR
);
106 return PCIBIOS_SUCCESSFUL
;
109 static int mcf_pci_writeconfig(struct pci_bus
*bus
, unsigned int devfn
,
110 int where
, int size
, u32 value
)
114 if (bus
->number
== 0) {
115 if (mcf_host_slot2sid
[PCI_SLOT(devfn
)] == 0)
116 return PCIBIOS_SUCCESSFUL
;
120 addr
= mcf_mk_pcicar(bus
->number
, devfn
, where
);
121 __raw_writel(PCICAR_E
| addr
, PCICAR
);
122 addr
= iospace
+ (where
& 0x3);
126 __raw_writeb(value
, addr
);
129 __raw_writew(cpu_to_le16(value
), addr
);
132 __raw_writel(cpu_to_le32(value
), addr
);
137 __raw_writel(0, PCICAR
);
138 return PCIBIOS_SUCCESSFUL
;
141 static struct pci_ops mcf_pci_ops
= {
142 .read
= mcf_pci_readconfig
,
143 .write
= mcf_pci_writeconfig
,
147 * IO address space access functions. Pretty strait forward, these are
148 * directly mapped in to the IO mapping window. And that is mapped into
149 * virtual address space.
151 u8
mcf_pci_inb(u32 addr
)
153 return __raw_readb(iospace
+ (addr
& PCI_IO_MASK
));
155 EXPORT_SYMBOL(mcf_pci_inb
);
157 u16
mcf_pci_inw(u32 addr
)
159 return le16_to_cpu(__raw_readw(iospace
+ (addr
& PCI_IO_MASK
)));
161 EXPORT_SYMBOL(mcf_pci_inw
);
163 u32
mcf_pci_inl(u32 addr
)
165 return le32_to_cpu(__raw_readl(iospace
+ (addr
& PCI_IO_MASK
)));
167 EXPORT_SYMBOL(mcf_pci_inl
);
169 void mcf_pci_insb(u32 addr
, u8
*buf
, u32 len
)
172 *buf
++ = mcf_pci_inb(addr
);
174 EXPORT_SYMBOL(mcf_pci_insb
);
176 void mcf_pci_insw(u32 addr
, u16
*buf
, u32 len
)
179 *buf
++ = mcf_pci_inw(addr
);
181 EXPORT_SYMBOL(mcf_pci_insw
);
183 void mcf_pci_insl(u32 addr
, u32
*buf
, u32 len
)
186 *buf
++ = mcf_pci_inl(addr
);
188 EXPORT_SYMBOL(mcf_pci_insl
);
190 void mcf_pci_outb(u8 v
, u32 addr
)
192 __raw_writeb(v
, iospace
+ (addr
& PCI_IO_MASK
));
194 EXPORT_SYMBOL(mcf_pci_outb
);
196 void mcf_pci_outw(u16 v
, u32 addr
)
198 __raw_writew(cpu_to_le16(v
), iospace
+ (addr
& PCI_IO_MASK
));
200 EXPORT_SYMBOL(mcf_pci_outw
);
202 void mcf_pci_outl(u32 v
, u32 addr
)
204 __raw_writel(cpu_to_le32(v
), iospace
+ (addr
& PCI_IO_MASK
));
206 EXPORT_SYMBOL(mcf_pci_outl
);
208 void mcf_pci_outsb(u32 addr
, const u8
*buf
, u32 len
)
211 mcf_pci_outb(*buf
++, addr
);
213 EXPORT_SYMBOL(mcf_pci_outsb
);
215 void mcf_pci_outsw(u32 addr
, const u16
*buf
, u32 len
)
218 mcf_pci_outw(*buf
++, addr
);
220 EXPORT_SYMBOL(mcf_pci_outsw
);
222 void mcf_pci_outsl(u32 addr
, const u32
*buf
, u32 len
)
225 mcf_pci_outl(*buf
++, addr
);
227 EXPORT_SYMBOL(mcf_pci_outsl
);
230 * Initialize the PCI bus registers, and scan the bus.
232 static struct resource mcf_pci_mem
= {
233 .name
= "PCI Memory space",
235 .end
= PCI_MEM_PA
+ PCI_MEM_SIZE
- 1,
236 .flags
= IORESOURCE_MEM
,
239 static struct resource mcf_pci_io
= {
240 .name
= "PCI IO space",
243 .flags
= IORESOURCE_IO
,
247 * Interrupt mapping and setting.
249 static int mcf_pci_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
253 sid
= mcf_host_slot2sid
[slot
];
255 return mcf_host_irq
[sid
];
259 static int __init
mcf_pci_init(void)
261 pr_info("ColdFire: PCI bus initialization...\n");
263 /* Reset the external PCI bus */
264 __raw_writel(PCIGSCR_RESET
, PCIGSCR
);
265 __raw_writel(0, PCITCR
);
267 request_resource(&iomem_resource
, &mcf_pci_mem
);
268 request_resource(&iomem_resource
, &mcf_pci_io
);
270 /* Configure PCI arbiter */
271 __raw_writel(PACR_INTMPRI
| PACR_INTMINTE
| PACR_EXTMPRI(0x1f) |
272 PACR_EXTMINTE(0x1f), PACR
);
274 /* Set required multi-function pins for PCI bus use */
275 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG
);
276 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR
);
278 /* Set up config space for local host bus controller */
279 __raw_writel(PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
280 PCI_COMMAND_INVALIDATE
, PCISCR
);
281 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1
);
282 __raw_writel(0, PCICR2
);
285 * Set up the initiator windows for memory and IO mapping.
286 * These give the CPU bus access onto the PCI bus. One for each of
287 * PCI memory and IO address spaces.
289 __raw_writel(WXBTAR(PCI_MEM_PA
, PCI_MEM_BA
, PCI_MEM_SIZE
),
291 __raw_writel(WXBTAR(PCI_IO_PA
, PCI_IO_BA
, PCI_IO_SIZE
),
293 __raw_writel(PCIIWCR_W0_MEM
/*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E
|
294 PCIIWCR_W1_IO
| PCIIWCR_W1_E
, PCIIWCR
);
297 * Set up the target windows for access from the PCI bus back to the
298 * CPU bus. All we need is access to system RAM (for mastering).
300 __raw_writel(CONFIG_RAMBASE
, PCIBAR1
);
301 __raw_writel(CONFIG_RAMBASE
| PCITBATR1_E
, PCITBATR1
);
303 /* Keep a virtual mapping to IO/config space active */
304 iospace
= (unsigned long) ioremap(PCI_IO_PA
, PCI_IO_SIZE
);
307 pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
310 /* Turn of PCI reset, and wait for devices to settle */
311 __raw_writel(0, PCIGSCR
);
312 set_current_state(TASK_UNINTERRUPTIBLE
);
313 schedule_timeout(msecs_to_jiffies(200));
315 rootbus
= pci_scan_bus(0, &mcf_pci_ops
, NULL
);
316 rootbus
->resource
[0] = &mcf_pci_io
;
317 rootbus
->resource
[1] = &mcf_pci_mem
;
319 pci_fixup_irqs(pci_common_swizzle
, mcf_pci_map_irq
);
320 pci_bus_size_bridges(rootbus
);
321 pci_bus_assign_resources(rootbus
);
322 pci_enable_bridges(rootbus
);
323 pci_bus_add_devices(rootbus
);
327 subsys_initcall(mcf_pci_init
);