| blob | 116f0868695bc65a689d0759f9391247dc14eed3 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the entry point for the 64-bit kernel along
16 * with some early initialization code common to all 64-bit powerpc
17 * variants.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
25 #include <linux/threads.h>
26 #include <asm/reg.h>
27 #include <asm/page.h>
28 #include <asm/mmu.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/bug.h>
32 #include <asm/cputable.h>
33 #include <asm/setup.h>
34 #include <asm/hvcall.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37 #include <asm/page_64.h>
38 #include <asm/irqflags.h>
39 #include <asm/kvm_book3s_asm.h>
40 #include <asm/ptrace.h>
41 #include <asm/hw_irq.h>
43 /* The physical memory is laid out such that the secondary processor
44 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
45 * using the layout described in exceptions-64s.S
46 */
48 /*
49 * Entering into this code we make the following assumptions:
50 *
51 * For pSeries or server processors:
52 * 1. The MMU is off & open firmware is running in real mode.
53 * 2. The kernel is entered at __start
54 * -or- For OPAL entry:
55 * 1. The MMU is off, processor in HV mode, primary CPU enters at 0
56 * with device-tree in gpr3. We also get OPAL base in r8 and
57 * entry in r9 for debugging purposes
58 * 2. Secondary processors enter at 0x60 with PIR in gpr3
59 *
60 * For Book3E processors:
61 * 1. The MMU is on running in AS0 in a state defined in ePAPR
62 * 2. The kernel is entered at __start
63 */
65 .text
66 .globl _stext
67 _stext:
68 _GLOBAL(__start)
69 /* NOP this out unconditionally */
70 BEGIN_FTR_SECTION
71 b .__start_initialization_multiplatform
72 END_FTR_SECTION(0, 1)
74 /* Catch branch to 0 in real mode */
75 trap
77 /* Secondary processors spin on this value until it becomes nonzero.
78 * When it does it contains the real address of the descriptor
79 * of the function that the cpu should jump to to continue
80 * initialization.
81 */
82 .globl __secondary_hold_spinloop
83 __secondary_hold_spinloop:
84 .llong 0x0
86 /* Secondary processors write this value with their cpu # */
87 /* after they enter the spin loop immediately below. */
88 .globl __secondary_hold_acknowledge
89 __secondary_hold_acknowledge:
90 .llong 0x0
92 #ifdef CONFIG_RELOCATABLE
93 /* This flag is set to 1 by a loader if the kernel should run
94 * at the loaded address instead of the linked address. This
95 * is used by kexec-tools to keep the the kdump kernel in the
96 * crash_kernel region. The loader is responsible for
97 * observing the alignment requirement.
98 */
99 /* Do not move this variable as kexec-tools knows about it. */
100 . = 0x5c
101 .globl __run_at_load
102 __run_at_load:
103 .long 0x72756e30 /* "run0" -- relocate to 0 by default */
104 #endif
106 . = 0x60
107 /*
108 * The following code is used to hold secondary processors
109 * in a spin loop after they have entered the kernel, but
110 * before the bulk of the kernel has been relocated. This code
111 * is relocated to physical address 0x60 before prom_init is run.
112 * All of it must fit below the first exception vector at 0x100.
113 * Use .globl here not _GLOBAL because we want __secondary_hold
114 * to be the actual text address, not a descriptor.
115 */
116 .globl __secondary_hold
117 __secondary_hold:
118 #ifndef CONFIG_PPC_BOOK3E
119 mfmsr r24
120 ori r24,r24,MSR_RI
121 mtmsrd r24 /* RI on */
122 #endif
123 /* Grab our physical cpu number */
124 mr r24,r3
126 /* Tell the master cpu we're here */
127 /* Relocation is off & we are located at an address less */
128 /* than 0x100, so only need to grab low order offset. */
129 std r24,__secondary_hold_acknowledge-_stext(0)
130 sync
132 /* All secondary cpus wait here until told to start. */
133 100: ld r4,__secondary_hold_spinloop-_stext(0)
134 cmpdi 0,r4,0
135 beq 100b
137 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
138 ld r4,0(r4) /* deref function descriptor */
139 mtctr r4
140 mr r3,r24
141 li r4,0
142 /* Make sure that patched code is visible */
143 isync
144 bctr
145 #else
146 BUG_OPCODE
147 #endif
149 /* This value is used to mark exception frames on the stack. */
150 .section ".toc","aw"
151 exception_marker:
152 .tc ID_72656773_68657265[TC],0x7265677368657265
153 .text
155 /*
156 * On server, we include the exception vectors code here as it
157 * relies on absolute addressing which is only possible within
158 * this compilation unit
159 */
160 #ifdef CONFIG_PPC_BOOK3S
161 #include "exceptions-64s.S"
162 #endif
164 _GLOBAL(generic_secondary_thread_init)
165 mr r24,r3
167 /* turn on 64-bit mode */
168 bl .enable_64b_mode
170 /* get a valid TOC pointer, wherever we're mapped at */
171 bl .relative_toc
173 #ifdef CONFIG_PPC_BOOK3E
174 /* Book3E initialization */
175 mr r3,r24
176 bl .book3e_secondary_thread_init
177 #endif
178 b generic_secondary_common_init
180 /*
181 * On pSeries and most other platforms, secondary processors spin
182 * in the following code.
183 * At entry, r3 = this processor's number (physical cpu id)
184 *
185 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
186 * this core already exists (setup via some other mechanism such
187 * as SCOM before entry).
188 */
189 _GLOBAL(generic_secondary_smp_init)
190 mr r24,r3
191 mr r25,r4
193 /* turn on 64-bit mode */
194 bl .enable_64b_mode
196 /* get a valid TOC pointer, wherever we're mapped at */
197 bl .relative_toc
199 #ifdef CONFIG_PPC_BOOK3E
200 /* Book3E initialization */
201 mr r3,r24
202 mr r4,r25
203 bl .book3e_secondary_core_init
204 #endif
206 generic_secondary_common_init:
207 /* Set up a paca value for this processor. Since we have the
208 * physical cpu id in r24, we need to search the pacas to find
209 * which logical id maps to our physical one.
210 */
211 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
212 ld r13,0(r13) /* Get base vaddr of paca array */
213 #ifndef CONFIG_SMP
214 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */
215 b .kexec_wait /* wait for next kernel if !SMP */
216 #else
217 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
218 lwz r7,0(r7) /* also the max paca allocated */
219 li r5,0 /* logical cpu id */
220 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
221 cmpw r6,r24 /* Compare to our id */
222 beq 2f
223 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
224 addi r5,r5,1
225 cmpw r5,r7 /* Check if more pacas exist */
226 blt 1b
228 mr r3,r24 /* not found, copy phys to r3 */
229 b .kexec_wait /* next kernel might do better */
231 2: SET_PACA(r13)
232 #ifdef CONFIG_PPC_BOOK3E
233 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
234 mtspr SPRN_SPRG_TLB_EXFRAME,r12
235 #endif
237 /* From now on, r24 is expected to be logical cpuid */
238 mr r24,r5
240 /* See if we need to call a cpu state restore handler */
241 LOAD_REG_ADDR(r23, cur_cpu_spec)
242 ld r23,0(r23)
243 ld r23,CPU_SPEC_RESTORE(r23)
244 cmpdi 0,r23,0
245 beq 3f
246 ld r23,0(r23)
247 mtctr r23
248 bctrl
250 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
251 lwarx r4,0,r3
252 subi r4,r4,1
253 stwcx. r4,0,r3
254 bne 3b
255 isync
257 4: HMT_LOW
258 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
259 /* start. */
260 cmpwi 0,r23,0
261 beq 4b /* Loop until told to go */
263 sync /* order paca.run and cur_cpu_spec */
264 isync /* In case code patching happened */
266 /* Create a temp kernel stack for use before relocation is on. */
267 ld r1,PACAEMERGSP(r13)
268 subi r1,r1,STACK_FRAME_OVERHEAD
270 b __secondary_start
271 #endif /* SMP */
273 /*
274 * Turn the MMU off.
275 * Assumes we're mapped EA == RA if the MMU is on.
276 */
277 #ifdef CONFIG_PPC_BOOK3S
278 _STATIC(__mmu_off)
279 mfmsr r3
280 andi. r0,r3,MSR_IR|MSR_DR
281 beqlr
282 mflr r4
283 andc r3,r3,r0
284 mtspr SPRN_SRR0,r4
285 mtspr SPRN_SRR1,r3
286 sync
287 rfid
288 b . /* prevent speculative execution */
289 #endif
292 /*
293 * Here is our main kernel entry point. We support currently 2 kind of entries
294 * depending on the value of r5.
295 *
296 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
297 * in r3...r7
298 *
299 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
300 * DT block, r4 is a physical pointer to the kernel itself
301 *
302 */
303 _GLOBAL(__start_initialization_multiplatform)
304 /* Make sure we are running in 64 bits mode */
305 bl .enable_64b_mode
307 /* Get TOC pointer (current runtime address) */
308 bl .relative_toc
310 /* find out where we are now */
311 bcl 20,31,$+4
312 0: mflr r26 /* r26 = runtime addr here */
313 addis r26,r26,(_stext - 0b)@ha
314 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
316 /*
317 * Are we booted from a PROM Of-type client-interface ?
318 */
319 cmpldi cr0,r5,0
320 beq 1f
321 b .__boot_from_prom /* yes -> prom */
322 1:
323 /* Save parameters */
324 mr r31,r3
325 mr r30,r4
326 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
327 /* Save OPAL entry */
328 mr r28,r8
329 mr r29,r9
330 #endif
332 #ifdef CONFIG_PPC_BOOK3E
333 bl .start_initialization_book3e
334 b .__after_prom_start
335 #else
336 /* Setup some critical 970 SPRs before switching MMU off */
337 mfspr r0,SPRN_PVR
338 srwi r0,r0,16
339 cmpwi r0,0x39 /* 970 */
340 beq 1f
341 cmpwi r0,0x3c /* 970FX */
342 beq 1f
343 cmpwi r0,0x44 /* 970MP */
344 beq 1f
345 cmpwi r0,0x45 /* 970GX */
346 bne 2f
347 1: bl .__cpu_preinit_ppc970
348 2:
350 /* Switch off MMU if not already off */
351 bl .__mmu_off
352 b .__after_prom_start
353 #endif /* CONFIG_PPC_BOOK3E */
355 _INIT_STATIC(__boot_from_prom)
356 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
357 /* Save parameters */
358 mr r31,r3
359 mr r30,r4
360 mr r29,r5
361 mr r28,r6
362 mr r27,r7
364 /*
365 * Align the stack to 16-byte boundary
366 * Depending on the size and layout of the ELF sections in the initial
367 * boot binary, the stack pointer may be unaligned on PowerMac
368 */
369 rldicr r1,r1,0,59
371 #ifdef CONFIG_RELOCATABLE
372 /* Relocate code for where we are now */
373 mr r3,r26
374 bl .relocate
375 #endif
377 /* Restore parameters */
378 mr r3,r31
379 mr r4,r30
380 mr r5,r29
381 mr r6,r28
382 mr r7,r27
384 /* Do all of the interaction with OF client interface */
385 mr r8,r26
386 bl .prom_init
387 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
389 /* We never return. We also hit that trap if trying to boot
390 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
391 trap
393 _STATIC(__after_prom_start)
394 #ifdef CONFIG_RELOCATABLE
395 /* process relocations for the final address of the kernel */
396 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
397 sldi r25,r25,32
398 lwz r7,__run_at_load-_stext(r26)
399 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
400 bne 1f
401 add r25,r25,r26
402 1: mr r3,r25
403 bl .relocate
404 #endif
406 /*
407 * We need to run with _stext at physical address PHYSICAL_START.
408 * This will leave some code in the first 256B of
409 * real memory, which are reserved for software use.
410 *
411 * Note: This process overwrites the OF exception vectors.
412 */
413 li r3,0 /* target addr */
414 #ifdef CONFIG_PPC_BOOK3E
415 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
416 #endif
417 mr. r4,r26 /* In some cases the loader may */
418 beq 9f /* have already put us at zero */
419 li r6,0x100 /* Start offset, the first 0x100 */
420 /* bytes were copied earlier. */
421 #ifdef CONFIG_PPC_BOOK3E
422 tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */
423 #endif
425 #ifdef CONFIG_RELOCATABLE
426 /*
427 * Check if the kernel has to be running as relocatable kernel based on the
428 * variable __run_at_load, if it is set the kernel is treated as relocatable
429 * kernel, otherwise it will be moved to PHYSICAL_START
430 */
431 lwz r7,__run_at_load-_stext(r26)
432 cmplwi cr0,r7,1
433 bne 3f
435 /* just copy interrupts */
436 LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext)
437 b 5f
438 3:
439 #endif
440 lis r5,(copy_to_here - _stext)@ha
441 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */
443 bl .copy_and_flush /* copy the first n bytes */
444 /* this includes the code being */
445 /* executed here. */
446 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */
447 addi r8,r8,(4f - _stext)@l /* that we just made */
448 mtctr r8
449 bctr
451 p_end: .llong _end - _stext
453 4: /* Now copy the rest of the kernel up to _end */
454 addis r5,r26,(p_end - _stext)@ha
455 ld r5,(p_end - _stext)@l(r5) /* get _end */
456 5: bl .copy_and_flush /* copy the rest */
458 9: b .start_here_multiplatform
460 /*
461 * Copy routine used to copy the kernel to start at physical address 0
462 * and flush and invalidate the caches as needed.
463 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
464 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
465 *
466 * Note: this routine *only* clobbers r0, r6 and lr
467 */
468 _GLOBAL(copy_and_flush)
469 addi r5,r5,-8
470 addi r6,r6,-8
471 4: li r0,8 /* Use the smallest common */
472 /* denominator cache line */
473 /* size. This results in */
474 /* extra cache line flushes */
475 /* but operation is correct. */
476 /* Can't get cache line size */
477 /* from NACA as it is being */
478 /* moved too. */
480 mtctr r0 /* put # words/line in ctr */
481 3: addi r6,r6,8 /* copy a cache line */
482 ldx r0,r6,r4
483 stdx r0,r6,r3
484 bdnz 3b
485 dcbst r6,r3 /* write it to memory */
486 sync
487 icbi r6,r3 /* flush the icache line */
488 cmpld 0,r6,r5
489 blt 4b
490 sync
491 addi r5,r5,8
492 addi r6,r6,8
493 blr
495 .align 8
496 copy_to_here:
498 #ifdef CONFIG_SMP
499 #ifdef CONFIG_PPC_PMAC
500 /*
501 * On PowerMac, secondary processors starts from the reset vector, which
502 * is temporarily turned into a call to one of the functions below.
503 */
504 .section ".text";
505 .align 2 ;
507 .globl __secondary_start_pmac_0
508 __secondary_start_pmac_0:
509 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
510 li r24,0
511 b 1f
512 li r24,1
513 b 1f
514 li r24,2
515 b 1f
516 li r24,3
517 1:
519 _GLOBAL(pmac_secondary_start)
520 /* turn on 64-bit mode */
521 bl .enable_64b_mode
523 li r0,0
524 mfspr r3,SPRN_HID4
525 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
526 sync
527 mtspr SPRN_HID4,r3
528 isync
529 sync
530 slbia
532 /* get TOC pointer (real address) */
533 bl .relative_toc
535 /* Copy some CPU settings from CPU 0 */
536 bl .__restore_cpu_ppc970
538 /* pSeries do that early though I don't think we really need it */
539 mfmsr r3
540 ori r3,r3,MSR_RI
541 mtmsrd r3 /* RI on */
543 /* Set up a paca value for this processor. */
544 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */
545 ld r4,0(r4) /* Get base vaddr of paca array */
546 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
547 add r13,r13,r4 /* for this processor. */
548 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
550 /* Mark interrupts soft and hard disabled (they might be enabled
551 * in the PACA when doing hotplug)
552 */
553 li r0,0
554 stb r0,PACASOFTIRQEN(r13)
555 li r0,PACA_IRQ_HARD_DIS
556 stb r0,PACAIRQHAPPENED(r13)
558 /* Create a temp kernel stack for use before relocation is on. */
559 ld r1,PACAEMERGSP(r13)
560 subi r1,r1,STACK_FRAME_OVERHEAD
562 b __secondary_start
564 #endif /* CONFIG_PPC_PMAC */
566 /*
567 * This function is called after the master CPU has released the
568 * secondary processors. The execution environment is relocation off.
569 * The paca for this processor has the following fields initialized at
570 * this point:
571 * 1. Processor number
572 * 2. Segment table pointer (virtual address)
573 * On entry the following are set:
574 * r1 = stack pointer (real addr of temp stack)
575 * r24 = cpu# (in Linux terms)
576 * r13 = paca virtual address
577 * SPRG_PACA = paca virtual address
578 */
579 .section ".text";
580 .align 2 ;
582 .globl __secondary_start
583 __secondary_start:
584 /* Set thread priority to MEDIUM */
585 HMT_MEDIUM
587 /* Initialize the kernel stack */
588 LOAD_REG_ADDR(r3, current_set)
589 sldi r28,r24,3 /* get current_set[cpu#] */
590 ldx r14,r3,r28
591 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
592 std r14,PACAKSAVE(r13)
594 /* Do early setup for that CPU (stab, slb, hash table pointer) */
595 bl .early_setup_secondary
597 /*
598 * setup the new stack pointer, but *don't* use this until
599 * translation is on.
600 */
601 mr r1, r14
603 /* Clear backchain so we get nice backtraces */
604 li r7,0
605 mtlr r7
607 /* Mark interrupts soft and hard disabled (they might be enabled
608 * in the PACA when doing hotplug)
609 */
610 stb r7,PACASOFTIRQEN(r13)
611 li r0,PACA_IRQ_HARD_DIS
612 stb r0,PACAIRQHAPPENED(r13)
614 /* enable MMU and jump to start_secondary */
615 LOAD_REG_ADDR(r3, .start_secondary_prolog)
616 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
618 mtspr SPRN_SRR0,r3
619 mtspr SPRN_SRR1,r4
620 RFI
621 b . /* prevent speculative execution */
623 /*
624 * Running with relocation on at this point. All we want to do is
625 * zero the stack back-chain pointer and get the TOC virtual address
626 * before going into C code.
627 */
628 _GLOBAL(start_secondary_prolog)
629 ld r2,PACATOC(r13)
630 li r3,0
631 std r3,0(r1) /* Zero the stack frame pointer */
632 bl .start_secondary
633 b .
634 /*
635 * Reset stack pointer and call start_secondary
636 * to continue with online operation when woken up
637 * from cede in cpu offline.
638 */
639 _GLOBAL(start_secondary_resume)
640 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
641 li r3,0
642 std r3,0(r1) /* Zero the stack frame pointer */
643 bl .start_secondary
644 b .
645 #endif
647 /*
648 * This subroutine clobbers r11 and r12
649 */
650 _GLOBAL(enable_64b_mode)
651 mfmsr r11 /* grab the current MSR */
652 #ifdef CONFIG_PPC_BOOK3E
653 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
654 mtmsr r11
655 #else /* CONFIG_PPC_BOOK3E */
656 li r12,(MSR_64BIT | MSR_ISF)@highest
657 sldi r12,r12,48
658 or r11,r11,r12
659 mtmsrd r11
660 isync
661 #endif
662 blr
664 /*
665 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
666 * by the toolchain). It computes the correct value for wherever we
667 * are running at the moment, using position-independent code.
668 */
669 _GLOBAL(relative_toc)
670 mflr r0
671 bcl 20,31,$+4
672 0: mflr r11
673 ld r2,(p_toc - 0b)(r11)
674 add r2,r2,r11
675 mtlr r0
676 blr
678 p_toc: .llong __toc_start + 0x8000 - 0b
680 /*
681 * This is where the main kernel code starts.
682 */
683 _INIT_STATIC(start_here_multiplatform)
684 /* set up the TOC (real address) */
685 bl .relative_toc
687 /* Clear out the BSS. It may have been done in prom_init,
688 * already but that's irrelevant since prom_init will soon
689 * be detached from the kernel completely. Besides, we need
690 * to clear it now for kexec-style entry.
691 */
692 LOAD_REG_ADDR(r11,__bss_stop)
693 LOAD_REG_ADDR(r8,__bss_start)
694 sub r11,r11,r8 /* bss size */
695 addi r11,r11,7 /* round up to an even double word */
696 srdi. r11,r11,3 /* shift right by 3 */
697 beq 4f
698 addi r8,r8,-8
699 li r0,0
700 mtctr r11 /* zero this many doublewords */
701 3: stdu r0,8(r8)
702 bdnz 3b
703 4:
705 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
706 /* Setup OPAL entry */
707 LOAD_REG_ADDR(r11, opal)
708 std r28,0(r11);
709 std r29,8(r11);
710 #endif
712 #ifndef CONFIG_PPC_BOOK3E
713 mfmsr r6
714 ori r6,r6,MSR_RI
715 mtmsrd r6 /* RI on */
716 #endif
718 #ifdef CONFIG_RELOCATABLE
719 /* Save the physical address we're running at in kernstart_addr */
720 LOAD_REG_ADDR(r4, kernstart_addr)
721 clrldi r0,r25,2
722 std r0,0(r4)
723 #endif
725 /* The following gets the stack set up with the regs */
726 /* pointing to the real addr of the kernel stack. This is */
727 /* all done to support the C function call below which sets */
728 /* up the htab. This is done because we have relocated the */
729 /* kernel but are still running in real mode. */
731 LOAD_REG_ADDR(r3,init_thread_union)
733 /* set up a stack pointer */
734 addi r1,r3,THREAD_SIZE
735 li r0,0
736 stdu r0,-STACK_FRAME_OVERHEAD(r1)
738 /* Do very early kernel initializations, including initial hash table,
739 * stab and slb setup before we turn on relocation. */
741 /* Restore parameters passed from prom_init/kexec */
742 mr r3,r31
743 bl .early_setup /* also sets r13 and SPRG_PACA */
745 LOAD_REG_ADDR(r3, .start_here_common)
746 ld r4,PACAKMSR(r13)
747 mtspr SPRN_SRR0,r3
748 mtspr SPRN_SRR1,r4
749 RFI
750 b . /* prevent speculative execution */
752 /* This is where all platforms converge execution */
753 _INIT_GLOBAL(start_here_common)
754 /* relocation is on at this point */
755 std r1,PACAKSAVE(r13)
757 /* Load the TOC (virtual address) */
758 ld r2,PACATOC(r13)
760 /* Do more system initializations in virtual mode */
761 bl .setup_system
763 /* Mark interrupts soft and hard disabled (they might be enabled
764 * in the PACA when doing hotplug)
765 */
766 li r0,0
767 stb r0,PACASOFTIRQEN(r13)
768 li r0,PACA_IRQ_HARD_DIS
769 stb r0,PACAIRQHAPPENED(r13)
771 /* Generic kernel entry */
772 bl .start_kernel
774 /* Not reached */
775 BUG_OPCODE
777 /*
778 * We put a few things here that have to be page-aligned.
779 * This stuff goes at the beginning of the bss, which is page-aligned.
780 */
781 .section ".bss"
783 .align PAGE_SHIFT
785 .globl empty_zero_page
786 empty_zero_page:
787 .space PAGE_SIZE
789 .globl swapper_pg_dir
790 swapper_pg_dir:
791 .space PGD_TABLE_SIZE