| blob | 5cfa8008693b83aaae96dd4f5d91a7e8190d234b |
1 /*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 */
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
21 #include <asm/page.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
27 #include <asm/kexec.h>
28 #include <asm/ptrace.h>
30 .text
32 _GLOBAL(call_do_softirq)
33 mflr r0
34 std r0,16(r1)
35 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
36 mr r1,r3
37 bl .__do_softirq
38 ld r1,0(r1)
39 ld r0,16(r1)
40 mtlr r0
41 blr
43 _GLOBAL(call_handle_irq)
44 ld r8,0(r6)
45 mflr r0
46 std r0,16(r1)
47 mtctr r8
48 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
49 mr r1,r5
50 bctrl
51 ld r1,0(r1)
52 ld r0,16(r1)
53 mtlr r0
54 blr
56 .section ".toc","aw"
57 PPC64_CACHES:
58 .tc ppc64_caches[TC],ppc64_caches
59 .section ".text"
61 /*
62 * Write any modified data cache blocks out to memory
63 * and invalidate the corresponding instruction cache blocks.
64 *
65 * flush_icache_range(unsigned long start, unsigned long stop)
66 *
67 * flush all bytes from start through stop-1 inclusive
68 */
70 _KPROBE(__flush_icache_range)
72 /*
73 * Flush the data cache to memory
74 *
75 * Different systems have different cache line sizes
76 * and in some cases i-cache and d-cache line sizes differ from
77 * each other.
78 */
79 ld r10,PPC64_CACHES@toc(r2)
80 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
81 addi r5,r7,-1
82 andc r6,r3,r5 /* round low to line bdy */
83 subf r8,r6,r4 /* compute length */
84 add r8,r8,r5 /* ensure we get enough */
85 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
86 srw. r8,r8,r9 /* compute line count */
87 beqlr /* nothing to do? */
88 mtctr r8
89 1: dcbst 0,r6
90 add r6,r6,r7
91 bdnz 1b
92 sync
94 /* Now invalidate the instruction cache */
96 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
97 addi r5,r7,-1
98 andc r6,r3,r5 /* round low to line bdy */
99 subf r8,r6,r4 /* compute length */
100 add r8,r8,r5
101 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
102 srw. r8,r8,r9 /* compute line count */
103 beqlr /* nothing to do? */
104 mtctr r8
105 2: icbi 0,r6
106 add r6,r6,r7
107 bdnz 2b
108 isync
109 blr
110 .previous .text
111 /*
112 * Like above, but only do the D-cache.
113 *
114 * flush_dcache_range(unsigned long start, unsigned long stop)
115 *
116 * flush all bytes from start to stop-1 inclusive
117 */
118 _GLOBAL(flush_dcache_range)
120 /*
121 * Flush the data cache to memory
122 *
123 * Different systems have different cache line sizes
124 */
125 ld r10,PPC64_CACHES@toc(r2)
126 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
127 addi r5,r7,-1
128 andc r6,r3,r5 /* round low to line bdy */
129 subf r8,r6,r4 /* compute length */
130 add r8,r8,r5 /* ensure we get enough */
131 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
132 srw. r8,r8,r9 /* compute line count */
133 beqlr /* nothing to do? */
134 mtctr r8
135 0: dcbst 0,r6
136 add r6,r6,r7
137 bdnz 0b
138 sync
139 blr
141 /*
142 * Like above, but works on non-mapped physical addresses.
143 * Use only for non-LPAR setups ! It also assumes real mode
144 * is cacheable. Used for flushing out the DART before using
145 * it as uncacheable memory
146 *
147 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
148 *
149 * flush all bytes from start to stop-1 inclusive
150 */
151 _GLOBAL(flush_dcache_phys_range)
152 ld r10,PPC64_CACHES@toc(r2)
153 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
154 addi r5,r7,-1
155 andc r6,r3,r5 /* round low to line bdy */
156 subf r8,r6,r4 /* compute length */
157 add r8,r8,r5 /* ensure we get enough */
158 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
159 srw. r8,r8,r9 /* compute line count */
160 beqlr /* nothing to do? */
161 mfmsr r5 /* Disable MMU Data Relocation */
162 ori r0,r5,MSR_DR
163 xori r0,r0,MSR_DR
164 sync
165 mtmsr r0
166 sync
167 isync
168 mtctr r8
169 0: dcbst 0,r6
170 add r6,r6,r7
171 bdnz 0b
172 sync
173 isync
174 mtmsr r5 /* Re-enable MMU Data Relocation */
175 sync
176 isync
177 blr
179 _GLOBAL(flush_inval_dcache_range)
180 ld r10,PPC64_CACHES@toc(r2)
181 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
182 addi r5,r7,-1
183 andc r6,r3,r5 /* round low to line bdy */
184 subf r8,r6,r4 /* compute length */
185 add r8,r8,r5 /* ensure we get enough */
186 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
187 srw. r8,r8,r9 /* compute line count */
188 beqlr /* nothing to do? */
189 sync
190 isync
191 mtctr r8
192 0: dcbf 0,r6
193 add r6,r6,r7
194 bdnz 0b
195 sync
196 isync
197 blr
200 /*
201 * Flush a particular page from the data cache to RAM.
202 * Note: this is necessary because the instruction cache does *not*
203 * snoop from the data cache.
204 *
205 * void __flush_dcache_icache(void *page)
206 */
207 _GLOBAL(__flush_dcache_icache)
208 /*
209 * Flush the data cache to memory
210 *
211 * Different systems have different cache line sizes
212 */
214 /* Flush the dcache */
215 ld r7,PPC64_CACHES@toc(r2)
216 clrrdi r3,r3,PAGE_SHIFT /* Page align */
217 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
218 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
219 mr r6,r3
220 mtctr r4
221 0: dcbst 0,r6
222 add r6,r6,r5
223 bdnz 0b
224 sync
226 /* Now invalidate the icache */
228 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
229 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
230 mtctr r4
231 1: icbi 0,r3
232 add r3,r3,r5
233 bdnz 1b
234 isync
235 blr
238 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
239 /*
240 * Do an IO access in real mode
241 */
242 _GLOBAL(real_readb)
243 mfmsr r7
244 ori r0,r7,MSR_DR
245 xori r0,r0,MSR_DR
246 sync
247 mtmsrd r0
248 sync
249 isync
250 mfspr r6,SPRN_HID4
251 rldicl r5,r6,32,0
252 ori r5,r5,0x100
253 rldicl r5,r5,32,0
254 sync
255 mtspr SPRN_HID4,r5
256 isync
257 slbia
258 isync
259 lbz r3,0(r3)
260 sync
261 mtspr SPRN_HID4,r6
262 isync
263 slbia
264 isync
265 mtmsrd r7
266 sync
267 isync
268 blr
270 /*
271 * Do an IO access in real mode
272 */
273 _GLOBAL(real_writeb)
274 mfmsr r7
275 ori r0,r7,MSR_DR
276 xori r0,r0,MSR_DR
277 sync
278 mtmsrd r0
279 sync
280 isync
281 mfspr r6,SPRN_HID4
282 rldicl r5,r6,32,0
283 ori r5,r5,0x100
284 rldicl r5,r5,32,0
285 sync
286 mtspr SPRN_HID4,r5
287 isync
288 slbia
289 isync
290 stb r3,0(r4)
291 sync
292 mtspr SPRN_HID4,r6
293 isync
294 slbia
295 isync
296 mtmsrd r7
297 sync
298 isync
299 blr
300 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
302 #ifdef CONFIG_PPC_PASEMI
304 _GLOBAL(real_205_readb)
305 mfmsr r7
306 ori r0,r7,MSR_DR
307 xori r0,r0,MSR_DR
308 sync
309 mtmsrd r0
310 sync
311 isync
312 LBZCIX(R3,R0,R3)
313 isync
314 mtmsrd r7
315 sync
316 isync
317 blr
319 _GLOBAL(real_205_writeb)
320 mfmsr r7
321 ori r0,r7,MSR_DR
322 xori r0,r0,MSR_DR
323 sync
324 mtmsrd r0
325 sync
326 isync
327 STBCIX(R3,R0,R4)
328 isync
329 mtmsrd r7
330 sync
331 isync
332 blr
334 #endif /* CONFIG_PPC_PASEMI */
337 #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
338 /*
339 * SCOM access functions for 970 (FX only for now)
340 *
341 * unsigned long scom970_read(unsigned int address);
342 * void scom970_write(unsigned int address, unsigned long value);
343 *
344 * The address passed in is the 24 bits register address. This code
345 * is 970 specific and will not check the status bits, so you should
346 * know what you are doing.
347 */
348 _GLOBAL(scom970_read)
349 /* interrupts off */
350 mfmsr r4
351 ori r0,r4,MSR_EE
352 xori r0,r0,MSR_EE
353 mtmsrd r0,1
355 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
356 * (including parity). On current CPUs they must be 0'd,
357 * and finally or in RW bit
358 */
359 rlwinm r3,r3,8,0,15
360 ori r3,r3,0x8000
362 /* do the actual scom read */
363 sync
364 mtspr SPRN_SCOMC,r3
365 isync
366 mfspr r3,SPRN_SCOMD
367 isync
368 mfspr r0,SPRN_SCOMC
369 isync
371 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
372 * that's the best we can do). Not implemented yet as we don't use
373 * the scom on any of the bogus CPUs yet, but may have to be done
374 * ultimately
375 */
377 /* restore interrupts */
378 mtmsrd r4,1
379 blr
382 _GLOBAL(scom970_write)
383 /* interrupts off */
384 mfmsr r5
385 ori r0,r5,MSR_EE
386 xori r0,r0,MSR_EE
387 mtmsrd r0,1
389 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
390 * (including parity). On current CPUs they must be 0'd.
391 */
393 rlwinm r3,r3,8,0,15
395 sync
396 mtspr SPRN_SCOMD,r4 /* write data */
397 isync
398 mtspr SPRN_SCOMC,r3 /* write command */
399 isync
400 mfspr 3,SPRN_SCOMC
401 isync
403 /* restore interrupts */
404 mtmsrd r5,1
405 blr
406 #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
409 /*
410 * disable_kernel_fp()
411 * Disable the FPU.
412 */
413 _GLOBAL(disable_kernel_fp)
414 mfmsr r3
415 rldicl r0,r3,(63-MSR_FP_LG),1
416 rldicl r3,r0,(MSR_FP_LG+1),0
417 mtmsrd r3 /* disable use of fpu now */
418 isync
419 blr
421 /* kexec_wait(phys_cpu)
422 *
423 * wait for the flag to change, indicating this kernel is going away but
424 * the slave code for the next one is at addresses 0 to 100.
425 *
426 * This is used by all slaves, even those that did not find a matching
427 * paca in the secondary startup code.
428 *
429 * Physical (hardware) cpu id should be in r3.
430 */
431 _GLOBAL(kexec_wait)
432 bl 1f
433 1: mflr r5
434 addi r5,r5,kexec_flag-1b
436 99: HMT_LOW
437 #ifdef CONFIG_KEXEC /* use no memory without kexec */
438 lwz r4,0(r5)
439 cmpwi 0,r4,0
440 bnea 0x60
441 #endif
442 b 99b
444 /* this can be in text because we won't change it until we are
445 * running in real anyways
446 */
447 kexec_flag:
448 .long 0
451 #ifdef CONFIG_KEXEC
453 /* kexec_smp_wait(void)
454 *
455 * call with interrupts off
456 * note: this is a terminal routine, it does not save lr
457 *
458 * get phys id from paca
459 * switch to real mode
460 * mark the paca as no longer used
461 * join other cpus in kexec_wait(phys_id)
462 */
463 _GLOBAL(kexec_smp_wait)
464 lhz r3,PACAHWCPUID(r13)
465 bl real_mode
467 li r4,KEXEC_STATE_REAL_MODE
468 stb r4,PACAKEXECSTATE(r13)
469 SYNC
471 b .kexec_wait
473 /*
474 * switch to real mode (turn mmu off)
475 * we use the early kernel trick that the hardware ignores bits
476 * 0 and 1 (big endian) of the effective address in real mode
477 *
478 * don't overwrite r3 here, it is live for kexec_wait above.
479 */
480 real_mode: /* assume normal blr return */
481 1: li r9,MSR_RI
482 li r10,MSR_DR|MSR_IR
483 mflr r11 /* return address to SRR0 */
484 mfmsr r12
485 andc r9,r12,r9
486 andc r10,r12,r10
488 mtmsrd r9,1
489 mtspr SPRN_SRR1,r10
490 mtspr SPRN_SRR0,r11
491 rfid
494 /*
495 * kexec_sequence(newstack, start, image, control, clear_all())
496 *
497 * does the grungy work with stack switching and real mode switches
498 * also does simple calls to other code
499 */
501 _GLOBAL(kexec_sequence)
502 mflr r0
503 std r0,16(r1)
505 /* switch stacks to newstack -- &kexec_stack.stack */
506 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
507 mr r1,r3
509 li r0,0
510 std r0,16(r1)
512 /* save regs for local vars on new stack.
513 * yes, we won't go back, but ...
514 */
515 std r31,-8(r1)
516 std r30,-16(r1)
517 std r29,-24(r1)
518 std r28,-32(r1)
519 std r27,-40(r1)
520 std r26,-48(r1)
521 std r25,-56(r1)
523 stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
525 /* save args into preserved regs */
526 mr r31,r3 /* newstack (both) */
527 mr r30,r4 /* start (real) */
528 mr r29,r5 /* image (virt) */
529 mr r28,r6 /* control, unused */
530 mr r27,r7 /* clear_all() fn desc */
531 mr r26,r8 /* spare */
532 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
534 /* disable interrupts, we are overwriting kernel data next */
535 mfmsr r3
536 rlwinm r3,r3,0,17,15
537 mtmsrd r3,1
539 /* copy dest pages, flush whole dest image */
540 mr r3,r29
541 bl .kexec_copy_flush /* (image) */
543 /* turn off mmu */
544 bl real_mode
546 /* copy 0x100 bytes starting at start to 0 */
547 li r3,0
548 mr r4,r30 /* start, aka phys mem offset */
549 li r5,0x100
550 li r6,0
551 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
552 1: /* assume normal blr return */
554 /* release other cpus to the new kernel secondary start at 0x60 */
555 mflr r5
556 li r6,1
557 stw r6,kexec_flag-1b(5)
559 /* clear out hardware hash page table and tlb */
560 ld r5,0(r27) /* deref function descriptor */
561 mtctr r5
562 bctrl /* ppc_md.hpte_clear_all(void); */
564 /*
565 * kexec image calling is:
566 * the first 0x100 bytes of the entry point are copied to 0
567 *
568 * all slaves branch to slave = 0x60 (absolute)
569 * slave(phys_cpu_id);
570 *
571 * master goes to start = entry point
572 * start(phys_cpu_id, start, 0);
573 *
574 *
575 * a wrapper is needed to call existing kernels, here is an approximate
576 * description of one method:
577 *
578 * v2: (2.6.10)
579 * start will be near the boot_block (maybe 0x100 bytes before it?)
580 * it will have a 0x60, which will b to boot_block, where it will wait
581 * and 0 will store phys into struct boot-block and load r3 from there,
582 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
583 *
584 * v1: (2.6.9)
585 * boot block will have all cpus scanning device tree to see if they
586 * are the boot cpu ?????
587 * other device tree differences (prop sizes, va vs pa, etc)...
588 */
589 mr r3,r25 # my phys cpu
590 mr r4,r30 # start, aka phys mem offset
591 mtlr 4
592 li r5,0
593 blr /* image->start(physid, image->start, 0); */
594 #endif /* CONFIG_KEXEC */