| blob | b4113bf863538adbf6d0bffdaa3aabe090270064 |
1 /*
2 * Low level TLB miss handlers for Book3E
3 *
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
13 #include <asm/processor.h>
14 #include <asm/reg.h>
15 #include <asm/page.h>
16 #include <asm/mmu.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
21 #include <asm/exception-64e.h>
22 #include <asm/ppc-opcode.h>
23 #include <asm/kvm_asm.h>
24 #include <asm/kvm_booke_hv_asm.h>
26 #ifdef CONFIG_PPC_64K_PAGES
27 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
28 #else
29 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
30 #endif
31 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
32 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
33 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
35 /**********************************************************************
36 * *
37 * TLB miss handling for Book3E with a bolted linear mapping *
38 * No virtual page table, no nested TLB misses *
39 * *
40 **********************************************************************/
42 .macro tlb_prolog_bolted intnum addr
43 mtspr SPRN_SPRG_GEN_SCRATCH,r13
44 mfspr r13,SPRN_SPRG_PACA
45 std r10,PACA_EXTLB+EX_TLB_R10(r13)
46 mfcr r10
47 std r11,PACA_EXTLB+EX_TLB_R11(r13)
48 #ifdef CONFIG_KVM_BOOKE_HV
49 BEGIN_FTR_SECTION
50 mfspr r11, SPRN_SRR1
51 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
52 #endif
53 DO_KVM \intnum, SPRN_SRR1
54 std r16,PACA_EXTLB+EX_TLB_R16(r13)
55 mfspr r16,\addr /* get faulting address */
56 std r14,PACA_EXTLB+EX_TLB_R14(r13)
57 ld r14,PACAPGD(r13)
58 std r15,PACA_EXTLB+EX_TLB_R15(r13)
59 std r10,PACA_EXTLB+EX_TLB_CR(r13)
60 TLB_MISS_PROLOG_STATS_BOLTED
61 .endm
63 .macro tlb_epilog_bolted
64 ld r14,PACA_EXTLB+EX_TLB_CR(r13)
65 ld r10,PACA_EXTLB+EX_TLB_R10(r13)
66 ld r11,PACA_EXTLB+EX_TLB_R11(r13)
67 mtcr r14
68 ld r14,PACA_EXTLB+EX_TLB_R14(r13)
69 ld r15,PACA_EXTLB+EX_TLB_R15(r13)
70 TLB_MISS_RESTORE_STATS_BOLTED
71 ld r16,PACA_EXTLB+EX_TLB_R16(r13)
72 mfspr r13,SPRN_SPRG_GEN_SCRATCH
73 .endm
75 /* Data TLB miss */
76 START_EXCEPTION(data_tlb_miss_bolted)
77 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
79 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
81 /* We do the user/kernel test for the PID here along with the RW test
82 */
83 /* We pre-test some combination of permissions to avoid double
84 * faults:
85 *
86 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
87 * ESR_ST is 0x00800000
88 * _PAGE_BAP_SW is 0x00000010
89 * So the shift is >> 19. This tests for supervisor writeability.
90 * If the page happens to be supervisor writeable and not user
91 * writeable, we will take a new fault later, but that should be
92 * a rare enough case.
93 *
94 * We also move ESR_ST in _PAGE_DIRTY position
95 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
96 *
97 * MAS1 is preset for all we need except for TID that needs to
98 * be cleared for kernel translations
99 */
101 mfspr r11,SPRN_ESR
103 srdi r15,r16,60 /* get region */
104 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
105 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
107 rlwinm r10,r11,32-19,27,27
108 rlwimi r10,r11,32-16,19,19
109 cmpwi r15,0 /* user vs kernel check */
110 ori r10,r10,_PAGE_PRESENT
111 oris r11,r10,_PAGE_ACCESSED@h
113 TLB_MISS_STATS_SAVE_INFO_BOLTED
114 bne tlb_miss_kernel_bolted
116 tlb_miss_common_bolted:
117 /*
118 * This is the guts of the TLB miss handler for bolted-linear.
119 * We are entered with:
120 *
121 * r16 = faulting address
122 * r15 = crap (free to use)
123 * r14 = page table base
124 * r13 = PACA
125 * r11 = PTE permission mask
126 * r10 = crap (free to use)
127 */
128 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
129 cmpldi cr0,r14,0
130 clrrdi r15,r15,3
131 beq tlb_miss_fault_bolted /* No PGDIR, bail */
133 BEGIN_MMU_FTR_SECTION
134 /* Set the TLB reservation and search for existing entry. Then load
135 * the entry.
136 */
137 PPC_TLBSRX_DOT(0,R16)
138 ldx r14,r14,r15 /* grab pgd entry */
139 beq normal_tlb_miss_done /* tlb exists already, bail */
140 MMU_FTR_SECTION_ELSE
141 ldx r14,r14,r15 /* grab pgd entry */
142 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
144 #ifndef CONFIG_PPC_64K_PAGES
145 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
146 clrrdi r15,r15,3
147 cmpdi cr0,r14,0
148 bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */
149 ldx r14,r14,r15 /* grab pud entry */
150 #endif /* CONFIG_PPC_64K_PAGES */
152 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
153 clrrdi r15,r15,3
154 cmpdi cr0,r14,0
155 bge tlb_miss_fault_bolted
156 ldx r14,r14,r15 /* Grab pmd entry */
158 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
159 clrrdi r15,r15,3
160 cmpdi cr0,r14,0
161 bge tlb_miss_fault_bolted
162 ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */
164 /* Check if required permissions are met */
165 andc. r15,r11,r14
166 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
167 bne- tlb_miss_fault_bolted
169 /* Now we build the MAS:
170 *
171 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
172 * MAS 1 : Almost fully setup
173 * - PID already updated by caller if necessary
174 * - TSIZE need change if !base page size, not
175 * yet implemented for now
176 * MAS 2 : Defaults not useful, need to be redone
177 * MAS 3+7 : Needs to be done
178 */
179 clrrdi r11,r16,12 /* Clear low crap in EA */
180 clrldi r15,r15,12 /* Clear crap at the top */
181 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
182 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
183 mtspr SPRN_MAS2,r11
184 andi. r11,r14,_PAGE_DIRTY
185 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
187 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
188 bne 1f
189 li r11,MAS3_SW|MAS3_UW
190 andc r15,r15,r11
191 1:
192 mtspr SPRN_MAS7_MAS3,r15
193 tlbwe
195 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
196 tlb_epilog_bolted
197 rfi
199 itlb_miss_kernel_bolted:
200 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
201 oris r11,r11,_PAGE_ACCESSED@h
202 tlb_miss_kernel_bolted:
203 mfspr r10,SPRN_MAS1
204 ld r14,PACA_KERNELPGD(r13)
205 cmpldi cr0,r15,8 /* Check for vmalloc region */
206 rlwinm r10,r10,0,16,1 /* Clear TID */
207 mtspr SPRN_MAS1,r10
208 beq+ tlb_miss_common_bolted
210 tlb_miss_fault_bolted:
211 /* We need to check if it was an instruction miss */
212 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
213 bne itlb_miss_fault_bolted
214 dtlb_miss_fault_bolted:
215 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
216 tlb_epilog_bolted
217 b exc_data_storage_book3e
218 itlb_miss_fault_bolted:
219 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
220 tlb_epilog_bolted
221 b exc_instruction_storage_book3e
223 /* Instruction TLB miss */
224 START_EXCEPTION(instruction_tlb_miss_bolted)
225 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
227 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
228 srdi r15,r16,60 /* get region */
229 TLB_MISS_STATS_SAVE_INFO_BOLTED
230 bne- itlb_miss_fault_bolted
232 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
234 /* We do the user/kernel test for the PID here along with the RW test
235 */
237 cmpldi cr0,r15,0 /* Check for user region */
238 oris r11,r11,_PAGE_ACCESSED@h
239 beq tlb_miss_common_bolted
240 b itlb_miss_kernel_bolted
242 /**********************************************************************
243 * *
244 * TLB miss handling for Book3E with TLB reservation and HES support *
245 * *
246 **********************************************************************/
249 /* Data TLB miss */
250 START_EXCEPTION(data_tlb_miss)
251 TLB_MISS_PROLOG
253 /* Now we handle the fault proper. We only save DEAR in normal
254 * fault case since that's the only interesting values here.
255 * We could probably also optimize by not saving SRR0/1 in the
256 * linear mapping case but I'll leave that for later
257 */
258 mfspr r14,SPRN_ESR
259 mfspr r16,SPRN_DEAR /* get faulting address */
260 srdi r15,r16,60 /* get region */
261 cmpldi cr0,r15,0xc /* linear mapping ? */
262 TLB_MISS_STATS_SAVE_INFO
263 beq tlb_load_linear /* yes -> go to linear map load */
265 /* The page tables are mapped virtually linear. At this point, though,
266 * we don't know whether we are trying to fault in a first level
267 * virtual address or a virtual page table address. We can get that
268 * from bit 0x1 of the region ID which we have set for a page table
269 */
270 andi. r10,r15,0x1
271 bne- virt_page_table_tlb_miss
273 std r14,EX_TLB_ESR(r12); /* save ESR */
274 std r16,EX_TLB_DEAR(r12); /* save DEAR */
276 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
277 li r11,_PAGE_PRESENT
278 oris r11,r11,_PAGE_ACCESSED@h
280 /* We do the user/kernel test for the PID here along with the RW test
281 */
282 cmpldi cr0,r15,0 /* Check for user region */
284 /* We pre-test some combination of permissions to avoid double
285 * faults:
286 *
287 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
288 * ESR_ST is 0x00800000
289 * _PAGE_BAP_SW is 0x00000010
290 * So the shift is >> 19. This tests for supervisor writeability.
291 * If the page happens to be supervisor writeable and not user
292 * writeable, we will take a new fault later, but that should be
293 * a rare enough case.
294 *
295 * We also move ESR_ST in _PAGE_DIRTY position
296 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
297 *
298 * MAS1 is preset for all we need except for TID that needs to
299 * be cleared for kernel translations
300 */
301 rlwimi r11,r14,32-19,27,27
302 rlwimi r11,r14,32-16,19,19
303 beq normal_tlb_miss
304 /* XXX replace the RMW cycles with immediate loads + writes */
305 1: mfspr r10,SPRN_MAS1
306 cmpldi cr0,r15,8 /* Check for vmalloc region */
307 rlwinm r10,r10,0,16,1 /* Clear TID */
308 mtspr SPRN_MAS1,r10
309 beq+ normal_tlb_miss
311 /* We got a crappy address, just fault with whatever DEAR and ESR
312 * are here
313 */
314 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
315 TLB_MISS_EPILOG_ERROR
316 b exc_data_storage_book3e
318 /* Instruction TLB miss */
319 START_EXCEPTION(instruction_tlb_miss)
320 TLB_MISS_PROLOG
322 /* If we take a recursive fault, the second level handler may need
323 * to know whether we are handling a data or instruction fault in
324 * order to get to the right store fault handler. We provide that
325 * info by writing a crazy value in ESR in our exception frame
326 */
327 li r14,-1 /* store to exception frame is done later */
329 /* Now we handle the fault proper. We only save DEAR in the non
330 * linear mapping case since we know the linear mapping case will
331 * not re-enter. We could indeed optimize and also not save SRR0/1
332 * in the linear mapping case but I'll leave that for later
333 *
334 * Faulting address is SRR0 which is already in r16
335 */
336 srdi r15,r16,60 /* get region */
337 cmpldi cr0,r15,0xc /* linear mapping ? */
338 TLB_MISS_STATS_SAVE_INFO
339 beq tlb_load_linear /* yes -> go to linear map load */
341 /* We do the user/kernel test for the PID here along with the RW test
342 */
343 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
344 oris r11,r11,_PAGE_ACCESSED@h
346 cmpldi cr0,r15,0 /* Check for user region */
347 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
348 beq normal_tlb_miss
350 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
351 oris r11,r11,_PAGE_ACCESSED@h
352 /* XXX replace the RMW cycles with immediate loads + writes */
353 mfspr r10,SPRN_MAS1
354 cmpldi cr0,r15,8 /* Check for vmalloc region */
355 rlwinm r10,r10,0,16,1 /* Clear TID */
356 mtspr SPRN_MAS1,r10
357 beq+ normal_tlb_miss
359 /* We got a crappy address, just fault */
360 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
361 TLB_MISS_EPILOG_ERROR
362 b exc_instruction_storage_book3e
364 /*
365 * This is the guts of the first-level TLB miss handler for direct
366 * misses. We are entered with:
367 *
368 * r16 = faulting address
369 * r15 = region ID
370 * r14 = crap (free to use)
371 * r13 = PACA
372 * r12 = TLB exception frame in PACA
373 * r11 = PTE permission mask
374 * r10 = crap (free to use)
375 */
376 normal_tlb_miss:
377 /* So we first construct the page table address. We do that by
378 * shifting the bottom of the address (not the region ID) by
379 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
380 * or'ing the fourth high bit.
381 *
382 * NOTE: For 64K pages, we do things slightly differently in
383 * order to handle the weird page table format used by linux
384 */
385 ori r10,r15,0x1
386 #ifdef CONFIG_PPC_64K_PAGES
387 /* For the top bits, 16 bytes per PTE */
388 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
389 /* Now create the bottom bits as 0 in position 0x8000 and
390 * the rest calculated for 8 bytes per PTE
391 */
392 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
393 /* Insert the bottom bits in */
394 rlwimi r14,r15,0,16,31
395 #else
396 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
397 #endif
398 sldi r15,r10,60
399 clrrdi r14,r14,3
400 or r10,r15,r14
402 BEGIN_MMU_FTR_SECTION
403 /* Set the TLB reservation and search for existing entry. Then load
404 * the entry.
405 */
406 PPC_TLBSRX_DOT(0,R16)
407 ld r14,0(r10)
408 beq normal_tlb_miss_done
409 MMU_FTR_SECTION_ELSE
410 ld r14,0(r10)
411 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
413 finish_normal_tlb_miss:
414 /* Check if required permissions are met */
415 andc. r15,r11,r14
416 bne- normal_tlb_miss_access_fault
418 /* Now we build the MAS:
419 *
420 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
421 * MAS 1 : Almost fully setup
422 * - PID already updated by caller if necessary
423 * - TSIZE need change if !base page size, not
424 * yet implemented for now
425 * MAS 2 : Defaults not useful, need to be redone
426 * MAS 3+7 : Needs to be done
427 *
428 * TODO: mix up code below for better scheduling
429 */
430 clrrdi r11,r16,12 /* Clear low crap in EA */
431 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
432 mtspr SPRN_MAS2,r11
434 /* Check page size, if not standard, update MAS1 */
435 rldicl r11,r14,64-8,64-8
436 #ifdef CONFIG_PPC_64K_PAGES
437 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
438 #else
439 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
440 #endif
441 beq- 1f
442 mfspr r11,SPRN_MAS1
443 rlwimi r11,r14,31,21,24
444 rlwinm r11,r11,0,21,19
445 mtspr SPRN_MAS1,r11
446 1:
447 /* Move RPN in position */
448 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
449 clrldi r15,r11,12 /* Clear crap at the top */
450 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
451 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
453 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
454 andi. r11,r14,_PAGE_DIRTY
455 bne 1f
456 li r11,MAS3_SW|MAS3_UW
457 andc r15,r15,r11
458 1:
459 BEGIN_MMU_FTR_SECTION
460 srdi r16,r15,32
461 mtspr SPRN_MAS3,r15
462 mtspr SPRN_MAS7,r16
463 MMU_FTR_SECTION_ELSE
464 mtspr SPRN_MAS7_MAS3,r15
465 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
467 tlbwe
469 normal_tlb_miss_done:
470 /* We don't bother with restoring DEAR or ESR since we know we are
471 * level 0 and just going back to userland. They are only needed
472 * if you are going to take an access fault
473 */
474 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
475 TLB_MISS_EPILOG_SUCCESS
476 rfi
478 normal_tlb_miss_access_fault:
479 /* We need to check if it was an instruction miss */
480 andi. r10,r11,_PAGE_EXEC
481 bne 1f
482 ld r14,EX_TLB_DEAR(r12)
483 ld r15,EX_TLB_ESR(r12)
484 mtspr SPRN_DEAR,r14
485 mtspr SPRN_ESR,r15
486 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
487 TLB_MISS_EPILOG_ERROR
488 b exc_data_storage_book3e
489 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
490 TLB_MISS_EPILOG_ERROR
491 b exc_instruction_storage_book3e
494 /*
495 * This is the guts of the second-level TLB miss handler for direct
496 * misses. We are entered with:
497 *
498 * r16 = virtual page table faulting address
499 * r15 = region (top 4 bits of address)
500 * r14 = crap (free to use)
501 * r13 = PACA
502 * r12 = TLB exception frame in PACA
503 * r11 = crap (free to use)
504 * r10 = crap (free to use)
505 *
506 * Note that this should only ever be called as a second level handler
507 * with the current scheme when using SW load.
508 * That means we can always get the original fault DEAR at
509 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
510 *
511 * It can be re-entered by the linear mapping miss handler. However, to
512 * avoid too much complication, it will restart the whole fault at level
513 * 0 so we don't care too much about clobbers
514 *
515 * XXX That code was written back when we couldn't clobber r14. We can now,
516 * so we could probably optimize things a bit
517 */
518 virt_page_table_tlb_miss:
519 /* Are we hitting a kernel page table ? */
520 andi. r10,r15,0x8
522 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
523 * and we happen to have the swapper_pg_dir at offset 8 from the user
524 * pgdir in the PACA :-).
525 */
526 add r11,r10,r13
528 /* If kernel, we need to clear MAS1 TID */
529 beq 1f
530 /* XXX replace the RMW cycles with immediate loads + writes */
531 mfspr r10,SPRN_MAS1
532 rlwinm r10,r10,0,16,1 /* Clear TID */
533 mtspr SPRN_MAS1,r10
534 1:
535 BEGIN_MMU_FTR_SECTION
536 /* Search if we already have a TLB entry for that virtual address, and
537 * if we do, bail out.
538 */
539 PPC_TLBSRX_DOT(0,R16)
540 beq virt_page_table_tlb_miss_done
541 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
543 /* Now, we need to walk the page tables. First check if we are in
544 * range.
545 */
546 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
547 bne- virt_page_table_tlb_miss_fault
549 /* Get the PGD pointer */
550 ld r15,PACAPGD(r11)
551 cmpldi cr0,r15,0
552 beq- virt_page_table_tlb_miss_fault
554 /* Get to PGD entry */
555 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
556 clrrdi r10,r11,3
557 ldx r15,r10,r15
558 cmpdi cr0,r15,0
559 bge virt_page_table_tlb_miss_fault
561 #ifndef CONFIG_PPC_64K_PAGES
562 /* Get to PUD entry */
563 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
564 clrrdi r10,r11,3
565 ldx r15,r10,r15
566 cmpdi cr0,r15,0
567 bge virt_page_table_tlb_miss_fault
568 #endif /* CONFIG_PPC_64K_PAGES */
570 /* Get to PMD entry */
571 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
572 clrrdi r10,r11,3
573 ldx r15,r10,r15
574 cmpdi cr0,r15,0
575 bge virt_page_table_tlb_miss_fault
577 /* Ok, we're all right, we can now create a kernel translation for
578 * a 4K or 64K page from r16 -> r15.
579 */
580 /* Now we build the MAS:
581 *
582 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
583 * MAS 1 : Almost fully setup
584 * - PID already updated by caller if necessary
585 * - TSIZE for now is base page size always
586 * MAS 2 : Use defaults
587 * MAS 3+7 : Needs to be done
588 *
589 * So we only do MAS 2 and 3 for now...
590 */
591 clrldi r11,r15,4 /* remove region ID from RPN */
592 ori r10,r11,1 /* Or-in SR */
594 BEGIN_MMU_FTR_SECTION
595 srdi r16,r10,32
596 mtspr SPRN_MAS3,r10
597 mtspr SPRN_MAS7,r16
598 MMU_FTR_SECTION_ELSE
599 mtspr SPRN_MAS7_MAS3,r10
600 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
602 tlbwe
604 BEGIN_MMU_FTR_SECTION
605 virt_page_table_tlb_miss_done:
607 /* We have overriden MAS2:EPN but currently our primary TLB miss
608 * handler will always restore it so that should not be an issue,
609 * if we ever optimize the primary handler to not write MAS2 on
610 * some cases, we'll have to restore MAS2:EPN here based on the
611 * original fault's DEAR. If we do that we have to modify the
612 * ITLB miss handler to also store SRR0 in the exception frame
613 * as DEAR.
614 *
615 * However, one nasty thing we did is we cleared the reservation
616 * (well, potentially we did). We do a trick here thus if we
617 * are not a level 0 exception (we interrupted the TLB miss) we
618 * offset the return address by -4 in order to replay the tlbsrx
619 * instruction there
620 */
621 subf r10,r13,r12
622 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
623 bne- 1f
624 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
625 addi r10,r11,-4
626 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
627 1:
628 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
629 /* Return to caller, normal case */
630 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
631 TLB_MISS_EPILOG_SUCCESS
632 rfi
634 virt_page_table_tlb_miss_fault:
635 /* If we fault here, things are a little bit tricky. We need to call
636 * either data or instruction store fault, and we need to retrieve
637 * the original fault address and ESR (for data).
638 *
639 * The thing is, we know that in normal circumstances, this is
640 * always called as a second level tlb miss for SW load or as a first
641 * level TLB miss for HW load, so we should be able to peek at the
642 * relevant information in the first exception frame in the PACA.
643 *
644 * However, we do need to double check that, because we may just hit
645 * a stray kernel pointer or a userland attack trying to hit those
646 * areas. If that is the case, we do a data fault. (We can't get here
647 * from an instruction tlb miss anyway).
648 *
649 * Note also that when going to a fault, we must unwind the previous
650 * level as well. Since we are doing that, we don't need to clear or
651 * restore the TLB reservation neither.
652 */
653 subf r10,r13,r12
654 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
655 bne- virt_page_table_tlb_miss_whacko_fault
657 /* We dig the original DEAR and ESR from slot 0 */
658 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
659 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
661 /* We check for the "special" ESR value for instruction faults */
662 cmpdi cr0,r16,-1
663 beq 1f
664 mtspr SPRN_DEAR,r15
665 mtspr SPRN_ESR,r16
666 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
667 TLB_MISS_EPILOG_ERROR
668 b exc_data_storage_book3e
669 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
670 TLB_MISS_EPILOG_ERROR
671 b exc_instruction_storage_book3e
673 virt_page_table_tlb_miss_whacko_fault:
674 /* The linear fault will restart everything so ESR and DEAR will
675 * not have been clobbered, let's just fault with what we have
676 */
677 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
678 TLB_MISS_EPILOG_ERROR
679 b exc_data_storage_book3e
682 /**************************************************************
683 * *
684 * TLB miss handling for Book3E with hw page table support *
685 * *
686 **************************************************************/
689 /* Data TLB miss */
690 START_EXCEPTION(data_tlb_miss_htw)
691 TLB_MISS_PROLOG
693 /* Now we handle the fault proper. We only save DEAR in normal
694 * fault case since that's the only interesting values here.
695 * We could probably also optimize by not saving SRR0/1 in the
696 * linear mapping case but I'll leave that for later
697 */
698 mfspr r14,SPRN_ESR
699 mfspr r16,SPRN_DEAR /* get faulting address */
700 srdi r11,r16,60 /* get region */
701 cmpldi cr0,r11,0xc /* linear mapping ? */
702 TLB_MISS_STATS_SAVE_INFO
703 beq tlb_load_linear /* yes -> go to linear map load */
705 /* We do the user/kernel test for the PID here along with the RW test
706 */
707 cmpldi cr0,r11,0 /* Check for user region */
708 ld r15,PACAPGD(r13) /* Load user pgdir */
709 beq htw_tlb_miss
711 /* XXX replace the RMW cycles with immediate loads + writes */
712 1: mfspr r10,SPRN_MAS1
713 cmpldi cr0,r11,8 /* Check for vmalloc region */
714 rlwinm r10,r10,0,16,1 /* Clear TID */
715 mtspr SPRN_MAS1,r10
716 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
717 beq+ htw_tlb_miss
719 /* We got a crappy address, just fault with whatever DEAR and ESR
720 * are here
721 */
722 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
723 TLB_MISS_EPILOG_ERROR
724 b exc_data_storage_book3e
726 /* Instruction TLB miss */
727 START_EXCEPTION(instruction_tlb_miss_htw)
728 TLB_MISS_PROLOG
730 /* If we take a recursive fault, the second level handler may need
731 * to know whether we are handling a data or instruction fault in
732 * order to get to the right store fault handler. We provide that
733 * info by keeping a crazy value for ESR in r14
734 */
735 li r14,-1 /* store to exception frame is done later */
737 /* Now we handle the fault proper. We only save DEAR in the non
738 * linear mapping case since we know the linear mapping case will
739 * not re-enter. We could indeed optimize and also not save SRR0/1
740 * in the linear mapping case but I'll leave that for later
741 *
742 * Faulting address is SRR0 which is already in r16
743 */
744 srdi r11,r16,60 /* get region */
745 cmpldi cr0,r11,0xc /* linear mapping ? */
746 TLB_MISS_STATS_SAVE_INFO
747 beq tlb_load_linear /* yes -> go to linear map load */
749 /* We do the user/kernel test for the PID here along with the RW test
750 */
751 cmpldi cr0,r11,0 /* Check for user region */
752 ld r15,PACAPGD(r13) /* Load user pgdir */
753 beq htw_tlb_miss
755 /* XXX replace the RMW cycles with immediate loads + writes */
756 1: mfspr r10,SPRN_MAS1
757 cmpldi cr0,r11,8 /* Check for vmalloc region */
758 rlwinm r10,r10,0,16,1 /* Clear TID */
759 mtspr SPRN_MAS1,r10
760 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
761 beq+ htw_tlb_miss
763 /* We got a crappy address, just fault */
764 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
765 TLB_MISS_EPILOG_ERROR
766 b exc_instruction_storage_book3e
769 /*
770 * This is the guts of the second-level TLB miss handler for direct
771 * misses. We are entered with:
772 *
773 * r16 = virtual page table faulting address
774 * r15 = PGD pointer
775 * r14 = ESR
776 * r13 = PACA
777 * r12 = TLB exception frame in PACA
778 * r11 = crap (free to use)
779 * r10 = crap (free to use)
780 *
781 * It can be re-entered by the linear mapping miss handler. However, to
782 * avoid too much complication, it will save/restore things for us
783 */
784 htw_tlb_miss:
785 /* Search if we already have a TLB entry for that virtual address, and
786 * if we do, bail out.
787 *
788 * MAS1:IND should be already set based on MAS4
789 */
790 PPC_TLBSRX_DOT(0,R16)
791 beq htw_tlb_miss_done
793 /* Now, we need to walk the page tables. First check if we are in
794 * range.
795 */
796 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
797 bne- htw_tlb_miss_fault
799 /* Get the PGD pointer */
800 cmpldi cr0,r15,0
801 beq- htw_tlb_miss_fault
803 /* Get to PGD entry */
804 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
805 clrrdi r10,r11,3
806 ldx r15,r10,r15
807 cmpdi cr0,r15,0
808 bge htw_tlb_miss_fault
810 #ifndef CONFIG_PPC_64K_PAGES
811 /* Get to PUD entry */
812 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
813 clrrdi r10,r11,3
814 ldx r15,r10,r15
815 cmpdi cr0,r15,0
816 bge htw_tlb_miss_fault
817 #endif /* CONFIG_PPC_64K_PAGES */
819 /* Get to PMD entry */
820 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
821 clrrdi r10,r11,3
822 ldx r15,r10,r15
823 cmpdi cr0,r15,0
824 bge htw_tlb_miss_fault
826 /* Ok, we're all right, we can now create an indirect entry for
827 * a 1M or 256M page.
828 *
829 * The last trick is now that because we use "half" pages for
830 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
831 * for an added LSB bit to the RPN. For 64K pages, there is no
832 * problem as we already use 32K arrays (half PTE pages), but for
833 * 4K page we need to extract a bit from the virtual address and
834 * insert it into the "PA52" bit of the RPN.
835 */
836 #ifndef CONFIG_PPC_64K_PAGES
837 rlwimi r15,r16,32-9,20,20
838 #endif
839 /* Now we build the MAS:
840 *
841 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
842 * MAS 1 : Almost fully setup
843 * - PID already updated by caller if necessary
844 * - TSIZE for now is base ind page size always
845 * MAS 2 : Use defaults
846 * MAS 3+7 : Needs to be done
847 */
848 #ifdef CONFIG_PPC_64K_PAGES
849 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
850 #else
851 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
852 #endif
854 BEGIN_MMU_FTR_SECTION
855 srdi r16,r10,32
856 mtspr SPRN_MAS3,r10
857 mtspr SPRN_MAS7,r16
858 MMU_FTR_SECTION_ELSE
859 mtspr SPRN_MAS7_MAS3,r10
860 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
862 tlbwe
864 htw_tlb_miss_done:
865 /* We don't bother with restoring DEAR or ESR since we know we are
866 * level 0 and just going back to userland. They are only needed
867 * if you are going to take an access fault
868 */
869 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
870 TLB_MISS_EPILOG_SUCCESS
871 rfi
873 htw_tlb_miss_fault:
874 /* We need to check if it was an instruction miss. We know this
875 * though because r14 would contain -1
876 */
877 cmpdi cr0,r14,-1
878 beq 1f
879 mtspr SPRN_DEAR,r16
880 mtspr SPRN_ESR,r14
881 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
882 TLB_MISS_EPILOG_ERROR
883 b exc_data_storage_book3e
884 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
885 TLB_MISS_EPILOG_ERROR
886 b exc_instruction_storage_book3e
888 /*
889 * This is the guts of "any" level TLB miss handler for kernel linear
890 * mapping misses. We are entered with:
891 *
892 *
893 * r16 = faulting address
894 * r15 = crap (free to use)
895 * r14 = ESR (data) or -1 (instruction)
896 * r13 = PACA
897 * r12 = TLB exception frame in PACA
898 * r11 = crap (free to use)
899 * r10 = crap (free to use)
900 *
901 * In addition we know that we will not re-enter, so in theory, we could
902 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
903 *
904 * We also need to be careful about MAS registers here & TLB reservation,
905 * as we know we'll have clobbered them if we interrupt the main TLB miss
906 * handlers in which case we probably want to do a full restart at level
907 * 0 rather than saving / restoring the MAS.
908 *
909 * Note: If we care about performance of that core, we can easily shuffle
910 * a few things around
911 */
912 tlb_load_linear:
913 /* For now, we assume the linear mapping is contiguous and stops at
914 * linear_map_top. We also assume the size is a multiple of 1G, thus
915 * we only use 1G pages for now. That might have to be changed in a
916 * final implementation, especially when dealing with hypervisors
917 */
918 ld r11,PACATOC(r13)
919 ld r11,linear_map_top@got(r11)
920 ld r10,0(r11)
921 cmpld cr0,r10,r16
922 bge tlb_load_linear_fault
924 /* MAS1 need whole new setup. */
925 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
926 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
927 mtspr SPRN_MAS1,r15
929 /* Already somebody there ? */
930 PPC_TLBSRX_DOT(0,R16)
931 beq tlb_load_linear_done
933 /* Now we build the remaining MAS. MAS0 and 2 should be fine
934 * with their defaults, which leaves us with MAS 3 and 7. The
935 * mapping is linear, so we just take the address, clear the
936 * region bits, and or in the permission bits which are currently
937 * hard wired
938 */
939 clrrdi r10,r16,30 /* 1G page index */
940 clrldi r10,r10,4 /* clear region bits */
941 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
943 BEGIN_MMU_FTR_SECTION
944 srdi r16,r10,32
945 mtspr SPRN_MAS3,r10
946 mtspr SPRN_MAS7,r16
947 MMU_FTR_SECTION_ELSE
948 mtspr SPRN_MAS7_MAS3,r10
949 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
951 tlbwe
953 tlb_load_linear_done:
954 /* We use the "error" epilog for success as we do want to
955 * restore to the initial faulting context, whatever it was.
956 * We do that because we can't resume a fault within a TLB
957 * miss handler, due to MAS and TLB reservation being clobbered.
958 */
959 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
960 TLB_MISS_EPILOG_ERROR
961 rfi
963 tlb_load_linear_fault:
964 /* We keep the DEAR and ESR around, this shouldn't have happened */
965 cmpdi cr0,r14,-1
966 beq 1f
967 TLB_MISS_EPILOG_ERROR_SPECIAL
968 b exc_data_storage_book3e
969 1: TLB_MISS_EPILOG_ERROR_SPECIAL
970 b exc_instruction_storage_book3e
973 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
974 .tlb_stat_inc:
975 1: ldarx r8,0,r9
976 addi r8,r8,1
977 stdcx. r8,0,r9
978 bne- 1b
979 blr
980 #endif