arch/powerpc/platforms/52xx/mpc52xx_gpt.c

   1 /*
   2  * MPC5200 General Purpose Timer device driver
   3  *
   4  * Copyright (c) 2009 Secret Lab Technologies Ltd.
   5  * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  * This file is a driver for the the General Purpose Timer (gpt) devices
  13  * found on the MPC5200 SoC.  Each timer has an IO pin which can be used
  14  * for GPIO or can be used to raise interrupts.  The timer function can
  15  * be used independently from the IO pin, or it can be used to control
  16  * output signals or measure input signals.
  17  *
  18  * This driver supports the GPIO and IRQ controller functions of the GPT
  19  * device.  Timer functions are not yet supported.
  20  *
  21  * The timer gpt0 can be used as watchdog (wdt).  If the wdt mode is used,
  22  * this prevents the use of any gpt0 gpt function (i.e. they will fail with
  23  * -EBUSY).  Thus, the safety wdt function always has precedence over the gpt
  24  * function.  If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
  25  * this means that gpt0 is locked in wdt mode until the next reboot - this
  26  * may be a requirement in safety applications.
  27  *
  28  * To use the GPIO function, the following two properties must be added
  29  * to the device tree node for the gpt device (typically in the .dts file
  30  * for the board):
  31  *      gpio-controller;
  32  *      #gpio-cells = < 2 >;
  33  * This driver will register the GPIO pin if it finds the gpio-controller
  34  * property in the device tree.
  35  *
  36  * To use the IRQ controller function, the following two properties must
  37  * be added to the device tree node for the gpt device:
  38  *      interrupt-controller;
  39  *      #interrupt-cells = < 1 >;
  40  * The IRQ controller binding only uses one cell to specify the interrupt,
  41  * and the IRQ flags are encoded in the cell.  A cell is not used to encode
  42  * the IRQ number because the GPT only has a single IRQ source.  For flags,
  43  * a value of '1' means rising edge sensitive and '2' means falling edge.
  44  *
  45  * The GPIO and the IRQ controller functions can be used at the same time,
  46  * but in this use case the IO line will only work as an input.  Trying to
  47  * use it as a GPIO output will not work.
  48  *
  49  * When using the GPIO line as an output, it can either be driven as normal
  50  * IO, or it can be an Open Collector (OC) output.  At the moment it is the
  51  * responsibility of either the bootloader or the platform setup code to set
  52  * the output mode.  This driver does not change the output mode setting.
  53  */
  54
  55 #include <linux/device.h>
  56 #include <linux/irq.h>
  57 #include <linux/interrupt.h>
  58 #include <linux/io.h>
  59 #include <linux/list.h>
  60 #include <linux/mutex.h>
  61 #include <linux/of.h>
  62 #include <linux/of_platform.h>
  63 #include <linux/of_gpio.h>
  64 #include <linux/kernel.h>
  65 #include <linux/slab.h>
  66 #include <linux/fs.h>
  67 #include <linux/watchdog.h>
  68 #include <linux/miscdevice.h>
  69 #include <linux/uaccess.h>
  70 #include <linux/module.h>
  71 #include <asm/div64.h>
  72 #include <asm/mpc52xx.h>
  73
  74 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
  75 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
  76 MODULE_LICENSE("GPL");
  77
  78 /**
  79  * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
  80  * @dev: pointer to device structure
  81  * @regs: virtual address of GPT registers
  82  * @lock: spinlock to coordinate between different functions.
  83  * @gc: gpio_chip instance structure; used when GPIO is enabled
  84  * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
  85  * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
  86  *   if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
  87  *   if the timer is actively used as wdt which blocks gpt functions
  88  */
  89 struct mpc52xx_gpt_priv {
  90         struct list_head list;          /* List of all GPT devices */
  91         struct device *dev;
  92         struct mpc52xx_gpt __iomem *regs;
  93         spinlock_t lock;
  94         struct irq_domain *irqhost;
  95         u32 ipb_freq;
  96         u8 wdt_mode;
  97
  98 #if defined(CONFIG_GPIOLIB)
  99         struct gpio_chip gc;
 100 #endif
 101 };
 102
 103 LIST_HEAD(mpc52xx_gpt_list);
 104 DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
 105
 106 #define MPC52xx_GPT_MODE_MS_MASK        (0x07)
 107 #define MPC52xx_GPT_MODE_MS_IC          (0x01)
 108 #define MPC52xx_GPT_MODE_MS_OC          (0x02)
 109 #define MPC52xx_GPT_MODE_MS_PWM         (0x03)
 110 #define MPC52xx_GPT_MODE_MS_GPIO        (0x04)
 111
 112 #define MPC52xx_GPT_MODE_GPIO_MASK      (0x30)
 113 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW   (0x20)
 114 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH  (0x30)
 115
 116 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
 117 #define MPC52xx_GPT_MODE_CONTINUOUS     (0x0400)
 118 #define MPC52xx_GPT_MODE_OPEN_DRAIN     (0x0200)
 119 #define MPC52xx_GPT_MODE_IRQ_EN         (0x0100)
 120 #define MPC52xx_GPT_MODE_WDT_EN         (0x8000)
 121
 122 #define MPC52xx_GPT_MODE_ICT_MASK       (0x030000)
 123 #define MPC52xx_GPT_MODE_ICT_RISING     (0x010000)
 124 #define MPC52xx_GPT_MODE_ICT_FALLING    (0x020000)
 125 #define MPC52xx_GPT_MODE_ICT_TOGGLE     (0x030000)
 126
 127 #define MPC52xx_GPT_MODE_WDT_PING       (0xa5)
 128
 129 #define MPC52xx_GPT_STATUS_IRQMASK      (0x000f)
 130
 131 #define MPC52xx_GPT_CAN_WDT             (1 << 0)
 132 #define MPC52xx_GPT_IS_WDT              (1 << 1)
 133
 134
 135 /* ---------------------------------------------------------------------
 136  * Cascaded interrupt controller hooks
 137  */
 138
 139 static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
 140 {
 141         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
 142         unsigned long flags;
 143
 144         spin_lock_irqsave(&gpt->lock, flags);
 145         setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
 146         spin_unlock_irqrestore(&gpt->lock, flags);
 147 }
 148
 149 static void mpc52xx_gpt_irq_mask(struct irq_data *d)
 150 {
 151         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
 152         unsigned long flags;
 153
 154         spin_lock_irqsave(&gpt->lock, flags);
 155         clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
 156         spin_unlock_irqrestore(&gpt->lock, flags);
 157 }
 158
 159 static void mpc52xx_gpt_irq_ack(struct irq_data *d)
 160 {
 161         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
 162
 163         out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
 164 }
 165
 166 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
 167 {
 168         struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
 169         unsigned long flags;
 170         u32 reg;
 171
 172         dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
 173
 174         spin_lock_irqsave(&gpt->lock, flags);
 175         reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
 176         if (flow_type & IRQF_TRIGGER_RISING)
 177                 reg |= MPC52xx_GPT_MODE_ICT_RISING;
 178         if (flow_type & IRQF_TRIGGER_FALLING)
 179                 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
 180         out_be32(&gpt->regs->mode, reg);
 181         spin_unlock_irqrestore(&gpt->lock, flags);
 182
 183         return 0;
 184 }
 185
 186 static struct irq_chip mpc52xx_gpt_irq_chip = {
 187         .name = "MPC52xx GPT",
 188         .irq_unmask = mpc52xx_gpt_irq_unmask,
 189         .irq_mask = mpc52xx_gpt_irq_mask,
 190         .irq_ack = mpc52xx_gpt_irq_ack,
 191         .irq_set_type = mpc52xx_gpt_irq_set_type,
 192 };
 193
 194 void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
 195 {
 196         struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq);
 197         int sub_virq;
 198         u32 status;
 199
 200         status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
 201         if (status) {
 202                 sub_virq = irq_linear_revmap(gpt->irqhost, 0);
 203                 generic_handle_irq(sub_virq);
 204         }
 205 }
 206
 207 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
 208                                irq_hw_number_t hw)
 209 {
 210         struct mpc52xx_gpt_priv *gpt = h->host_data;
 211
 212         dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
 213         irq_set_chip_data(virq, gpt);
 214         irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
 215
 216         return 0;
 217 }
 218
 219 static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
 220                                  const u32 *intspec, unsigned int intsize,
 221                                  irq_hw_number_t *out_hwirq,
 222                                  unsigned int *out_flags)
 223 {
 224         struct mpc52xx_gpt_priv *gpt = h->host_data;
 225
 226         dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
 227
 228         if ((intsize < 1) || (intspec[0] > 3)) {
 229                 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
 230                 return -EINVAL;
 231         }
 232
 233         *out_hwirq = 0; /* The GPT only has 1 IRQ line */
 234         *out_flags = intspec[0];
 235
 236         return 0;
 237 }
 238
 239 static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
 240         .map = mpc52xx_gpt_irq_map,
 241         .xlate = mpc52xx_gpt_irq_xlate,
 242 };
 243
 244 static void
 245 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
 246 {
 247         int cascade_virq;
 248         unsigned long flags;
 249         u32 mode;
 250
 251         cascade_virq = irq_of_parse_and_map(node, 0);
 252         if (!cascade_virq)
 253                 return;
 254
 255         gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
 256         if (!gpt->irqhost) {
 257                 dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
 258                 return;
 259         }
 260
 261         irq_set_handler_data(cascade_virq, gpt);
 262         irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
 263
 264         /* If the GPT is currently disabled, then change it to be in Input
 265          * Capture mode.  If the mode is non-zero, then the pin could be
 266          * already in use for something. */
 267         spin_lock_irqsave(&gpt->lock, flags);
 268         mode = in_be32(&gpt->regs->mode);
 269         if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
 270                 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
 271         spin_unlock_irqrestore(&gpt->lock, flags);
 272
 273         dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
 274 }
 275
 276
 277 /* ---------------------------------------------------------------------
 278  * GPIOLIB hooks
 279  */
 280 #if defined(CONFIG_GPIOLIB)
 281 static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
 282 {
 283         return container_of(gc, struct mpc52xx_gpt_priv, gc);
 284 }
 285
 286 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 287 {
 288         struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
 289
 290         return (in_be32(&gpt->regs->status) >> 8) & 1;
 291 }
 292
 293 static void
 294 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
 295 {
 296         struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
 297         unsigned long flags;
 298         u32 r;
 299
 300         dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
 301         r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
 302
 303         spin_lock_irqsave(&gpt->lock, flags);
 304         clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
 305         spin_unlock_irqrestore(&gpt->lock, flags);
 306 }
 307
 308 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 309 {
 310         struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
 311         unsigned long flags;
 312
 313         dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
 314
 315         spin_lock_irqsave(&gpt->lock, flags);
 316         clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
 317         spin_unlock_irqrestore(&gpt->lock, flags);
 318
 319         return 0;
 320 }
 321
 322 static int
 323 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 324 {
 325         mpc52xx_gpt_gpio_set(gc, gpio, val);
 326         return 0;
 327 }
 328
 329 static void
 330 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
 331 {
 332         int rc;
 333
 334         /* Only setup GPIO if the device tree claims the GPT is
 335          * a GPIO controller */
 336         if (!of_find_property(node, "gpio-controller", NULL))
 337                 return;
 338
 339         gpt->gc.label = kstrdup(node->full_name, GFP_KERNEL);
 340         if (!gpt->gc.label) {
 341                 dev_err(gpt->dev, "out of memory\n");
 342                 return;
 343         }
 344
 345         gpt->gc.ngpio = 1;
 346         gpt->gc.direction_input  = mpc52xx_gpt_gpio_dir_in;
 347         gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
 348         gpt->gc.get = mpc52xx_gpt_gpio_get;
 349         gpt->gc.set = mpc52xx_gpt_gpio_set;
 350         gpt->gc.base = -1;
 351         gpt->gc.of_node = node;
 352
 353         /* Setup external pin in GPIO mode */
 354         clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
 355                         MPC52xx_GPT_MODE_MS_GPIO);
 356
 357         rc = gpiochip_add(&gpt->gc);
 358         if (rc)
 359                 dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
 360
 361         dev_dbg(gpt->dev, "%s() complete.\n", __func__);
 362 }
 363 #else /* defined(CONFIG_GPIOLIB) */
 364 static void
 365 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
 366 #endif /* defined(CONFIG_GPIOLIB) */
 367
 368 /***********************************************************************
 369  * Timer API
 370  */
 371
 372 /**
 373  * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
 374  * @irq: irq of timer.
 375  */
 376 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
 377 {
 378         struct mpc52xx_gpt_priv *gpt;
 379         struct list_head *pos;
 380
 381         /* Iterate over the list of timers looking for a matching device */
 382         mutex_lock(&mpc52xx_gpt_list_mutex);
 383         list_for_each(pos, &mpc52xx_gpt_list) {
 384                 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
 385                 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
 386                         mutex_unlock(&mpc52xx_gpt_list_mutex);
 387                         return gpt;
 388                 }
 389         }
 390         mutex_unlock(&mpc52xx_gpt_list_mutex);
 391
 392         return NULL;
 393 }
 394 EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
 395
 396 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
 397                                 int continuous, int as_wdt)
 398 {
 399         u32 clear, set;
 400         u64 clocks;
 401         u32 prescale;
 402         unsigned long flags;
 403
 404         clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
 405         set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
 406         if (as_wdt) {
 407                 clear |= MPC52xx_GPT_MODE_IRQ_EN;
 408                 set |= MPC52xx_GPT_MODE_WDT_EN;
 409         } else if (continuous)
 410                 set |= MPC52xx_GPT_MODE_CONTINUOUS;
 411
 412         /* Determine the number of clocks in the requested period.  64 bit
 413          * arithmatic is done here to preserve the precision until the value
 414          * is scaled back down into the u32 range.  Period is in 'ns', bus
 415          * frequency is in Hz. */
 416         clocks = period * (u64)gpt->ipb_freq;
 417         do_div(clocks, 1000000000); /* Scale it down to ns range */
 418
 419         /* This device cannot handle a clock count greater than 32 bits */
 420         if (clocks > 0xffffffff)
 421                 return -EINVAL;
 422
 423         /* Calculate the prescaler and count values from the clocks value.
 424          * 'clocks' is the number of clock ticks in the period.  The timer
 425          * has 16 bit precision and a 16 bit prescaler.  Prescaler is
 426          * calculated by integer dividing the clocks by 0x10000 (shifting
 427          * down 16 bits) to obtain the smallest possible divisor for clocks
 428          * to get a 16 bit count value.
 429          *
 430          * Note: the prescale register is '1' based, not '0' based.  ie. a
 431          * value of '1' means divide the clock by one.  0xffff divides the
 432          * clock by 0xffff.  '0x0000' does not divide by zero, but wraps
 433          * around and divides by 0x10000.  That is why prescale must be
 434          * a u32 variable, not a u16, for this calculation. */
 435         prescale = (clocks >> 16) + 1;
 436         do_div(clocks, prescale);
 437         if (clocks > 0xffff) {
 438                 pr_err("calculation error; prescale:%x clocks:%llx\n",
 439                        prescale, clocks);
 440                 return -EINVAL;
 441         }
 442
 443         /* Set and enable the timer, reject an attempt to use a wdt as gpt */
 444         spin_lock_irqsave(&gpt->lock, flags);
 445         if (as_wdt)
 446                 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
 447         else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
 448                 spin_unlock_irqrestore(&gpt->lock, flags);
 449                 return -EBUSY;
 450         }
 451         out_be32(&gpt->regs->count, prescale << 16 | clocks);
 452         clrsetbits_be32(&gpt->regs->mode, clear, set);
 453         spin_unlock_irqrestore(&gpt->lock, flags);
 454
 455         return 0;
 456 }
 457
 458 /**
 459  * mpc52xx_gpt_start_timer - Set and enable the GPT timer
 460  * @gpt: Pointer to gpt private data structure
 461  * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
 462  * @continuous: set to 1 to make timer continuous free running
 463  *
 464  * An interrupt will be generated every time the timer fires
 465  */
 466 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
 467                             int continuous)
 468 {
 469         return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
 470 }
 471 EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
 472
 473 /**
 474  * mpc52xx_gpt_stop_timer - Stop a gpt
 475  * @gpt: Pointer to gpt private data structure
 476  *
 477  * Returns an error if attempting to stop a wdt
 478  */
 479 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
 480 {
 481         unsigned long flags;
 482
 483         /* reject the operation if the timer is used as watchdog (gpt 0 only) */
 484         spin_lock_irqsave(&gpt->lock, flags);
 485         if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
 486                 spin_unlock_irqrestore(&gpt->lock, flags);
 487                 return -EBUSY;
 488         }
 489
 490         clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
 491         spin_unlock_irqrestore(&gpt->lock, flags);
 492         return 0;
 493 }
 494 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
 495
 496 /**
 497  * mpc52xx_gpt_timer_period - Read the timer period
 498  * @gpt: Pointer to gpt private data structure
 499  *
 500  * Returns the timer period in ns
 501  */
 502 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
 503 {
 504         u64 period;
 505         u64 prescale;
 506         unsigned long flags;
 507
 508         spin_lock_irqsave(&gpt->lock, flags);
 509         period = in_be32(&gpt->regs->count);
 510         spin_unlock_irqrestore(&gpt->lock, flags);
 511
 512         prescale = period >> 16;
 513         period &= 0xffff;
 514         if (prescale == 0)
 515                 prescale = 0x10000;
 516         period = period * prescale * 1000000000ULL;
 517         do_div(period, (u64)gpt->ipb_freq);
 518         return period;
 519 }
 520 EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
 521
 522 #if defined(CONFIG_MPC5200_WDT)
 523 /***********************************************************************
 524  * Watchdog API for gpt0
 525  */
 526
 527 #define WDT_IDENTITY        "mpc52xx watchdog on GPT0"
 528
 529 /* wdt_is_active stores whether or not the /dev/watchdog device is opened */
 530 static unsigned long wdt_is_active;
 531
 532 /* wdt-capable gpt */
 533 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
 534
 535 /* low-level wdt functions */
 536 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
 537 {
 538         unsigned long flags;
 539
 540         spin_lock_irqsave(&gpt_wdt->lock, flags);
 541         out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
 542         spin_unlock_irqrestore(&gpt_wdt->lock, flags);
 543 }
 544
 545 /* wdt misc device api */
 546 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
 547                                  size_t len, loff_t *ppos)
 548 {
 549         struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
 550         mpc52xx_gpt_wdt_ping(gpt_wdt);
 551         return 0;
 552 }
 553
 554 static const struct watchdog_info mpc5200_wdt_info = {
 555         .options        = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
 556         .identity       = WDT_IDENTITY,
 557 };
 558
 559 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
 560                               unsigned long arg)
 561 {
 562         struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
 563         int __user *data = (int __user *)arg;
 564         int timeout;
 565         u64 real_timeout;
 566         int ret = 0;
 567
 568         switch (cmd) {
 569         case WDIOC_GETSUPPORT:
 570                 ret = copy_to_user(data, &mpc5200_wdt_info,
 571                                    sizeof(mpc5200_wdt_info));
 572                 if (ret)
 573                         ret = -EFAULT;
 574                 break;
 575
 576         case WDIOC_GETSTATUS:
 577         case WDIOC_GETBOOTSTATUS:
 578                 ret = put_user(0, data);
 579                 break;
 580
 581         case WDIOC_KEEPALIVE:
 582                 mpc52xx_gpt_wdt_ping(gpt_wdt);
 583                 break;
 584
 585         case WDIOC_SETTIMEOUT:
 586                 ret = get_user(timeout, data);
 587                 if (ret)
 588                         break;
 589                 real_timeout = (u64) timeout * 1000000000ULL;
 590                 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
 591                 if (ret)
 592                         break;
 593                 /* fall through and return the timeout */
 594
 595         case WDIOC_GETTIMEOUT:
 596                 /* we need to round here as to avoid e.g. the following
 597                  * situation:
 598                  * - timeout requested is 1 second;
 599                  * - real timeout @33MHz is 999997090ns
 600                  * - the int divide by 10^9 will return 0.
 601                  */
 602                 real_timeout =
 603                         mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
 604                 do_div(real_timeout, 1000000000ULL);
 605                 timeout = (int) real_timeout;
 606                 ret = put_user(timeout, data);
 607                 break;
 608
 609         default:
 610                 ret = -ENOTTY;
 611         }
 612         return ret;
 613 }
 614
 615 static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
 616 {
 617         int ret;
 618
 619         /* sanity check */
 620         if (!mpc52xx_gpt_wdt)
 621                 return -ENODEV;
 622
 623         /* /dev/watchdog can only be opened once */
 624         if (test_and_set_bit(0, &wdt_is_active))
 625                 return -EBUSY;
 626
 627         /* Set and activate the watchdog with 30 seconds timeout */
 628         ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
 629                                    0, 1);
 630         if (ret) {
 631                 clear_bit(0, &wdt_is_active);
 632                 return ret;
 633         }
 634
 635         file->private_data = mpc52xx_gpt_wdt;
 636         return nonseekable_open(inode, file);
 637 }
 638
 639 static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
 640 {
 641         /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
 642 #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
 643         struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
 644         unsigned long flags;
 645
 646         spin_lock_irqsave(&gpt_wdt->lock, flags);
 647         clrbits32(&gpt_wdt->regs->mode,
 648                   MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
 649         gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
 650         spin_unlock_irqrestore(&gpt_wdt->lock, flags);
 651 #endif
 652         clear_bit(0, &wdt_is_active);
 653         return 0;
 654 }
 655
 656
 657 static const struct file_operations mpc52xx_wdt_fops = {
 658         .owner          = THIS_MODULE,
 659         .llseek         = no_llseek,
 660         .write          = mpc52xx_wdt_write,
 661         .unlocked_ioctl = mpc52xx_wdt_ioctl,
 662         .open           = mpc52xx_wdt_open,
 663         .release        = mpc52xx_wdt_release,
 664 };
 665
 666 static struct miscdevice mpc52xx_wdt_miscdev = {
 667         .minor          = WATCHDOG_MINOR,
 668         .name           = "watchdog",
 669         .fops           = &mpc52xx_wdt_fops,
 670 };
 671
 672 static int mpc52xx_gpt_wdt_init(void)
 673 {
 674         int err;
 675
 676         /* try to register the watchdog misc device */
 677         err = misc_register(&mpc52xx_wdt_miscdev);
 678         if (err)
 679                 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
 680         else
 681                 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
 682         return err;
 683 }
 684
 685 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
 686                                  const u32 *period)
 687 {
 688         u64 real_timeout;
 689
 690         /* remember the gpt for the wdt operation */
 691         mpc52xx_gpt_wdt = gpt;
 692
 693         /* configure the wdt if the device tree contained a timeout */
 694         if (!period || *period == 0)
 695                 return 0;
 696
 697         real_timeout = (u64) *period * 1000000000ULL;
 698         if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
 699                 dev_warn(gpt->dev, "starting as wdt failed\n");
 700         else
 701                 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
 702         return 0;
 703 }
 704
 705 #else
 706
 707 static int mpc52xx_gpt_wdt_init(void)
 708 {
 709         return 0;
 710 }
 711
 712 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
 713                                         const u32 *period)
 714 {
 715         return 0;
 716 }
 717
 718 #endif  /*  CONFIG_MPC5200_WDT  */
 719
 720 /* ---------------------------------------------------------------------
 721  * of_platform bus binding code
 722  */
 723 static int mpc52xx_gpt_probe(struct platform_device *ofdev)
 724 {
 725         struct mpc52xx_gpt_priv *gpt;
 726
 727         gpt = kzalloc(sizeof *gpt, GFP_KERNEL);
 728         if (!gpt)
 729                 return -ENOMEM;
 730
 731         spin_lock_init(&gpt->lock);
 732         gpt->dev = &ofdev->dev;
 733         gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
 734         gpt->regs = of_iomap(ofdev->dev.of_node, 0);
 735         if (!gpt->regs) {
 736                 kfree(gpt);
 737                 return -ENOMEM;
 738         }
 739
 740         dev_set_drvdata(&ofdev->dev, gpt);
 741
 742         mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node);
 743         mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
 744
 745         mutex_lock(&mpc52xx_gpt_list_mutex);
 746         list_add(&gpt->list, &mpc52xx_gpt_list);
 747         mutex_unlock(&mpc52xx_gpt_list_mutex);
 748
 749         /* check if this device could be a watchdog */
 750         if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
 751             of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
 752                 const u32 *on_boot_wdt;
 753
 754                 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
 755                 on_boot_wdt = of_get_property(ofdev->dev.of_node,
 756                                               "fsl,wdt-on-boot", NULL);
 757                 if (on_boot_wdt) {
 758                         dev_info(gpt->dev, "used as watchdog\n");
 759                         gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
 760                 } else
 761                         dev_info(gpt->dev, "can function as watchdog\n");
 762                 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
 763         }
 764
 765         return 0;
 766 }
 767
 768 static int mpc52xx_gpt_remove(struct platform_device *ofdev)
 769 {
 770         return -EBUSY;
 771 }
 772
 773 static const struct of_device_id mpc52xx_gpt_match[] = {
 774         { .compatible = "fsl,mpc5200-gpt", },
 775
 776         /* Depreciated compatible values; don't use for new dts files */
 777         { .compatible = "fsl,mpc5200-gpt-gpio", },
 778         { .compatible = "mpc5200-gpt", },
 779         {}
 780 };
 781
 782 static struct platform_driver mpc52xx_gpt_driver = {
 783         .driver = {
 784                 .name = "mpc52xx-gpt",
 785                 .owner = THIS_MODULE,
 786                 .of_match_table = mpc52xx_gpt_match,
 787         },
 788         .probe = mpc52xx_gpt_probe,
 789         .remove = mpc52xx_gpt_remove,
 790 };
 791
 792 static int __init mpc52xx_gpt_init(void)
 793 {
 794         return platform_driver_register(&mpc52xx_gpt_driver);
 795 }
 796
 797 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
 798 subsys_initcall(mpc52xx_gpt_init);
 799 device_initcall(mpc52xx_gpt_wdt_init);