2 * SMP support for power macintosh.
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/hardirq.h>
34 #include <linux/cpu.h>
35 #include <linux/compiler.h>
37 #include <asm/ptrace.h>
38 #include <linux/atomic.h>
39 #include <asm/code-patching.h>
42 #include <asm/pgtable.h>
43 #include <asm/sections.h>
47 #include <asm/machdep.h>
48 #include <asm/pmac_feature.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54 #include <asm/pmac_pfunc.h>
61 #define DBG(fmt...) udbg_printf(fmt)
66 extern void __secondary_start_pmac_0(void);
67 extern int pmac_pfunc_base_install(void);
69 static void (*pmac_tb_freeze
)(int freeze
);
73 #ifdef CONFIG_PPC_PMAC32_PSURGE
76 * Powersurge (old powermac SMP) support.
79 /* Addresses for powersurge registers */
80 #define HAMMERHEAD_BASE 0xf8000000
81 #define HHEAD_CONFIG 0x90
82 #define HHEAD_SEC_INTR 0xc0
84 /* register for interrupting the primary processor on the powersurge */
85 /* N.B. this is actually the ethernet ROM! */
86 #define PSURGE_PRI_INTR 0xf3019000
88 /* register for storing the start address for the secondary processor */
89 /* N.B. this is the PCI config space address register for the 1st bridge */
90 #define PSURGE_START 0xf2800000
92 /* Daystar/XLR8 4-CPU card */
93 #define PSURGE_QUAD_REG_ADDR 0xf8800000
95 #define PSURGE_QUAD_IRQ_SET 0
96 #define PSURGE_QUAD_IRQ_CLR 1
97 #define PSURGE_QUAD_IRQ_PRIMARY 2
98 #define PSURGE_QUAD_CKSTOP_CTL 3
99 #define PSURGE_QUAD_PRIMARY_ARB 4
100 #define PSURGE_QUAD_BOARD_ID 6
101 #define PSURGE_QUAD_WHICH_CPU 7
102 #define PSURGE_QUAD_CKSTOP_RDBK 8
103 #define PSURGE_QUAD_RESET_CTL 11
105 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
106 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
107 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
108 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
110 /* virtual addresses for the above */
111 static volatile u8 __iomem
*hhead_base
;
112 static volatile u8 __iomem
*quad_base
;
113 static volatile u32 __iomem
*psurge_pri_intr
;
114 static volatile u8 __iomem
*psurge_sec_intr
;
115 static volatile u32 __iomem
*psurge_start
;
117 /* values for psurge_type */
118 #define PSURGE_NONE -1
119 #define PSURGE_DUAL 0
120 #define PSURGE_QUAD_OKEE 1
121 #define PSURGE_QUAD_COTTON 2
122 #define PSURGE_QUAD_ICEGRASS 3
124 /* what sort of powersurge board we have */
125 static int psurge_type
= PSURGE_NONE
;
127 /* irq for secondary cpus to report */
128 static struct irq_domain
*psurge_host
;
129 int psurge_secondary_virq
;
132 * Set and clear IPIs for powersurge.
134 static inline void psurge_set_ipi(int cpu
)
136 if (psurge_type
== PSURGE_NONE
)
139 in_be32(psurge_pri_intr
);
140 else if (psurge_type
== PSURGE_DUAL
)
141 out_8(psurge_sec_intr
, 0);
143 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET
, 1 << cpu
);
146 static inline void psurge_clr_ipi(int cpu
)
149 switch(psurge_type
) {
151 out_8(psurge_sec_intr
, ~0);
155 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, 1 << cpu
);
161 * On powersurge (old SMP powermac architecture) we don't have
162 * separate IPIs for separate messages like openpic does. Instead
163 * use the generic demux helpers
166 static irqreturn_t
psurge_ipi_intr(int irq
, void *d
)
168 psurge_clr_ipi(smp_processor_id());
174 static void smp_psurge_cause_ipi(int cpu
, unsigned long data
)
179 static int psurge_host_map(struct irq_domain
*h
, unsigned int virq
,
182 irq_set_chip_and_handler(virq
, &dummy_irq_chip
, handle_percpu_irq
);
187 static const struct irq_domain_ops psurge_host_ops
= {
188 .map
= psurge_host_map
,
191 static int psurge_secondary_ipi_init(void)
195 psurge_host
= irq_domain_add_nomap(NULL
, 0, &psurge_host_ops
, NULL
);
198 psurge_secondary_virq
= irq_create_direct_mapping(psurge_host
);
200 if (psurge_secondary_virq
)
201 rc
= request_irq(psurge_secondary_virq
, psurge_ipi_intr
,
202 IRQF_PERCPU
| IRQF_NO_THREAD
, "IPI", NULL
);
205 pr_err("Failed to setup secondary cpu IPI\n");
211 * Determine a quad card presence. We read the board ID register, we
212 * force the data bus to change to something else, and we read it again.
213 * It it's stable, then the register probably exist (ugh !)
215 static int __init
psurge_quad_probe(void)
220 type
= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
);
221 if (type
< PSURGE_QUAD_OKEE
|| type
> PSURGE_QUAD_ICEGRASS
222 || type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
225 /* looks OK, try a slightly more rigorous test */
226 /* bogus is not necessarily cacheline-aligned,
227 though I don't suppose that really matters. -- paulus */
228 for (i
= 0; i
< 100; i
++) {
229 volatile u32 bogus
[8];
230 bogus
[(0+i
)%8] = 0x00000000;
231 bogus
[(1+i
)%8] = 0x55555555;
232 bogus
[(2+i
)%8] = 0xFFFFFFFF;
233 bogus
[(3+i
)%8] = 0xAAAAAAAA;
234 bogus
[(4+i
)%8] = 0x33333333;
235 bogus
[(5+i
)%8] = 0xCCCCCCCC;
236 bogus
[(6+i
)%8] = 0xCCCCCCCC;
237 bogus
[(7+i
)%8] = 0x33333333;
239 asm volatile("dcbf 0,%0" : : "r" (bogus
) : "memory");
241 if (type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
247 static void __init
psurge_quad_init(void)
251 if (ppc_md
.progress
) ppc_md
.progress("psurge_quad_init", 0x351);
252 procbits
= ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU
);
253 if (psurge_type
== PSURGE_QUAD_ICEGRASS
)
254 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
256 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
258 out_8(psurge_sec_intr
, ~0);
259 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, procbits
);
260 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
261 if (psurge_type
!= PSURGE_QUAD_ICEGRASS
)
262 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
263 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
265 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL
, procbits
);
267 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
271 static int __init
smp_psurge_probe(void)
274 struct device_node
*dn
;
276 /* We don't do SMP on the PPC601 -- paulus */
277 if (PVR_VER(mfspr(SPRN_PVR
)) == 1)
281 * The powersurge cpu board can be used in the generation
282 * of powermacs that have a socket for an upgradeable cpu card,
283 * including the 7500, 8500, 9500, 9600.
284 * The device tree doesn't tell you if you have 2 cpus because
285 * OF doesn't know anything about the 2nd processor.
286 * Instead we look for magic bits in magic registers,
287 * in the hammerhead memory controller in the case of the
288 * dual-cpu powersurge board. -- paulus.
290 dn
= of_find_node_by_name(NULL
, "hammerhead");
295 hhead_base
= ioremap(HAMMERHEAD_BASE
, 0x800);
296 quad_base
= ioremap(PSURGE_QUAD_REG_ADDR
, 1024);
297 psurge_sec_intr
= hhead_base
+ HHEAD_SEC_INTR
;
299 psurge_type
= psurge_quad_probe();
300 if (psurge_type
!= PSURGE_DUAL
) {
302 /* All released cards using this HW design have 4 CPUs */
304 /* No sure how timebase sync works on those, let's use SW */
305 smp_ops
->give_timebase
= smp_generic_give_timebase
;
306 smp_ops
->take_timebase
= smp_generic_take_timebase
;
309 if ((in_8(hhead_base
+ HHEAD_CONFIG
) & 0x02) == 0) {
310 /* not a dual-cpu card */
312 psurge_type
= PSURGE_NONE
;
318 if (psurge_secondary_ipi_init())
321 psurge_start
= ioremap(PSURGE_START
, 4);
322 psurge_pri_intr
= ioremap(PSURGE_PRI_INTR
, 4);
324 /* This is necessary because OF doesn't know about the
325 * secondary cpu(s), and thus there aren't nodes in the
326 * device tree for them, and smp_setup_cpu_maps hasn't
327 * set their bits in cpu_present_mask.
331 for (i
= 1; i
< ncpus
; ++i
)
332 set_cpu_present(i
, true);
334 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_probe - done", 0x352);
339 static int __init
smp_psurge_kick_cpu(int nr
)
341 unsigned long start
= __pa(__secondary_start_pmac_0
) + nr
* 8;
342 unsigned long a
, flags
;
345 /* Defining this here is evil ... but I prefer hiding that
346 * crap to avoid giving people ideas that they can do the
349 extern volatile unsigned int cpu_callin_map
[NR_CPUS
];
351 /* may need to flush here if secondary bats aren't setup */
352 for (a
= KERNELBASE
; a
< KERNELBASE
+ 0x800000; a
+= 32)
353 asm volatile("dcbf 0,%0" : : "r" (a
) : "memory");
354 asm volatile("sync");
356 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu", 0x353);
358 /* This is going to freeze the timeebase, we disable interrupts */
359 local_irq_save(flags
);
361 out_be32(psurge_start
, start
);
367 * We can't use udelay here because the timebase is now frozen.
369 for (i
= 0; i
< 2000; ++i
)
370 asm volatile("nop" : : : "memory");
374 * Also, because the timebase is frozen, we must not return to the
375 * caller which will try to do udelay's etc... Instead, we wait -here-
376 * for the CPU to callin.
378 for (i
= 0; i
< 100000 && !cpu_callin_map
[nr
]; ++i
) {
379 for (j
= 1; j
< 10000; j
++)
380 asm volatile("nop" : : : "memory");
381 asm volatile("sync" : : : "memory");
383 if (!cpu_callin_map
[nr
])
386 /* And we do the TB sync here too for standard dual CPU cards */
387 if (psurge_type
== PSURGE_DUAL
) {
399 /* now interrupt the secondary, restarting both TBs */
400 if (psurge_type
== PSURGE_DUAL
)
403 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu - done", 0x354);
408 static struct irqaction psurge_irqaction
= {
409 .handler
= psurge_ipi_intr
,
410 .flags
= IRQF_PERCPU
| IRQF_NO_THREAD
,
411 .name
= "primary IPI",
414 static void __init
smp_psurge_setup_cpu(int cpu_nr
)
416 if (cpu_nr
!= 0 || !psurge_start
)
419 /* reset the entry point so if we get another intr we won't
420 * try to startup again */
421 out_be32(psurge_start
, 0x100);
422 if (setup_irq(irq_create_mapping(NULL
, 30), &psurge_irqaction
))
423 printk(KERN_ERR
"Couldn't get primary IPI interrupt");
426 void __init
smp_psurge_take_timebase(void)
428 if (psurge_type
!= PSURGE_DUAL
)
436 set_tb(timebase
>> 32, timebase
& 0xffffffff);
439 set_dec(tb_ticks_per_jiffy
/2);
442 void __init
smp_psurge_give_timebase(void)
444 /* Nothing to do here */
447 /* PowerSurge-style Macs */
448 struct smp_ops_t psurge_smp_ops
= {
449 .message_pass
= NULL
, /* Use smp_muxed_ipi_message_pass */
450 .cause_ipi
= smp_psurge_cause_ipi
,
451 .probe
= smp_psurge_probe
,
452 .kick_cpu
= smp_psurge_kick_cpu
,
453 .setup_cpu
= smp_psurge_setup_cpu
,
454 .give_timebase
= smp_psurge_give_timebase
,
455 .take_timebase
= smp_psurge_take_timebase
,
457 #endif /* CONFIG_PPC_PMAC32_PSURGE */
460 * Core 99 and later support
464 static void smp_core99_give_timebase(void)
468 local_irq_save(flags
);
473 (*pmac_tb_freeze
)(1);
480 (*pmac_tb_freeze
)(0);
483 local_irq_restore(flags
);
487 static void smp_core99_take_timebase(void)
491 local_irq_save(flags
);
498 set_tb(timebase
>> 32, timebase
& 0xffffffff);
502 local_irq_restore(flags
);
507 * G5s enable/disable the timebase via an i2c-connected clock chip.
509 static struct pmac_i2c_bus
*pmac_tb_clock_chip_host
;
510 static u8 pmac_tb_pulsar_addr
;
512 static void smp_core99_cypress_tb_freeze(int freeze
)
517 /* Strangely, the device-tree says address is 0xd2, but darwin
520 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
521 pmac_i2c_mode_combined
);
522 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
523 0xd0 | pmac_i2c_read
,
528 data
= (data
& 0xf3) | (freeze
? 0x00 : 0x0c);
530 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
531 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
532 0xd0 | pmac_i2c_write
,
537 printk("Cypress Timebase %s rc: %d\n",
538 freeze
? "freeze" : "unfreeze", rc
);
539 panic("Timebase freeze failed !\n");
544 static void smp_core99_pulsar_tb_freeze(int freeze
)
549 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
550 pmac_i2c_mode_combined
);
551 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
552 pmac_tb_pulsar_addr
| pmac_i2c_read
,
557 data
= (data
& 0x88) | (freeze
? 0x11 : 0x22);
559 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
560 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
561 pmac_tb_pulsar_addr
| pmac_i2c_write
,
565 printk(KERN_ERR
"Pulsar Timebase %s rc: %d\n",
566 freeze
? "freeze" : "unfreeze", rc
);
567 panic("Timebase freeze failed !\n");
571 static void __init
smp_core99_setup_i2c_hwsync(int ncpus
)
573 struct device_node
*cc
= NULL
;
574 struct device_node
*p
;
575 const char *name
= NULL
;
579 /* Look for the clock chip */
580 while ((cc
= of_find_node_by_name(cc
, "i2c-hwclock")) != NULL
) {
581 p
= of_get_parent(cc
);
582 ok
= p
&& of_device_is_compatible(p
, "uni-n-i2c");
587 pmac_tb_clock_chip_host
= pmac_i2c_find_bus(cc
);
588 if (pmac_tb_clock_chip_host
== NULL
)
590 reg
= of_get_property(cc
, "reg", NULL
);
595 if (of_device_is_compatible(cc
,"pulsar-legacy-slewing")) {
596 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
597 pmac_tb_pulsar_addr
= 0xd2;
599 } else if (of_device_is_compatible(cc
, "cy28508")) {
600 pmac_tb_freeze
= smp_core99_cypress_tb_freeze
;
605 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
606 pmac_tb_pulsar_addr
= 0xd4;
610 if (pmac_tb_freeze
!= NULL
)
613 if (pmac_tb_freeze
!= NULL
) {
614 /* Open i2c bus for synchronous access */
615 if (pmac_i2c_open(pmac_tb_clock_chip_host
, 1)) {
616 printk(KERN_ERR
"Failed top open i2c bus for clock"
617 " sync, fallback to software sync !\n");
620 printk(KERN_INFO
"Processor timebase sync using %s i2c clock\n",
625 pmac_tb_freeze
= NULL
;
626 pmac_tb_clock_chip_host
= NULL
;
632 * Newer G5s uses a platform function
635 static void smp_core99_pfunc_tb_freeze(int freeze
)
637 struct device_node
*cpus
;
638 struct pmf_args args
;
640 cpus
= of_find_node_by_path("/cpus");
641 BUG_ON(cpus
== NULL
);
643 args
.u
[0].v
= !freeze
;
644 pmf_call_function(cpus
, "cpu-timebase", &args
);
648 #else /* CONFIG_PPC64 */
651 * SMP G4 use a GPIO to enable/disable the timebase.
654 static unsigned int core99_tb_gpio
; /* Timebase freeze GPIO */
656 static void smp_core99_gpio_tb_freeze(int freeze
)
659 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 4);
661 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 0);
662 pmac_call_feature(PMAC_FTR_READ_GPIO
, NULL
, core99_tb_gpio
, 0);
666 #endif /* !CONFIG_PPC64 */
668 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
669 volatile static long int core99_l2_cache
;
670 volatile static long int core99_l3_cache
;
672 static void core99_init_caches(int cpu
)
675 if (!cpu_has_feature(CPU_FTR_L2CR
))
679 core99_l2_cache
= _get_L2CR();
680 printk("CPU0: L2CR is %lx\n", core99_l2_cache
);
682 printk("CPU%d: L2CR was %lx\n", cpu
, _get_L2CR());
684 _set_L2CR(core99_l2_cache
);
685 printk("CPU%d: L2CR set to %lx\n", cpu
, core99_l2_cache
);
688 if (!cpu_has_feature(CPU_FTR_L3CR
))
692 core99_l3_cache
= _get_L3CR();
693 printk("CPU0: L3CR is %lx\n", core99_l3_cache
);
695 printk("CPU%d: L3CR was %lx\n", cpu
, _get_L3CR());
697 _set_L3CR(core99_l3_cache
);
698 printk("CPU%d: L3CR set to %lx\n", cpu
, core99_l3_cache
);
700 #endif /* !CONFIG_PPC64 */
703 static void __init
smp_core99_setup(int ncpus
)
707 /* i2c based HW sync on some G5s */
708 if (of_machine_is_compatible("PowerMac7,2") ||
709 of_machine_is_compatible("PowerMac7,3") ||
710 of_machine_is_compatible("RackMac3,1"))
711 smp_core99_setup_i2c_hwsync(ncpus
);
713 /* pfunc based HW sync on recent G5s */
714 if (pmac_tb_freeze
== NULL
) {
715 struct device_node
*cpus
=
716 of_find_node_by_path("/cpus");
718 of_get_property(cpus
, "platform-cpu-timebase", NULL
)) {
719 pmac_tb_freeze
= smp_core99_pfunc_tb_freeze
;
720 printk(KERN_INFO
"Processor timebase sync using"
721 " platform function\n");
725 #else /* CONFIG_PPC64 */
727 /* GPIO based HW sync on ppc32 Core99 */
728 if (pmac_tb_freeze
== NULL
&& !of_machine_is_compatible("MacRISC4")) {
729 struct device_node
*cpu
;
730 const u32
*tbprop
= NULL
;
732 core99_tb_gpio
= KL_GPIO_TB_ENABLE
; /* default value */
733 cpu
= of_find_node_by_type(NULL
, "cpu");
735 tbprop
= of_get_property(cpu
, "timebase-enable", NULL
);
737 core99_tb_gpio
= *tbprop
;
740 pmac_tb_freeze
= smp_core99_gpio_tb_freeze
;
741 printk(KERN_INFO
"Processor timebase sync using"
742 " GPIO 0x%02x\n", core99_tb_gpio
);
745 #endif /* CONFIG_PPC64 */
747 /* No timebase sync, fallback to software */
748 if (pmac_tb_freeze
== NULL
) {
749 smp_ops
->give_timebase
= smp_generic_give_timebase
;
750 smp_ops
->take_timebase
= smp_generic_take_timebase
;
751 printk(KERN_INFO
"Processor timebase sync using software\n");
758 /* XXX should get this from reg properties */
759 for (i
= 1; i
< ncpus
; ++i
)
760 set_hard_smp_processor_id(i
, i
);
764 /* 32 bits SMP can't NAP */
765 if (!of_machine_is_compatible("MacRISC4"))
769 static int __init
smp_core99_probe(void)
771 struct device_node
*cpus
;
774 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_probe", 0x345);
776 /* Count CPUs in the device-tree */
777 for (cpus
= NULL
; (cpus
= of_find_node_by_type(cpus
, "cpu")) != NULL
;)
780 printk(KERN_INFO
"PowerMac SMP probe found %d cpus\n", ncpus
);
782 /* Nothing more to do if less than 2 of them */
786 /* We need to perform some early initialisations before we can start
787 * setting up SMP as we are running before initcalls
789 pmac_pfunc_base_install();
792 /* Setup various bits like timebase sync method, ability to nap, ... */
793 smp_core99_setup(ncpus
);
798 /* Collect l2cr and l3cr values from CPU 0 */
799 core99_init_caches(0);
804 static int smp_core99_kick_cpu(int nr
)
806 unsigned int save_vector
;
807 unsigned long target
, flags
;
808 unsigned int *vector
= (unsigned int *)(PAGE_OFFSET
+0x100);
810 if (nr
< 0 || nr
> 3)
814 ppc_md
.progress("smp_core99_kick_cpu", 0x346);
816 local_irq_save(flags
);
818 /* Save reset vector */
819 save_vector
= *vector
;
821 /* Setup fake reset vector that does
822 * b __secondary_start_pmac_0 + nr*8
824 target
= (unsigned long) __secondary_start_pmac_0
+ nr
* 8;
825 patch_branch(vector
, target
, BRANCH_SET_LINK
);
827 /* Put some life in our friend */
828 pmac_call_feature(PMAC_FTR_RESET_CPU
, NULL
, nr
, 0);
830 /* FIXME: We wait a bit for the CPU to take the exception, I should
831 * instead wait for the entry code to set something for me. Well,
832 * ideally, all that crap will be done in prom.c and the CPU left
833 * in a RAM-based wait loop like CHRP.
837 /* Restore our exception vector */
838 *vector
= save_vector
;
839 flush_icache_range((unsigned long) vector
, (unsigned long) vector
+ 4);
841 local_irq_restore(flags
);
842 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_kick_cpu done", 0x347);
847 static void smp_core99_setup_cpu(int cpu_nr
)
851 core99_init_caches(cpu_nr
);
854 mpic_setup_this_cpu();
858 #ifdef CONFIG_HOTPLUG_CPU
859 static int smp_core99_cpu_notify(struct notifier_block
*self
,
860 unsigned long action
, void *hcpu
)
866 case CPU_UP_PREPARE_FROZEN
:
867 /* Open i2c bus if it was used for tb sync */
868 if (pmac_tb_clock_chip_host
) {
869 rc
= pmac_i2c_open(pmac_tb_clock_chip_host
, 1);
871 pr_err("Failed to open i2c bus for time sync\n");
872 return notifier_from_errno(rc
);
877 case CPU_UP_CANCELED
:
878 /* Close i2c bus if it was used for tb sync */
879 if (pmac_tb_clock_chip_host
)
880 pmac_i2c_close(pmac_tb_clock_chip_host
);
888 static struct notifier_block __cpuinitdata smp_core99_cpu_nb
= {
889 .notifier_call
= smp_core99_cpu_notify
,
891 #endif /* CONFIG_HOTPLUG_CPU */
893 static void __init
smp_core99_bringup_done(void)
895 extern void g5_phy_disable_cpu1(void);
897 /* Close i2c bus if it was used for tb sync */
898 if (pmac_tb_clock_chip_host
)
899 pmac_i2c_close(pmac_tb_clock_chip_host
);
901 /* If we didn't start the second CPU, we must take
904 if (of_machine_is_compatible("MacRISC4") &&
905 num_online_cpus() < 2) {
906 set_cpu_present(1, false);
907 g5_phy_disable_cpu1();
909 #ifdef CONFIG_HOTPLUG_CPU
910 register_cpu_notifier(&smp_core99_cpu_nb
);
914 ppc_md
.progress("smp_core99_bringup_done", 0x349);
916 #endif /* CONFIG_PPC64 */
918 #ifdef CONFIG_HOTPLUG_CPU
920 static int smp_core99_cpu_disable(void)
922 int rc
= generic_cpu_disable();
926 mpic_cpu_set_priority(0xf);
933 static void pmac_cpu_die(void)
935 int cpu
= smp_processor_id();
939 pr_debug("CPU%d offline\n", cpu
);
940 generic_set_cpu_dead(cpu
);
946 #else /* CONFIG_PPC32 */
948 static void pmac_cpu_die(void)
950 int cpu
= smp_processor_id();
956 * turn off as much as possible, we'll be
957 * kicked out as this will only be invoked
958 * on core99 platforms for now ...
961 printk(KERN_INFO
"CPU#%d offline\n", cpu
);
962 generic_set_cpu_dead(cpu
);
966 * Re-enable interrupts. The NAP code needs to enable them
967 * anyways, do it now so we deal with the case where one already
968 * happened while soft-disabled.
969 * We shouldn't get any external interrupts, only decrementer, and the
970 * decrementer handler is safe for use on offline CPUs
975 /* let's not take timer interrupts too often ... */
983 #endif /* else CONFIG_PPC32 */
984 #endif /* CONFIG_HOTPLUG_CPU */
986 /* Core99 Macs (dual G4s and G5s) */
987 struct smp_ops_t core99_smp_ops
= {
988 .message_pass
= smp_mpic_message_pass
,
989 .probe
= smp_core99_probe
,
991 .bringup_done
= smp_core99_bringup_done
,
993 .kick_cpu
= smp_core99_kick_cpu
,
994 .setup_cpu
= smp_core99_setup_cpu
,
995 .give_timebase
= smp_core99_give_timebase
,
996 .take_timebase
= smp_core99_take_timebase
,
997 #if defined(CONFIG_HOTPLUG_CPU)
998 .cpu_disable
= smp_core99_cpu_disable
,
999 .cpu_die
= generic_cpu_die
,
1003 void __init
pmac_setup_smp(void)
1005 struct device_node
*np
;
1007 /* Check for Core99 */
1008 np
= of_find_node_by_name(NULL
, "uni-n");
1010 np
= of_find_node_by_name(NULL
, "u3");
1012 np
= of_find_node_by_name(NULL
, "u4");
1015 smp_ops
= &core99_smp_ops
;
1017 #ifdef CONFIG_PPC_PMAC32_PSURGE
1019 /* We have to set bits in cpu_possible_mask here since the
1020 * secondary CPU(s) aren't in the device tree. Various
1021 * things won't be initialized for CPUs not in the possible
1022 * map, so we really need to fix it up here.
1026 for (cpu
= 1; cpu
< 4 && cpu
< NR_CPUS
; ++cpu
)
1027 set_cpu_possible(cpu
, true);
1028 smp_ops
= &psurge_smp_ops
;
1030 #endif /* CONFIG_PPC_PMAC32_PSURGE */
1032 #ifdef CONFIG_HOTPLUG_CPU
1033 ppc_md
.cpu_die
= pmac_cpu_die
;