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x86, efi: Set runtime_version to the EFI spec revision
[linux/fpc-iii.git] / arch / powerpc / platforms / powernv / pci-ioda.c
blob8e90e8906df305b422b7f47b02772c9eb6c552d0
1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/bootmem.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/msi.h>
23
24 #include <asm/sections.h>
25 #include <asm/io.h>
26 #include <asm/prom.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/machdep.h>
29 #include <asm/ppc-pci.h>
30 #include <asm/opal.h>
31 #include <asm/iommu.h>
32 #include <asm/tce.h>
33
34 #include "powernv.h"
35 #include "pci.h"
36
37 #define define_pe_printk_level(func, kern_level) \
38 static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \
39 { \
40 struct va_format vaf; \
41 va_list args; \
42 char pfix[32]; \
43 int r; \
44 \
45 va_start(args, fmt); \
46 \
47 vaf.fmt = fmt; \
48 vaf.va = &args; \
49 \
50 if (pe->pdev) \
51 strlcpy(pfix, dev_name(&pe->pdev->dev), \
52 sizeof(pfix)); \
53 else \
54 sprintf(pfix, "%04x:%02x ", \
55 pci_domain_nr(pe->pbus), \
56 pe->pbus->number); \
57 r = printk(kern_level "pci %s: [PE# %.3d] %pV", \
58 pfix, pe->pe_number, &vaf); \
59 \
60 va_end(args); \
61 \
62 return r; \
63 } \
64
65 define_pe_printk_level(pe_err, KERN_ERR);
66 define_pe_printk_level(pe_warn, KERN_WARNING);
67 define_pe_printk_level(pe_info, KERN_INFO);
68
69 static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
70 {
71 struct device_node *np;
72
73 np = pci_device_to_OF_node(dev);
74 if (!np)
75 return NULL;
76 return PCI_DN(np);
77 }
78
79 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
80 {
81 unsigned long pe;
82
83 do {
84 pe = find_next_zero_bit(phb->ioda.pe_alloc,
85 phb->ioda.total_pe, 0);
86 if (pe >= phb->ioda.total_pe)
87 return IODA_INVALID_PE;
88 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
89
90 phb->ioda.pe_array[pe].pe_number = pe;
91 return pe;
92 }
93
94 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
95 {
96 WARN_ON(phb->ioda.pe_array[pe].pdev);
97
98 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
99 clear_bit(pe, phb->ioda.pe_alloc);
100 }
101
102 /* Currently those 2 are only used when MSIs are enabled, this will change
103 * but in the meantime, we need to protect them to avoid warnings
104 */
105 #ifdef CONFIG_PCI_MSI
106 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
107 {
108 struct pci_controller *hose = pci_bus_to_host(dev->bus);
109 struct pnv_phb *phb = hose->private_data;
110 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
111
112 if (!pdn)
113 return NULL;
114 if (pdn->pe_number == IODA_INVALID_PE)
115 return NULL;
116 return &phb->ioda.pe_array[pdn->pe_number];
117 }
118 #endif /* CONFIG_PCI_MSI */
119
120 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
121 {
122 struct pci_dev *parent;
123 uint8_t bcomp, dcomp, fcomp;
124 long rc, rid_end, rid;
125
126 /* Bus validation ? */
127 if (pe->pbus) {
128 int count;
129
130 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
131 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
132 parent = pe->pbus->self;
133 if (pe->flags & PNV_IODA_PE_BUS_ALL)
134 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
135 else
136 count = 1;
137
138 switch(count) {
139 case 1: bcomp = OpalPciBusAll; break;
140 case 2: bcomp = OpalPciBus7Bits; break;
141 case 4: bcomp = OpalPciBus6Bits; break;
142 case 8: bcomp = OpalPciBus5Bits; break;
143 case 16: bcomp = OpalPciBus4Bits; break;
144 case 32: bcomp = OpalPciBus3Bits; break;
145 default:
146 pr_err("%s: Number of subordinate busses %d"
147 " unsupported\n",
148 pci_name(pe->pbus->self), count);
149 /* Do an exact match only */
150 bcomp = OpalPciBusAll;
151 }
152 rid_end = pe->rid + (count << 8);
153 } else {
154 parent = pe->pdev->bus->self;
155 bcomp = OpalPciBusAll;
156 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
157 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
158 rid_end = pe->rid + 1;
159 }
160
161 /* Associate PE in PELT */
162 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
163 bcomp, dcomp, fcomp, OPAL_MAP_PE);
164 if (rc) {
165 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
166 return -ENXIO;
167 }
168 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
169 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
170
171 /* Add to all parents PELT-V */
172 while (parent) {
173 struct pci_dn *pdn = pnv_ioda_get_pdn(parent);
174 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
175 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
176 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
177 /* XXX What to do in case of error ? */
178 }
179 parent = parent->bus->self;
180 }
181 /* Setup reverse map */
182 for (rid = pe->rid; rid < rid_end; rid++)
183 phb->ioda.pe_rmap[rid] = pe->pe_number;
184
185 /* Setup one MVTs on IODA1 */
186 if (phb->type == PNV_PHB_IODA1) {
187 pe->mve_number = pe->pe_number;
188 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
189 pe->pe_number);
190 if (rc) {
191 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
192 rc, pe->mve_number);
193 pe->mve_number = -1;
194 } else {
195 rc = opal_pci_set_mve_enable(phb->opal_id,
196 pe->mve_number, OPAL_ENABLE_MVE);
197 if (rc) {
198 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
199 rc, pe->mve_number);
200 pe->mve_number = -1;
201 }
202 }
203 } else if (phb->type == PNV_PHB_IODA2)
204 pe->mve_number = 0;
205
206 return 0;
207 }
208
209 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
210 struct pnv_ioda_pe *pe)
211 {
212 struct pnv_ioda_pe *lpe;
213
214 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
215 if (lpe->dma_weight < pe->dma_weight) {
216 list_add_tail(&pe->dma_link, &lpe->dma_link);
217 return;
218 }
219 }
220 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
221 }
222
223 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
224 {
225 /* This is quite simplistic. The "base" weight of a device
226 * is 10. 0 means no DMA is to be accounted for it.
227 */
228
229 /* If it's a bridge, no DMA */
230 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
231 return 0;
232
233 /* Reduce the weight of slow USB controllers */
234 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
235 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
236 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
237 return 3;
238
239 /* Increase the weight of RAID (includes Obsidian) */
240 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
241 return 15;
242
243 /* Default */
244 return 10;
245 }
246
247 #if 0
248 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
249 {
250 struct pci_controller *hose = pci_bus_to_host(dev->bus);
251 struct pnv_phb *phb = hose->private_data;
252 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
253 struct pnv_ioda_pe *pe;
254 int pe_num;
255
256 if (!pdn) {
257 pr_err("%s: Device tree node not associated properly\n",
258 pci_name(dev));
259 return NULL;
260 }
261 if (pdn->pe_number != IODA_INVALID_PE)
262 return NULL;
263
264 /* PE#0 has been pre-set */
265 if (dev->bus->number == 0)
266 pe_num = 0;
267 else
268 pe_num = pnv_ioda_alloc_pe(phb);
269 if (pe_num == IODA_INVALID_PE) {
270 pr_warning("%s: Not enough PE# available, disabling device\n",
271 pci_name(dev));
272 return NULL;
273 }
274
275 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
276 * pointer in the PE data structure, both should be destroyed at the
277 * same time. However, this needs to be looked at more closely again
278 * once we actually start removing things (Hotplug, SR-IOV, ...)
279 *
280 * At some point we want to remove the PDN completely anyways
281 */
282 pe = &phb->ioda.pe_array[pe_num];
283 pci_dev_get(dev);
284 pdn->pcidev = dev;
285 pdn->pe_number = pe_num;
286 pe->pdev = dev;
287 pe->pbus = NULL;
288 pe->tce32_seg = -1;
289 pe->mve_number = -1;
290 pe->rid = dev->bus->number << 8 | pdn->devfn;
291
292 pe_info(pe, "Associated device to PE\n");
293
294 if (pnv_ioda_configure_pe(phb, pe)) {
295 /* XXX What do we do here ? */
296 if (pe_num)
297 pnv_ioda_free_pe(phb, pe_num);
298 pdn->pe_number = IODA_INVALID_PE;
299 pe->pdev = NULL;
300 pci_dev_put(dev);
301 return NULL;
302 }
303
304 /* Assign a DMA weight to the device */
305 pe->dma_weight = pnv_ioda_dma_weight(dev);
306 if (pe->dma_weight != 0) {
307 phb->ioda.dma_weight += pe->dma_weight;
308 phb->ioda.dma_pe_count++;
309 }
310
311 /* Link the PE */
312 pnv_ioda_link_pe_by_weight(phb, pe);
313
314 return pe;
315 }
316 #endif /* Useful for SRIOV case */
317
318 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
319 {
320 struct pci_dev *dev;
321
322 list_for_each_entry(dev, &bus->devices, bus_list) {
323 struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
324
325 if (pdn == NULL) {
326 pr_warn("%s: No device node associated with device !\n",
327 pci_name(dev));
328 continue;
329 }
330 pci_dev_get(dev);
331 pdn->pcidev = dev;
332 pdn->pe_number = pe->pe_number;
333 pe->dma_weight += pnv_ioda_dma_weight(dev);
334 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
335 pnv_ioda_setup_same_PE(dev->subordinate, pe);
336 }
337 }
338
339 /*
340 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
341 * single PCI bus. Another one that contains the primary PCI bus and its
342 * subordinate PCI devices and buses. The second type of PE is normally
343 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
344 */
345 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
346 {
347 struct pci_controller *hose = pci_bus_to_host(bus);
348 struct pnv_phb *phb = hose->private_data;
349 struct pnv_ioda_pe *pe;
350 int pe_num;
351
352 pe_num = pnv_ioda_alloc_pe(phb);
353 if (pe_num == IODA_INVALID_PE) {
354 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
355 __func__, pci_domain_nr(bus), bus->number);
356 return;
357 }
358
359 pe = &phb->ioda.pe_array[pe_num];
360 pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
361 pe->pbus = bus;
362 pe->pdev = NULL;
363 pe->tce32_seg = -1;
364 pe->mve_number = -1;
365 pe->rid = bus->busn_res.start << 8;
366 pe->dma_weight = 0;
367
368 if (all)
369 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
370 bus->busn_res.start, bus->busn_res.end, pe_num);
371 else
372 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
373 bus->busn_res.start, pe_num);
374
375 if (pnv_ioda_configure_pe(phb, pe)) {
376 /* XXX What do we do here ? */
377 if (pe_num)
378 pnv_ioda_free_pe(phb, pe_num);
379 pe->pbus = NULL;
380 return;
381 }
382
383 /* Associate it with all child devices */
384 pnv_ioda_setup_same_PE(bus, pe);
385
386 /* Put PE to the list */
387 list_add_tail(&pe->list, &phb->ioda.pe_list);
388
389 /* Account for one DMA PE if at least one DMA capable device exist
390 * below the bridge
391 */
392 if (pe->dma_weight != 0) {
393 phb->ioda.dma_weight += pe->dma_weight;
394 phb->ioda.dma_pe_count++;
395 }
396
397 /* Link the PE */
398 pnv_ioda_link_pe_by_weight(phb, pe);
399 }
400
401 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
402 {
403 struct pci_dev *dev;
404
405 pnv_ioda_setup_bus_PE(bus, 0);
406
407 list_for_each_entry(dev, &bus->devices, bus_list) {
408 if (dev->subordinate) {
409 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
410 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
411 else
412 pnv_ioda_setup_PEs(dev->subordinate);
413 }
414 }
415 }
416
417 /*
418 * Configure PEs so that the downstream PCI buses and devices
419 * could have their associated PE#. Unfortunately, we didn't
420 * figure out the way to identify the PLX bridge yet. So we
421 * simply put the PCI bus and the subordinate behind the root
422 * port to PE# here. The game rule here is expected to be changed
423 * as soon as we can detected PLX bridge correctly.
424 */
425 static void pnv_pci_ioda_setup_PEs(void)
426 {
427 struct pci_controller *hose, *tmp;
428
429 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
430 pnv_ioda_setup_PEs(hose->bus);
431 }
432 }
433
434 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *dev)
435 {
436 /* We delay DMA setup after we have assigned all PE# */
437 }
438
439 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
440 {
441 struct pci_dev *dev;
442
443 list_for_each_entry(dev, &bus->devices, bus_list) {
444 set_iommu_table_base(&dev->dev, &pe->tce32_table);
445 if (dev->subordinate)
446 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
447 }
448 }
449
450 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
451 struct pnv_ioda_pe *pe, unsigned int base,
452 unsigned int segs)
453 {
454
455 struct page *tce_mem = NULL;
456 const __be64 *swinvp;
457 struct iommu_table *tbl;
458 unsigned int i;
459 int64_t rc;
460 void *addr;
461
462 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
463 #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
464
465 /* XXX FIXME: Handle 64-bit only DMA devices */
466 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
467 /* XXX FIXME: Allocate multi-level tables on PHB3 */
468
469 /* We shouldn't already have a 32-bit DMA associated */
470 if (WARN_ON(pe->tce32_seg >= 0))
471 return;
472
473 /* Grab a 32-bit TCE table */
474 pe->tce32_seg = base;
475 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
476 (base << 28), ((base + segs) << 28) - 1);
477
478 /* XXX Currently, we allocate one big contiguous table for the
479 * TCEs. We only really need one chunk per 256M of TCE space
480 * (ie per segment) but that's an optimization for later, it
481 * requires some added smarts with our get/put_tce implementation
482 */
483 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
484 get_order(TCE32_TABLE_SIZE * segs));
485 if (!tce_mem) {
486 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
487 goto fail;
488 }
489 addr = page_address(tce_mem);
490 memset(addr, 0, TCE32_TABLE_SIZE * segs);
491
492 /* Configure HW */
493 for (i = 0; i < segs; i++) {
494 rc = opal_pci_map_pe_dma_window(phb->opal_id,
495 pe->pe_number,
496 base + i, 1,
497 __pa(addr) + TCE32_TABLE_SIZE * i,
498 TCE32_TABLE_SIZE, 0x1000);
499 if (rc) {
500 pe_err(pe, " Failed to configure 32-bit TCE table,"
501 " err %ld\n", rc);
502 goto fail;
503 }
504 }
505
506 /* Setup linux iommu table */
507 tbl = &pe->tce32_table;
508 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
509 base << 28);
510
511 /* OPAL variant of P7IOC SW invalidated TCEs */
512 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
513 if (swinvp) {
514 /* We need a couple more fields -- an address and a data
515 * to or. Since the bus is only printed out on table free
516 * errors, and on the first pass the data will be a relative
517 * bus number, print that out instead.
518 */
519 tbl->it_busno = 0;
520 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
521 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE
522 | TCE_PCI_SWINV_PAIR;
523 }
524 iommu_init_table(tbl, phb->hose->node);
525
526 if (pe->pdev)
527 set_iommu_table_base(&pe->pdev->dev, tbl);
528 else
529 pnv_ioda_setup_bus_dma(pe, pe->pbus);
530
531 return;
532 fail:
533 /* XXX Failure: Try to fallback to 64-bit only ? */
534 if (pe->tce32_seg >= 0)
535 pe->tce32_seg = -1;
536 if (tce_mem)
537 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
538 }
539
540 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
541 {
542 struct pci_controller *hose = phb->hose;
543 unsigned int residual, remaining, segs, tw, base;
544 struct pnv_ioda_pe *pe;
545
546 /* If we have more PE# than segments available, hand out one
547 * per PE until we run out and let the rest fail. If not,
548 * then we assign at least one segment per PE, plus more based
549 * on the amount of devices under that PE
550 */
551 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
552 residual = 0;
553 else
554 residual = phb->ioda.tce32_count -
555 phb->ioda.dma_pe_count;
556
557 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
558 hose->global_number, phb->ioda.tce32_count);
559 pr_info("PCI: %d PE# for a total weight of %d\n",
560 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
561
562 /* Walk our PE list and configure their DMA segments, hand them
563 * out one base segment plus any residual segments based on
564 * weight
565 */
566 remaining = phb->ioda.tce32_count;
567 tw = phb->ioda.dma_weight;
568 base = 0;
569 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
570 if (!pe->dma_weight)
571 continue;
572 if (!remaining) {
573 pe_warn(pe, "No DMA32 resources available\n");
574 continue;
575 }
576 segs = 1;
577 if (residual) {
578 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw;
579 if (segs > remaining)
580 segs = remaining;
581 }
582 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
583 pe->dma_weight, segs);
584 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
585 remaining -= segs;
586 base += segs;
587 }
588 }
589
590 #ifdef CONFIG_PCI_MSI
591 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
592 unsigned int hwirq, unsigned int is_64,
593 struct msi_msg *msg)
594 {
595 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
596 unsigned int xive_num = hwirq - phb->msi_base;
597 uint64_t addr64;
598 uint32_t addr32, data;
599 int rc;
600
601 /* No PE assigned ? bail out ... no MSI for you ! */
602 if (pe == NULL)
603 return -ENXIO;
604
605 /* Check if we have an MVE */
606 if (pe->mve_number < 0)
607 return -ENXIO;
608
609 /* Assign XIVE to PE */
610 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
611 if (rc) {
612 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
613 pci_name(dev), rc, xive_num);
614 return -EIO;
615 }
616
617 if (is_64) {
618 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
619 &addr64, &data);
620 if (rc) {
621 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
622 pci_name(dev), rc);
623 return -EIO;
624 }
625 msg->address_hi = addr64 >> 32;
626 msg->address_lo = addr64 & 0xfffffffful;
627 } else {
628 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
629 &addr32, &data);
630 if (rc) {
631 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
632 pci_name(dev), rc);
633 return -EIO;
634 }
635 msg->address_hi = 0;
636 msg->address_lo = addr32;
637 }
638 msg->data = data;
639
640 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
641 " address=%x_%08x data=%x PE# %d\n",
642 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
643 msg->address_hi, msg->address_lo, data, pe->pe_number);
644
645 return 0;
646 }
647
648 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
649 {
650 unsigned int bmap_size;
651 const __be32 *prop = of_get_property(phb->hose->dn,
652 "ibm,opal-msi-ranges", NULL);
653 if (!prop) {
654 /* BML Fallback */
655 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
656 }
657 if (!prop)
658 return;
659
660 phb->msi_base = be32_to_cpup(prop);
661 phb->msi_count = be32_to_cpup(prop + 1);
662 bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
663 phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
664 if (!phb->msi_map) {
665 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
666 phb->hose->global_number);
667 return;
668 }
669 phb->msi_setup = pnv_pci_ioda_msi_setup;
670 phb->msi32_support = 1;
671 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
672 phb->msi_count, phb->msi_base);
673 }
674 #else
675 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
676 #endif /* CONFIG_PCI_MSI */
677
678 /*
679 * This function is supposed to be called on basis of PE from top
680 * to bottom style. So the the I/O or MMIO segment assigned to
681 * parent PE could be overrided by its child PEs if necessary.
682 */
683 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
684 struct pnv_ioda_pe *pe)
685 {
686 struct pnv_phb *phb = hose->private_data;
687 struct pci_bus_region region;
688 struct resource *res;
689 int i, index;
690 int rc;
691
692 /*
693 * NOTE: We only care PCI bus based PE for now. For PCI
694 * device based PE, for example SRIOV sensitive VF should
695 * be figured out later.
696 */
697 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
698
699 pci_bus_for_each_resource(pe->pbus, res, i) {
700 if (!res || !res->flags ||
701 res->start > res->end)
702 continue;
703
704 if (res->flags & IORESOURCE_IO) {
705 region.start = res->start - phb->ioda.io_pci_base;
706 region.end = res->end - phb->ioda.io_pci_base;
707 index = region.start / phb->ioda.io_segsize;
708
709 while (index < phb->ioda.total_pe &&
710 region.start <= region.end) {
711 phb->ioda.io_segmap[index] = pe->pe_number;
712 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
713 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
714 if (rc != OPAL_SUCCESS) {
715 pr_err("%s: OPAL error %d when mapping IO "
716 "segment #%d to PE#%d\n",
717 __func__, rc, index, pe->pe_number);
718 break;
719 }
720
721 region.start += phb->ioda.io_segsize;
722 index++;
723 }
724 } else if (res->flags & IORESOURCE_MEM) {
725 region.start = res->start -
726 hose->pci_mem_offset -
727 phb->ioda.m32_pci_base;
728 region.end = res->end -
729 hose->pci_mem_offset -
730 phb->ioda.m32_pci_base;
731 index = region.start / phb->ioda.m32_segsize;
732
733 while (index < phb->ioda.total_pe &&
734 region.start <= region.end) {
735 phb->ioda.m32_segmap[index] = pe->pe_number;
736 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
737 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
738 if (rc != OPAL_SUCCESS) {
739 pr_err("%s: OPAL error %d when mapping M32 "
740 "segment#%d to PE#%d",
741 __func__, rc, index, pe->pe_number);
742 break;
743 }
744
745 region.start += phb->ioda.m32_segsize;
746 index++;
747 }
748 }
749 }
750 }
751
752 static void pnv_pci_ioda_setup_seg(void)
753 {
754 struct pci_controller *tmp, *hose;
755 struct pnv_phb *phb;
756 struct pnv_ioda_pe *pe;
757
758 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
759 phb = hose->private_data;
760 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
761 pnv_ioda_setup_pe_seg(hose, pe);
762 }
763 }
764 }
765
766 static void pnv_pci_ioda_setup_DMA(void)
767 {
768 struct pci_controller *hose, *tmp;
769 struct pnv_phb *phb;
770
771 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
772 pnv_ioda_setup_dma(hose->private_data);
773
774 /* Mark the PHB initialization done */
775 phb = hose->private_data;
776 phb->initialized = 1;
777 }
778 }
779
780 static void pnv_pci_ioda_fixup(void)
781 {
782 pnv_pci_ioda_setup_PEs();
783 pnv_pci_ioda_setup_seg();
784 pnv_pci_ioda_setup_DMA();
785 }
786
787 /*
788 * Returns the alignment for I/O or memory windows for P2P
789 * bridges. That actually depends on how PEs are segmented.
790 * For now, we return I/O or M32 segment size for PE sensitive
791 * P2P bridges. Otherwise, the default values (4KiB for I/O,
792 * 1MiB for memory) will be returned.
793 *
794 * The current PCI bus might be put into one PE, which was
795 * create against the parent PCI bridge. For that case, we
796 * needn't enlarge the alignment so that we can save some
797 * resources.
798 */
799 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
800 unsigned long type)
801 {
802 struct pci_dev *bridge;
803 struct pci_controller *hose = pci_bus_to_host(bus);
804 struct pnv_phb *phb = hose->private_data;
805 int num_pci_bridges = 0;
806
807 bridge = bus->self;
808 while (bridge) {
809 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
810 num_pci_bridges++;
811 if (num_pci_bridges >= 2)
812 return 1;
813 }
814
815 bridge = bridge->bus->self;
816 }
817
818 /* We need support prefetchable memory window later */
819 if (type & IORESOURCE_MEM)
820 return phb->ioda.m32_segsize;
821
822 return phb->ioda.io_segsize;
823 }
824
825 /* Prevent enabling devices for which we couldn't properly
826 * assign a PE
827 */
828 static int pnv_pci_enable_device_hook(struct pci_dev *dev)
829 {
830 struct pci_controller *hose = pci_bus_to_host(dev->bus);
831 struct pnv_phb *phb = hose->private_data;
832 struct pci_dn *pdn;
833
834 /* The function is probably called while the PEs have
835 * not be created yet. For example, resource reassignment
836 * during PCI probe period. We just skip the check if
837 * PEs isn't ready.
838 */
839 if (!phb->initialized)
840 return 0;
841
842 pdn = pnv_ioda_get_pdn(dev);
843 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
844 return -EINVAL;
845
846 return 0;
847 }
848
849 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
850 u32 devfn)
851 {
852 return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
853 }
854
855 void __init pnv_pci_init_ioda1_phb(struct device_node *np)
856 {
857 struct pci_controller *hose;
858 static int primary = 1;
859 struct pnv_phb *phb;
860 unsigned long size, m32map_off, iomap_off, pemap_off;
861 const u64 *prop64;
862 u64 phb_id;
863 void *aux;
864 long rc;
865
866 pr_info(" Initializing IODA OPAL PHB %s\n", np->full_name);
867
868 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
869 if (!prop64) {
870 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
871 return;
872 }
873 phb_id = be64_to_cpup(prop64);
874 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
875
876 phb = alloc_bootmem(sizeof(struct pnv_phb));
877 if (phb) {
878 memset(phb, 0, sizeof(struct pnv_phb));
879 phb->hose = hose = pcibios_alloc_controller(np);
880 }
881 if (!phb || !phb->hose) {
882 pr_err("PCI: Failed to allocate PCI controller for %s\n",
883 np->full_name);
884 return;
885 }
886
887 spin_lock_init(&phb->lock);
888 /* XXX Use device-tree */
889 hose->first_busno = 0;
890 hose->last_busno = 0xff;
891 hose->private_data = phb;
892 phb->opal_id = phb_id;
893 phb->type = PNV_PHB_IODA1;
894
895 /* Detect specific models for error handling */
896 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
897 phb->model = PNV_PHB_MODEL_P7IOC;
898 else
899 phb->model = PNV_PHB_MODEL_UNKNOWN;
900
901 /* We parse "ranges" now since we need to deduce the register base
902 * from the IO base
903 */
904 pci_process_bridge_OF_ranges(phb->hose, np, primary);
905 primary = 0;
906
907 /* Magic formula from Milton */
908 phb->regs = of_iomap(np, 0);
909 if (phb->regs == NULL)
910 pr_err(" Failed to map registers !\n");
911
912
913 /* XXX This is hack-a-thon. This needs to be changed so that:
914 * - we obtain stuff like PE# etc... from device-tree
915 * - we properly re-allocate M32 ourselves
916 * (the OFW one isn't very good)
917 */
918
919 /* Initialize more IODA stuff */
920 phb->ioda.total_pe = 128;
921
922 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
923 /* OFW Has already off top 64k of M32 space (MSI space) */
924 phb->ioda.m32_size += 0x10000;
925
926 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
927 phb->ioda.m32_pci_base = hose->mem_resources[0].start -
928 hose->pci_mem_offset;
929 phb->ioda.io_size = hose->pci_io_size;
930 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
931 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
932
933 /* Allocate aux data & arrays */
934 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
935 m32map_off = size;
936 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
937 iomap_off = size;
938 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
939 pemap_off = size;
940 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
941 aux = alloc_bootmem(size);
942 memset(aux, 0, size);
943 phb->ioda.pe_alloc = aux;
944 phb->ioda.m32_segmap = aux + m32map_off;
945 phb->ioda.io_segmap = aux + iomap_off;
946 phb->ioda.pe_array = aux + pemap_off;
947 set_bit(0, phb->ioda.pe_alloc);
948
949 INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
950 INIT_LIST_HEAD(&phb->ioda.pe_list);
951
952 /* Calculate how many 32-bit TCE segments we have */
953 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
954
955 /* Clear unusable m64 */
956 hose->mem_resources[1].flags = 0;
957 hose->mem_resources[1].start = 0;
958 hose->mem_resources[1].end = 0;
959 hose->mem_resources[2].flags = 0;
960 hose->mem_resources[2].start = 0;
961 hose->mem_resources[2].end = 0;
962
963 #if 0
964 rc = opal_pci_set_phb_mem_window(opal->phb_id,
965 window_type,
966 window_num,
967 starting_real_address,
968 starting_pci_address,
969 segment_size);
970 #endif
971
972 pr_info(" %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n",
973 phb->ioda.total_pe,
974 phb->ioda.m32_size, phb->ioda.m32_segsize,
975 phb->ioda.io_size, phb->ioda.io_segsize);
976
977 if (phb->regs) {
978 pr_devel(" BUID = 0x%016llx\n", in_be64(phb->regs + 0x100));
979 pr_devel(" PHB2_CR = 0x%016llx\n", in_be64(phb->regs + 0x160));
980 pr_devel(" IO_BAR = 0x%016llx\n", in_be64(phb->regs + 0x170));
981 pr_devel(" IO_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x178));
982 pr_devel(" IO_SAR = 0x%016llx\n", in_be64(phb->regs + 0x180));
983 pr_devel(" M32_BAR = 0x%016llx\n", in_be64(phb->regs + 0x190));
984 pr_devel(" M32_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x198));
985 pr_devel(" M32_SAR = 0x%016llx\n", in_be64(phb->regs + 0x1a0));
986 }
987 phb->hose->ops = &pnv_pci_ops;
988
989 /* Setup RID -> PE mapping function */
990 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
991
992 /* Setup TCEs */
993 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
994
995 /* Setup MSI support */
996 pnv_pci_init_ioda_msis(phb);
997
998 /*
999 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
1000 * to let the PCI core do resource assignment. It's supposed
1001 * that the PCI core will do correct I/O and MMIO alignment
1002 * for the P2P bridge bars so that each PCI bus (excluding
1003 * the child P2P bridges) can form individual PE.
1004 */
1005 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
1006 ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
1007 ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
1008 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1009
1010 /* Reset IODA tables to a clean state */
1011 rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1012 if (rc)
1013 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
1014 opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
1015 }
1016
1017 void __init pnv_pci_init_ioda_hub(struct device_node *np)
1018 {
1019 struct device_node *phbn;
1020 const u64 *prop64;
1021 u64 hub_id;
1022
1023 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
1024
1025 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
1026 if (!prop64) {
1027 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
1028 return;
1029 }
1030 hub_id = be64_to_cpup(prop64);
1031 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
1032
1033 /* Count child PHBs */
1034 for_each_child_of_node(np, phbn) {
1035 /* Look for IODA1 PHBs */
1036 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
1037 pnv_pci_init_ioda1_phb(phbn);
1038 }
1039 }
Linux with added FPC-III support