2 * arch/powerpc/sysdev/qe_lib/qe_ic.c
4 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Li Yang <leoli@freescale.com>
7 * Based on code from Shlomi Gridish <gridish@freescale.com>
9 * QUICC ENGINE Interrupt Controller
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/slab.h>
22 #include <linux/stddef.h>
23 #include <linux/sched.h>
24 #include <linux/signal.h>
25 #include <linux/device.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
31 #include <asm/qe_ic.h>
35 static DEFINE_RAW_SPINLOCK(qe_ic_lock
);
37 static struct qe_ic_info qe_ic_info
[] = {
40 .mask_reg
= QEIC_CIMR
,
42 .pri_reg
= QEIC_CIPWCC
,
46 .mask_reg
= QEIC_CIMR
,
48 .pri_reg
= QEIC_CIPWCC
,
52 .mask_reg
= QEIC_CIMR
,
54 .pri_reg
= QEIC_CIPWCC
,
58 .mask_reg
= QEIC_CIMR
,
60 .pri_reg
= QEIC_CIPZCC
,
64 .mask_reg
= QEIC_CIMR
,
66 .pri_reg
= QEIC_CIPZCC
,
70 .mask_reg
= QEIC_CIMR
,
72 .pri_reg
= QEIC_CIPZCC
,
76 .mask_reg
= QEIC_CIMR
,
78 .pri_reg
= QEIC_CIPZCC
,
82 .mask_reg
= QEIC_CIMR
,
84 .pri_reg
= QEIC_CIPZCC
,
88 .mask_reg
= QEIC_CIMR
,
90 .pri_reg
= QEIC_CIPZCC
,
94 .mask_reg
= QEIC_CRIMR
,
96 .pri_reg
= QEIC_CIPRTA
,
100 .mask_reg
= QEIC_CRIMR
,
102 .pri_reg
= QEIC_CIPRTB
,
106 .mask_reg
= QEIC_CRIMR
,
108 .pri_reg
= QEIC_CIPRTB
,
112 .mask_reg
= QEIC_CRIMR
,
114 .pri_reg
= QEIC_CIPRTB
,
118 .mask_reg
= QEIC_CRIMR
,
120 .pri_reg
= QEIC_CIPRTB
,
124 .mask_reg
= QEIC_CIMR
,
126 .pri_reg
= QEIC_CIPXCC
,
130 .mask_reg
= QEIC_CIMR
,
132 .pri_reg
= QEIC_CIPXCC
,
136 .mask_reg
= QEIC_CIMR
,
138 .pri_reg
= QEIC_CIPXCC
,
142 .mask_reg
= QEIC_CIMR
,
144 .pri_reg
= QEIC_CIPXCC
,
148 .mask_reg
= QEIC_CIMR
,
150 .pri_reg
= QEIC_CIPXCC
,
154 .mask_reg
= QEIC_CIMR
,
156 .pri_reg
= QEIC_CIPYCC
,
160 .mask_reg
= QEIC_CIMR
,
162 .pri_reg
= QEIC_CIPYCC
,
166 .mask_reg
= QEIC_CIMR
,
168 .pri_reg
= QEIC_CIPYCC
,
172 .mask_reg
= QEIC_CIMR
,
174 .pri_reg
= QEIC_CIPYCC
,
178 static inline u32
qe_ic_read(volatile __be32 __iomem
* base
, unsigned int reg
)
180 return in_be32(base
+ (reg
>> 2));
183 static inline void qe_ic_write(volatile __be32 __iomem
* base
, unsigned int reg
,
186 out_be32(base
+ (reg
>> 2), value
);
189 static inline struct qe_ic
*qe_ic_from_irq(unsigned int virq
)
191 return irq_get_chip_data(virq
);
194 static inline struct qe_ic
*qe_ic_from_irq_data(struct irq_data
*d
)
196 return irq_data_get_irq_chip_data(d
);
199 static void qe_ic_unmask_irq(struct irq_data
*d
)
201 struct qe_ic
*qe_ic
= qe_ic_from_irq_data(d
);
202 unsigned int src
= irqd_to_hwirq(d
);
206 raw_spin_lock_irqsave(&qe_ic_lock
, flags
);
208 temp
= qe_ic_read(qe_ic
->regs
, qe_ic_info
[src
].mask_reg
);
209 qe_ic_write(qe_ic
->regs
, qe_ic_info
[src
].mask_reg
,
210 temp
| qe_ic_info
[src
].mask
);
212 raw_spin_unlock_irqrestore(&qe_ic_lock
, flags
);
215 static void qe_ic_mask_irq(struct irq_data
*d
)
217 struct qe_ic
*qe_ic
= qe_ic_from_irq_data(d
);
218 unsigned int src
= irqd_to_hwirq(d
);
222 raw_spin_lock_irqsave(&qe_ic_lock
, flags
);
224 temp
= qe_ic_read(qe_ic
->regs
, qe_ic_info
[src
].mask_reg
);
225 qe_ic_write(qe_ic
->regs
, qe_ic_info
[src
].mask_reg
,
226 temp
& ~qe_ic_info
[src
].mask
);
228 /* Flush the above write before enabling interrupts; otherwise,
229 * spurious interrupts will sometimes happen. To be 100% sure
230 * that the write has reached the device before interrupts are
231 * enabled, the mask register would have to be read back; however,
232 * this is not required for correctness, only to avoid wasting
233 * time on a large number of spurious interrupts. In testing,
234 * a sync reduced the observed spurious interrupts to zero.
238 raw_spin_unlock_irqrestore(&qe_ic_lock
, flags
);
241 static struct irq_chip qe_ic_irq_chip
= {
243 .irq_unmask
= qe_ic_unmask_irq
,
244 .irq_mask
= qe_ic_mask_irq
,
245 .irq_mask_ack
= qe_ic_mask_irq
,
248 static int qe_ic_host_match(struct irq_domain
*h
, struct device_node
*node
)
250 /* Exact match, unless qe_ic node is NULL */
251 return h
->of_node
== NULL
|| h
->of_node
== node
;
254 static int qe_ic_host_map(struct irq_domain
*h
, unsigned int virq
,
257 struct qe_ic
*qe_ic
= h
->host_data
;
258 struct irq_chip
*chip
;
260 if (qe_ic_info
[hw
].mask
== 0) {
261 printk(KERN_ERR
"Can't map reserved IRQ\n");
265 chip
= &qe_ic
->hc_irq
;
267 irq_set_chip_data(virq
, qe_ic
);
268 irq_set_status_flags(virq
, IRQ_LEVEL
);
270 irq_set_chip_and_handler(virq
, chip
, handle_level_irq
);
275 static struct irq_domain_ops qe_ic_host_ops
= {
276 .match
= qe_ic_host_match
,
277 .map
= qe_ic_host_map
,
278 .xlate
= irq_domain_xlate_onetwocell
,
281 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
282 unsigned int qe_ic_get_low_irq(struct qe_ic
*qe_ic
)
286 BUG_ON(qe_ic
== NULL
);
288 /* get the interrupt source vector. */
289 irq
= qe_ic_read(qe_ic
->regs
, QEIC_CIVEC
) >> 26;
294 return irq_linear_revmap(qe_ic
->irqhost
, irq
);
297 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
298 unsigned int qe_ic_get_high_irq(struct qe_ic
*qe_ic
)
302 BUG_ON(qe_ic
== NULL
);
304 /* get the interrupt source vector. */
305 irq
= qe_ic_read(qe_ic
->regs
, QEIC_CHIVEC
) >> 26;
310 return irq_linear_revmap(qe_ic
->irqhost
, irq
);
313 void __init
qe_ic_init(struct device_node
*node
, unsigned int flags
,
314 void (*low_handler
)(unsigned int irq
, struct irq_desc
*desc
),
315 void (*high_handler
)(unsigned int irq
, struct irq_desc
*desc
))
319 u32 temp
= 0, ret
, high_active
= 0;
321 ret
= of_address_to_resource(node
, 0, &res
);
325 qe_ic
= kzalloc(sizeof(*qe_ic
), GFP_KERNEL
);
329 qe_ic
->irqhost
= irq_domain_add_linear(node
, NR_QE_IC_INTS
,
330 &qe_ic_host_ops
, qe_ic
);
331 if (qe_ic
->irqhost
== NULL
) {
336 qe_ic
->regs
= ioremap(res
.start
, resource_size(&res
));
338 qe_ic
->hc_irq
= qe_ic_irq_chip
;
340 qe_ic
->virq_high
= irq_of_parse_and_map(node
, 0);
341 qe_ic
->virq_low
= irq_of_parse_and_map(node
, 1);
343 if (qe_ic
->virq_low
== NO_IRQ
) {
344 printk(KERN_ERR
"Failed to map QE_IC low IRQ\n");
349 /* default priority scheme is grouped. If spread mode is */
350 /* required, configure cicr accordingly. */
351 if (flags
& QE_IC_SPREADMODE_GRP_W
)
353 if (flags
& QE_IC_SPREADMODE_GRP_X
)
355 if (flags
& QE_IC_SPREADMODE_GRP_Y
)
357 if (flags
& QE_IC_SPREADMODE_GRP_Z
)
359 if (flags
& QE_IC_SPREADMODE_GRP_RISCA
)
361 if (flags
& QE_IC_SPREADMODE_GRP_RISCB
)
364 /* choose destination signal for highest priority interrupt */
365 if (flags
& QE_IC_HIGH_SIGNAL
) {
366 temp
|= (SIGNAL_HIGH
<< CICR_HPIT_SHIFT
);
370 qe_ic_write(qe_ic
->regs
, QEIC_CICR
, temp
);
372 irq_set_handler_data(qe_ic
->virq_low
, qe_ic
);
373 irq_set_chained_handler(qe_ic
->virq_low
, low_handler
);
375 if (qe_ic
->virq_high
!= NO_IRQ
&&
376 qe_ic
->virq_high
!= qe_ic
->virq_low
) {
377 irq_set_handler_data(qe_ic
->virq_high
, qe_ic
);
378 irq_set_chained_handler(qe_ic
->virq_high
, high_handler
);
382 void qe_ic_set_highest_priority(unsigned int virq
, int high
)
384 struct qe_ic
*qe_ic
= qe_ic_from_irq(virq
);
385 unsigned int src
= virq_to_hw(virq
);
388 temp
= qe_ic_read(qe_ic
->regs
, QEIC_CICR
);
390 temp
&= ~CICR_HP_MASK
;
391 temp
|= src
<< CICR_HP_SHIFT
;
393 temp
&= ~CICR_HPIT_MASK
;
394 temp
|= (high
? SIGNAL_HIGH
: SIGNAL_LOW
) << CICR_HPIT_SHIFT
;
396 qe_ic_write(qe_ic
->regs
, QEIC_CICR
, temp
);
399 /* Set Priority level within its group, from 1 to 8 */
400 int qe_ic_set_priority(unsigned int virq
, unsigned int priority
)
402 struct qe_ic
*qe_ic
= qe_ic_from_irq(virq
);
403 unsigned int src
= virq_to_hw(virq
);
406 if (priority
> 8 || priority
== 0)
410 if (qe_ic_info
[src
].pri_reg
== 0)
413 temp
= qe_ic_read(qe_ic
->regs
, qe_ic_info
[src
].pri_reg
);
416 temp
&= ~(0x7 << (32 - priority
* 3));
417 temp
|= qe_ic_info
[src
].pri_code
<< (32 - priority
* 3);
419 temp
&= ~(0x7 << (24 - priority
* 3));
420 temp
|= qe_ic_info
[src
].pri_code
<< (24 - priority
* 3);
423 qe_ic_write(qe_ic
->regs
, qe_ic_info
[src
].pri_reg
, temp
);
428 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */
429 int qe_ic_set_high_priority(unsigned int virq
, unsigned int priority
, int high
)
431 struct qe_ic
*qe_ic
= qe_ic_from_irq(virq
);
432 unsigned int src
= virq_to_hw(virq
);
433 u32 temp
, control_reg
= QEIC_CICNR
, shift
= 0;
435 if (priority
> 2 || priority
== 0)
438 switch (qe_ic_info
[src
].pri_reg
) {
440 shift
= CICNR_ZCC1T_SHIFT
;
443 shift
= CICNR_WCC1T_SHIFT
;
446 shift
= CICNR_YCC1T_SHIFT
;
449 shift
= CICNR_XCC1T_SHIFT
;
452 shift
= CRICR_RTA1T_SHIFT
;
453 control_reg
= QEIC_CRICR
;
456 shift
= CRICR_RTB1T_SHIFT
;
457 control_reg
= QEIC_CRICR
;
463 shift
+= (2 - priority
) * 2;
464 temp
= qe_ic_read(qe_ic
->regs
, control_reg
);
465 temp
&= ~(SIGNAL_MASK
<< shift
);
466 temp
|= (high
? SIGNAL_HIGH
: SIGNAL_LOW
) << shift
;
467 qe_ic_write(qe_ic
->regs
, control_reg
, temp
);
472 static struct bus_type qe_ic_subsys
= {
477 static struct device device_qe_ic
= {
479 .bus
= &qe_ic_subsys
,
482 static int __init
init_qe_ic_sysfs(void)
486 printk(KERN_DEBUG
"Registering qe_ic with sysfs...\n");
488 rc
= subsys_system_register(&qe_ic_subsys
, NULL
);
490 printk(KERN_ERR
"Failed registering qe_ic sys class\n");
493 rc
= device_register(&device_qe_ic
);
495 printk(KERN_ERR
"Failed registering qe_ic sys device\n");
501 subsys_initcall(init_qe_ic_sysfs
);