x86, efi: Set runtime_version to the EFI spec revision
[linux/fpc-iii.git] / arch / powerpc / sysdev / qe_lib / qe_ic.h
blobefef7ab9b753eba14ba858c50583c6e3a844415b
1 /*
2 * arch/powerpc/sysdev/qe_lib/qe_ic.h
4 * QUICC ENGINE Interrupt Controller Header
6 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
8 * Author: Li Yang <leoli@freescale.com>
9 * Based on code from Shlomi Gridish <gridish@freescale.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 #ifndef _POWERPC_SYSDEV_QE_IC_H
17 #define _POWERPC_SYSDEV_QE_IC_H
19 #include <asm/qe_ic.h>
21 #define NR_QE_IC_INTS 64
23 /* QE IC registers offset */
24 #define QEIC_CICR 0x00
25 #define QEIC_CIVEC 0x04
26 #define QEIC_CRIPNR 0x08
27 #define QEIC_CIPNR 0x0c
28 #define QEIC_CIPXCC 0x10
29 #define QEIC_CIPYCC 0x14
30 #define QEIC_CIPWCC 0x18
31 #define QEIC_CIPZCC 0x1c
32 #define QEIC_CIMR 0x20
33 #define QEIC_CRIMR 0x24
34 #define QEIC_CICNR 0x28
35 #define QEIC_CIPRTA 0x30
36 #define QEIC_CIPRTB 0x34
37 #define QEIC_CRICR 0x3c
38 #define QEIC_CHIVEC 0x60
40 /* Interrupt priority registers */
41 #define CIPCC_SHIFT_PRI0 29
42 #define CIPCC_SHIFT_PRI1 26
43 #define CIPCC_SHIFT_PRI2 23
44 #define CIPCC_SHIFT_PRI3 20
45 #define CIPCC_SHIFT_PRI4 13
46 #define CIPCC_SHIFT_PRI5 10
47 #define CIPCC_SHIFT_PRI6 7
48 #define CIPCC_SHIFT_PRI7 4
50 /* CICR priority modes */
51 #define CICR_GWCC 0x00040000
52 #define CICR_GXCC 0x00020000
53 #define CICR_GYCC 0x00010000
54 #define CICR_GZCC 0x00080000
55 #define CICR_GRTA 0x00200000
56 #define CICR_GRTB 0x00400000
57 #define CICR_HPIT_SHIFT 8
58 #define CICR_HPIT_MASK 0x00000300
59 #define CICR_HP_SHIFT 24
60 #define CICR_HP_MASK 0x3f000000
62 /* CICNR */
63 #define CICNR_WCC1T_SHIFT 20
64 #define CICNR_ZCC1T_SHIFT 28
65 #define CICNR_YCC1T_SHIFT 12
66 #define CICNR_XCC1T_SHIFT 4
68 /* CRICR */
69 #define CRICR_RTA1T_SHIFT 20
70 #define CRICR_RTB1T_SHIFT 28
72 /* Signal indicator */
73 #define SIGNAL_MASK 3
74 #define SIGNAL_HIGH 2
75 #define SIGNAL_LOW 0
77 struct qe_ic {
78 /* Control registers offset */
79 volatile u32 __iomem *regs;
81 /* The remapper for this QEIC */
82 struct irq_domain *irqhost;
84 /* The "linux" controller struct */
85 struct irq_chip hc_irq;
87 /* VIRQ numbers of QE high/low irqs */
88 unsigned int virq_high;
89 unsigned int virq_low;
93 * QE interrupt controller internal structure
95 struct qe_ic_info {
96 u32 mask; /* location of this source at the QIMR register. */
97 u32 mask_reg; /* Mask register offset */
98 u8 pri_code; /* for grouped interrupts sources - the interrupt
99 code as appears at the group priority register */
100 u32 pri_reg; /* Group priority register offset */
103 #endif /* _POWERPC_SYSDEV_QE_IC_H */