2 * arch/powerpc/sysdev/qe_lib/ucc.c
4 * QE UCC API Set - UCC specific routines implementations.
6 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/stddef.h>
20 #include <linux/spinlock.h>
21 #include <linux/export.h>
25 #include <asm/immap_qe.h>
29 int ucc_set_qe_mux_mii_mng(unsigned int ucc_num
)
33 if (ucc_num
> UCC_MAX_NUM
- 1)
36 spin_lock_irqsave(&cmxgcr_lock
, flags
);
37 clrsetbits_be32(&qe_immr
->qmx
.cmxgcr
, QE_CMXGCR_MII_ENET_MNG
,
38 ucc_num
<< QE_CMXGCR_MII_ENET_MNG_SHIFT
);
39 spin_unlock_irqrestore(&cmxgcr_lock
, flags
);
43 EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng
);
45 /* Configure the UCC to either Slow or Fast.
47 * A given UCC can be figured to support either "slow" devices (e.g. UART)
48 * or "fast" devices (e.g. Ethernet).
50 * 'ucc_num' is the UCC number, from 0 - 7.
52 * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
53 * must always be set to 1.
55 int ucc_set_type(unsigned int ucc_num
, enum ucc_speed_type speed
)
59 /* The GUEMR register is at the same location for both slow and fast
60 devices, so we just use uccX.slow.guemr. */
62 case 0: guemr
= &qe_immr
->ucc1
.slow
.guemr
;
64 case 1: guemr
= &qe_immr
->ucc2
.slow
.guemr
;
66 case 2: guemr
= &qe_immr
->ucc3
.slow
.guemr
;
68 case 3: guemr
= &qe_immr
->ucc4
.slow
.guemr
;
70 case 4: guemr
= &qe_immr
->ucc5
.slow
.guemr
;
72 case 5: guemr
= &qe_immr
->ucc6
.slow
.guemr
;
74 case 6: guemr
= &qe_immr
->ucc7
.slow
.guemr
;
76 case 7: guemr
= &qe_immr
->ucc8
.slow
.guemr
;
82 clrsetbits_8(guemr
, UCC_GUEMR_MODE_MASK
,
83 UCC_GUEMR_SET_RESERVED3
| speed
);
88 static void get_cmxucr_reg(unsigned int ucc_num
, __be32 __iomem
**cmxucr
,
89 unsigned int *reg_num
, unsigned int *shift
)
91 unsigned int cmx
= ((ucc_num
& 1) << 1) + (ucc_num
> 3);
94 *cmxucr
= &qe_immr
->qmx
.cmxucr
[cmx
];
95 *shift
= 16 - 8 * (ucc_num
& 2);
98 int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num
, int set
, u32 mask
)
100 __be32 __iomem
*cmxucr
;
101 unsigned int reg_num
;
104 /* check if the UCC number is in range. */
105 if (ucc_num
> UCC_MAX_NUM
- 1)
108 get_cmxucr_reg(ucc_num
, &cmxucr
, ®_num
, &shift
);
111 setbits32(cmxucr
, mask
<< shift
);
113 clrbits32(cmxucr
, mask
<< shift
);
118 int ucc_set_qe_mux_rxtx(unsigned int ucc_num
, enum qe_clock clock
,
121 __be32 __iomem
*cmxucr
;
122 unsigned int reg_num
;
126 /* check if the UCC number is in range. */
127 if (ucc_num
> UCC_MAX_NUM
- 1)
130 /* The communications direction must be RX or TX */
131 if (!((mode
== COMM_DIR_RX
) || (mode
== COMM_DIR_TX
)))
134 get_cmxucr_reg(ucc_num
, &cmxucr
, ®_num
, &shift
);
139 case QE_BRG1
: clock_bits
= 1; break;
140 case QE_BRG2
: clock_bits
= 2; break;
141 case QE_BRG7
: clock_bits
= 3; break;
142 case QE_BRG8
: clock_bits
= 4; break;
143 case QE_CLK9
: clock_bits
= 5; break;
144 case QE_CLK10
: clock_bits
= 6; break;
145 case QE_CLK11
: clock_bits
= 7; break;
146 case QE_CLK12
: clock_bits
= 8; break;
147 case QE_CLK15
: clock_bits
= 9; break;
148 case QE_CLK16
: clock_bits
= 10; break;
154 case QE_BRG5
: clock_bits
= 1; break;
155 case QE_BRG6
: clock_bits
= 2; break;
156 case QE_BRG7
: clock_bits
= 3; break;
157 case QE_BRG8
: clock_bits
= 4; break;
158 case QE_CLK13
: clock_bits
= 5; break;
159 case QE_CLK14
: clock_bits
= 6; break;
160 case QE_CLK19
: clock_bits
= 7; break;
161 case QE_CLK20
: clock_bits
= 8; break;
162 case QE_CLK15
: clock_bits
= 9; break;
163 case QE_CLK16
: clock_bits
= 10; break;
169 case QE_BRG9
: clock_bits
= 1; break;
170 case QE_BRG10
: clock_bits
= 2; break;
171 case QE_BRG15
: clock_bits
= 3; break;
172 case QE_BRG16
: clock_bits
= 4; break;
173 case QE_CLK3
: clock_bits
= 5; break;
174 case QE_CLK4
: clock_bits
= 6; break;
175 case QE_CLK17
: clock_bits
= 7; break;
176 case QE_CLK18
: clock_bits
= 8; break;
177 case QE_CLK7
: clock_bits
= 9; break;
178 case QE_CLK8
: clock_bits
= 10; break;
179 case QE_CLK16
: clock_bits
= 11; break;
185 case QE_BRG13
: clock_bits
= 1; break;
186 case QE_BRG14
: clock_bits
= 2; break;
187 case QE_BRG15
: clock_bits
= 3; break;
188 case QE_BRG16
: clock_bits
= 4; break;
189 case QE_CLK5
: clock_bits
= 5; break;
190 case QE_CLK6
: clock_bits
= 6; break;
191 case QE_CLK21
: clock_bits
= 7; break;
192 case QE_CLK22
: clock_bits
= 8; break;
193 case QE_CLK7
: clock_bits
= 9; break;
194 case QE_CLK8
: clock_bits
= 10; break;
195 case QE_CLK16
: clock_bits
= 11; break;
202 /* Check for invalid combination of clock and UCC number */
206 if (mode
== COMM_DIR_RX
)
209 clrsetbits_be32(cmxucr
, QE_CMXUCR_TX_CLK_SRC_MASK
<< shift
,
210 clock_bits
<< shift
);