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perf: Add active_entry list head to struct perf_event
[linux/fpc-iii.git] / drivers / clocksource / exynos_mct.c
blob62b0de6a18370fade34eca20205557bd5871cc3a
1 /* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpu.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/percpu.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/clocksource.h>
27
28 #include <asm/mach/time.h>
29
30 #define EXYNOS4_MCTREG(x) (x)
31 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
32 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
33 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
34 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
35 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
36 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
37 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
38 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
39 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
40 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
41 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
42 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
43 #define EXYNOS4_MCT_L_MASK (0xffffff00)
44
45 #define MCT_L_TCNTB_OFFSET (0x00)
46 #define MCT_L_ICNTB_OFFSET (0x08)
47 #define MCT_L_TCON_OFFSET (0x20)
48 #define MCT_L_INT_CSTAT_OFFSET (0x30)
49 #define MCT_L_INT_ENB_OFFSET (0x34)
50 #define MCT_L_WSTAT_OFFSET (0x40)
51 #define MCT_G_TCON_START (1 << 8)
52 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
53 #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
54 #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
55 #define MCT_L_TCON_INT_START (1 << 1)
56 #define MCT_L_TCON_TIMER_START (1 << 0)
57
58 #define TICK_BASE_CNT 1
59
60 enum {
61 MCT_INT_SPI,
62 MCT_INT_PPI
63 };
64
65 enum {
66 MCT_G0_IRQ,
67 MCT_G1_IRQ,
68 MCT_G2_IRQ,
69 MCT_G3_IRQ,
70 MCT_L0_IRQ,
71 MCT_L1_IRQ,
72 MCT_L2_IRQ,
73 MCT_L3_IRQ,
74 MCT_NR_IRQS,
75 };
76
77 static void __iomem *reg_base;
78 static unsigned long clk_rate;
79 static unsigned int mct_int_type;
80 static int mct_irqs[MCT_NR_IRQS];
81
82 struct mct_clock_event_device {
83 struct clock_event_device evt;
84 unsigned long base;
85 char name[10];
86 };
87
88 static void exynos4_mct_write(unsigned int value, unsigned long offset)
89 {
90 unsigned long stat_addr;
91 u32 mask;
92 u32 i;
93
94 __raw_writel(value, reg_base + offset);
95
96 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
97 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
98 switch (offset & EXYNOS4_MCT_L_MASK) {
99 case MCT_L_TCON_OFFSET:
100 mask = 1 << 3; /* L_TCON write status */
101 break;
102 case MCT_L_ICNTB_OFFSET:
103 mask = 1 << 1; /* L_ICNTB write status */
104 break;
105 case MCT_L_TCNTB_OFFSET:
106 mask = 1 << 0; /* L_TCNTB write status */
107 break;
108 default:
109 return;
110 }
111 } else {
112 switch (offset) {
113 case EXYNOS4_MCT_G_TCON:
114 stat_addr = EXYNOS4_MCT_G_WSTAT;
115 mask = 1 << 16; /* G_TCON write status */
116 break;
117 case EXYNOS4_MCT_G_COMP0_L:
118 stat_addr = EXYNOS4_MCT_G_WSTAT;
119 mask = 1 << 0; /* G_COMP0_L write status */
120 break;
121 case EXYNOS4_MCT_G_COMP0_U:
122 stat_addr = EXYNOS4_MCT_G_WSTAT;
123 mask = 1 << 1; /* G_COMP0_U write status */
124 break;
125 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
126 stat_addr = EXYNOS4_MCT_G_WSTAT;
127 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
128 break;
129 case EXYNOS4_MCT_G_CNT_L:
130 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
131 mask = 1 << 0; /* G_CNT_L write status */
132 break;
133 case EXYNOS4_MCT_G_CNT_U:
134 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
135 mask = 1 << 1; /* G_CNT_U write status */
136 break;
137 default:
138 return;
139 }
140 }
141
142 /* Wait maximum 1 ms until written values are applied */
143 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
144 if (__raw_readl(reg_base + stat_addr) & mask) {
145 __raw_writel(mask, reg_base + stat_addr);
146 return;
147 }
148
149 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
150 }
151
152 /* Clocksource handling */
153 static void exynos4_mct_frc_start(u32 hi, u32 lo)
154 {
155 u32 reg;
156
157 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
158 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
159
160 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
161 reg |= MCT_G_TCON_START;
162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
163 }
164
165 static cycle_t exynos4_frc_read(struct clocksource *cs)
166 {
167 unsigned int lo, hi;
168 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
169
170 do {
171 hi = hi2;
172 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
173 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
174 } while (hi != hi2);
175
176 return ((cycle_t)hi << 32) | lo;
177 }
178
179 static void exynos4_frc_resume(struct clocksource *cs)
180 {
181 exynos4_mct_frc_start(0, 0);
182 }
183
184 struct clocksource mct_frc = {
185 .name = "mct-frc",
186 .rating = 400,
187 .read = exynos4_frc_read,
188 .mask = CLOCKSOURCE_MASK(64),
189 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
190 .resume = exynos4_frc_resume,
191 };
192
193 static void __init exynos4_clocksource_init(void)
194 {
195 exynos4_mct_frc_start(0, 0);
196
197 if (clocksource_register_hz(&mct_frc, clk_rate))
198 panic("%s: can't register clocksource\n", mct_frc.name);
199 }
200
201 static void exynos4_mct_comp0_stop(void)
202 {
203 unsigned int tcon;
204
205 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
206 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
207
208 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
209 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
210 }
211
212 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
213 unsigned long cycles)
214 {
215 unsigned int tcon;
216 cycle_t comp_cycle;
217
218 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
219
220 if (mode == CLOCK_EVT_MODE_PERIODIC) {
221 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
222 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
223 }
224
225 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
226 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
227 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
228
229 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
230
231 tcon |= MCT_G_TCON_COMP0_ENABLE;
232 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
233 }
234
235 static int exynos4_comp_set_next_event(unsigned long cycles,
236 struct clock_event_device *evt)
237 {
238 exynos4_mct_comp0_start(evt->mode, cycles);
239
240 return 0;
241 }
242
243 static void exynos4_comp_set_mode(enum clock_event_mode mode,
244 struct clock_event_device *evt)
245 {
246 unsigned long cycles_per_jiffy;
247 exynos4_mct_comp0_stop();
248
249 switch (mode) {
250 case CLOCK_EVT_MODE_PERIODIC:
251 cycles_per_jiffy =
252 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
253 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
254 break;
255
256 case CLOCK_EVT_MODE_ONESHOT:
257 case CLOCK_EVT_MODE_UNUSED:
258 case CLOCK_EVT_MODE_SHUTDOWN:
259 case CLOCK_EVT_MODE_RESUME:
260 break;
261 }
262 }
263
264 static struct clock_event_device mct_comp_device = {
265 .name = "mct-comp",
266 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
267 .rating = 250,
268 .set_next_event = exynos4_comp_set_next_event,
269 .set_mode = exynos4_comp_set_mode,
270 };
271
272 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
273 {
274 struct clock_event_device *evt = dev_id;
275
276 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
277
278 evt->event_handler(evt);
279
280 return IRQ_HANDLED;
281 }
282
283 static struct irqaction mct_comp_event_irq = {
284 .name = "mct_comp_irq",
285 .flags = IRQF_TIMER | IRQF_IRQPOLL,
286 .handler = exynos4_mct_comp_isr,
287 .dev_id = &mct_comp_device,
288 };
289
290 static void exynos4_clockevent_init(void)
291 {
292 mct_comp_device.cpumask = cpumask_of(0);
293 clockevents_config_and_register(&mct_comp_device, clk_rate,
294 0xf, 0xffffffff);
295 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
296 }
297
298 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
299
300 /* Clock event handling */
301 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
302 {
303 unsigned long tmp;
304 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
305 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
306
307 tmp = __raw_readl(reg_base + offset);
308 if (tmp & mask) {
309 tmp &= ~mask;
310 exynos4_mct_write(tmp, offset);
311 }
312 }
313
314 static void exynos4_mct_tick_start(unsigned long cycles,
315 struct mct_clock_event_device *mevt)
316 {
317 unsigned long tmp;
318
319 exynos4_mct_tick_stop(mevt);
320
321 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
322
323 /* update interrupt count buffer */
324 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
325
326 /* enable MCT tick interrupt */
327 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
328
329 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
330 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
331 MCT_L_TCON_INTERVAL_MODE;
332 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
333 }
334
335 static int exynos4_tick_set_next_event(unsigned long cycles,
336 struct clock_event_device *evt)
337 {
338 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
339
340 exynos4_mct_tick_start(cycles, mevt);
341
342 return 0;
343 }
344
345 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
346 struct clock_event_device *evt)
347 {
348 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
349 unsigned long cycles_per_jiffy;
350
351 exynos4_mct_tick_stop(mevt);
352
353 switch (mode) {
354 case CLOCK_EVT_MODE_PERIODIC:
355 cycles_per_jiffy =
356 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
357 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
358 break;
359
360 case CLOCK_EVT_MODE_ONESHOT:
361 case CLOCK_EVT_MODE_UNUSED:
362 case CLOCK_EVT_MODE_SHUTDOWN:
363 case CLOCK_EVT_MODE_RESUME:
364 break;
365 }
366 }
367
368 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
369 {
370 struct clock_event_device *evt = &mevt->evt;
371
372 /*
373 * This is for supporting oneshot mode.
374 * Mct would generate interrupt periodically
375 * without explicit stopping.
376 */
377 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
378 exynos4_mct_tick_stop(mevt);
379
380 /* Clear the MCT tick interrupt */
381 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
382 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
383 return 1;
384 } else {
385 return 0;
386 }
387 }
388
389 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
390 {
391 struct mct_clock_event_device *mevt = dev_id;
392 struct clock_event_device *evt = &mevt->evt;
393
394 exynos4_mct_tick_clear(mevt);
395
396 evt->event_handler(evt);
397
398 return IRQ_HANDLED;
399 }
400
401 static int exynos4_local_timer_setup(struct clock_event_device *evt)
402 {
403 struct mct_clock_event_device *mevt;
404 unsigned int cpu = smp_processor_id();
405
406 mevt = container_of(evt, struct mct_clock_event_device, evt);
407
408 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
409 sprintf(mevt->name, "mct_tick%d", cpu);
410
411 evt->name = mevt->name;
412 evt->cpumask = cpumask_of(cpu);
413 evt->set_next_event = exynos4_tick_set_next_event;
414 evt->set_mode = exynos4_tick_set_mode;
415 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
416 evt->rating = 450;
417 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
418 0xf, 0x7fffffff);
419
420 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
421
422 if (mct_int_type == MCT_INT_SPI) {
423 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
424 if (request_irq(evt->irq, exynos4_mct_tick_isr,
425 IRQF_TIMER | IRQF_NOBALANCING,
426 evt->name, mevt)) {
427 pr_err("exynos-mct: cannot register IRQ %d\n",
428 evt->irq);
429 return -EIO;
430 }
431 } else {
432 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
433 }
434
435 return 0;
436 }
437
438 static void exynos4_local_timer_stop(struct clock_event_device *evt)
439 {
440 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
441 if (mct_int_type == MCT_INT_SPI)
442 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
443 else
444 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
445 }
446
447 static int exynos4_mct_cpu_notify(struct notifier_block *self,
448 unsigned long action, void *hcpu)
449 {
450 struct mct_clock_event_device *mevt;
451 unsigned int cpu;
452
453 /*
454 * Grab cpu pointer in each case to avoid spurious
455 * preemptible warnings
456 */
457 switch (action & ~CPU_TASKS_FROZEN) {
458 case CPU_STARTING:
459 mevt = this_cpu_ptr(&percpu_mct_tick);
460 exynos4_local_timer_setup(&mevt->evt);
461 break;
462 case CPU_ONLINE:
463 cpu = (unsigned long)hcpu;
464 if (mct_int_type == MCT_INT_SPI)
465 irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
466 cpumask_of(cpu));
467 break;
468 case CPU_DYING:
469 mevt = this_cpu_ptr(&percpu_mct_tick);
470 exynos4_local_timer_stop(&mevt->evt);
471 break;
472 }
473
474 return NOTIFY_OK;
475 }
476
477 static struct notifier_block exynos4_mct_cpu_nb = {
478 .notifier_call = exynos4_mct_cpu_notify,
479 };
480
481 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
482 {
483 int err;
484 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
485 struct clk *mct_clk, *tick_clk;
486
487 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
488 clk_get(NULL, "fin_pll");
489 if (IS_ERR(tick_clk))
490 panic("%s: unable to determine tick clock rate\n", __func__);
491 clk_rate = clk_get_rate(tick_clk);
492
493 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
494 if (IS_ERR(mct_clk))
495 panic("%s: unable to retrieve mct clock instance\n", __func__);
496 clk_prepare_enable(mct_clk);
497
498 reg_base = base;
499 if (!reg_base)
500 panic("%s: unable to ioremap mct address space\n", __func__);
501
502 if (mct_int_type == MCT_INT_PPI) {
503
504 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
505 exynos4_mct_tick_isr, "MCT",
506 &percpu_mct_tick);
507 WARN(err, "MCT: can't request IRQ %d (%d)\n",
508 mct_irqs[MCT_L0_IRQ], err);
509 } else {
510 irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
511 }
512
513 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
514 if (err)
515 goto out_irq;
516
517 /* Immediately configure the timer on the boot CPU */
518 exynos4_local_timer_setup(&mevt->evt);
519 return;
520
521 out_irq:
522 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
523 }
524
525 void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
526 {
527 mct_irqs[MCT_G0_IRQ] = irq_g0;
528 mct_irqs[MCT_L0_IRQ] = irq_l0;
529 mct_irqs[MCT_L1_IRQ] = irq_l1;
530 mct_int_type = MCT_INT_SPI;
531
532 exynos4_timer_resources(NULL, base);
533 exynos4_clocksource_init();
534 exynos4_clockevent_init();
535 }
536
537 static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
538 {
539 u32 nr_irqs, i;
540
541 mct_int_type = int_type;
542
543 /* This driver uses only one global timer interrupt */
544 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
545
546 /*
547 * Find out the number of local irqs specified. The local
548 * timer irqs are specified after the four global timer
549 * irqs are specified.
550 */
551 #ifdef CONFIG_OF
552 nr_irqs = of_irq_count(np);
553 #else
554 nr_irqs = 0;
555 #endif
556 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
557 mct_irqs[i] = irq_of_parse_and_map(np, i);
558
559 exynos4_timer_resources(np, of_iomap(np, 0));
560 exynos4_clocksource_init();
561 exynos4_clockevent_init();
562 }
563
564
565 static void __init mct_init_spi(struct device_node *np)
566 {
567 return mct_init_dt(np, MCT_INT_SPI);
568 }
569
570 static void __init mct_init_ppi(struct device_node *np)
571 {
572 return mct_init_dt(np, MCT_INT_PPI);
573 }
574 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
575 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Linux with added FPC-III support