drivers/gpio/gpio-rcar.c

   1 /*
   2  * Renesas R-Car GPIO Support
   3  *
   4  *  Copyright (C) 2013 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/ioport.h>
  22 #include <linux/irq.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/platform_data/gpio-rcar.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/slab.h>
  31
  32 struct gpio_rcar_priv {
  33         void __iomem *base;
  34         spinlock_t lock;
  35         struct gpio_rcar_config config;
  36         struct platform_device *pdev;
  37         struct gpio_chip gpio_chip;
  38         struct irq_chip irq_chip;
  39         struct irq_domain *irq_domain;
  40 };
  41
  42 #define IOINTSEL 0x00
  43 #define INOUTSEL 0x04
  44 #define OUTDT 0x08
  45 #define INDT 0x0c
  46 #define INTDT 0x10
  47 #define INTCLR 0x14
  48 #define INTMSK 0x18
  49 #define MSKCLR 0x1c
  50 #define POSNEG 0x20
  51 #define EDGLEVEL 0x24
  52 #define FILONOFF 0x28
  53 #define BOTHEDGE 0x4c
  54
  55 #define RCAR_MAX_GPIO_PER_BANK          32
  56
  57 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  58 {
  59         return ioread32(p->base + offs);
  60 }
  61
  62 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  63                                    u32 value)
  64 {
  65         iowrite32(value, p->base + offs);
  66 }
  67
  68 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  69                                  int bit, bool value)
  70 {
  71         u32 tmp = gpio_rcar_read(p, offs);
  72
  73         if (value)
  74                 tmp |= BIT(bit);
  75         else
  76                 tmp &= ~BIT(bit);
  77
  78         gpio_rcar_write(p, offs, tmp);
  79 }
  80
  81 static void gpio_rcar_irq_disable(struct irq_data *d)
  82 {
  83         struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  84
  85         gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  86 }
  87
  88 static void gpio_rcar_irq_enable(struct irq_data *d)
  89 {
  90         struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  91
  92         gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
  93 }
  94
  95 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
  96                                                   unsigned int hwirq,
  97                                                   bool active_high_rising_edge,
  98                                                   bool level_trigger,
  99                                                   bool both)
 100 {
 101         unsigned long flags;
 102
 103         /* follow steps in the GPIO documentation for
 104          * "Setting Edge-Sensitive Interrupt Input Mode" and
 105          * "Setting Level-Sensitive Interrupt Input Mode"
 106          */
 107
 108         spin_lock_irqsave(&p->lock, flags);
 109
 110         /* Configure postive or negative logic in POSNEG */
 111         gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
 112
 113         /* Configure edge or level trigger in EDGLEVEL */
 114         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 115
 116         /* Select one edge or both edges in BOTHEDGE */
 117         if (p->config.has_both_edge_trigger)
 118                 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 119
 120         /* Select "Interrupt Input Mode" in IOINTSEL */
 121         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 122
 123         /* Write INTCLR in case of edge trigger */
 124         if (!level_trigger)
 125                 gpio_rcar_write(p, INTCLR, BIT(hwirq));
 126
 127         spin_unlock_irqrestore(&p->lock, flags);
 128 }
 129
 130 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 131 {
 132         struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
 133         unsigned int hwirq = irqd_to_hwirq(d);
 134
 135         dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
 136
 137         switch (type & IRQ_TYPE_SENSE_MASK) {
 138         case IRQ_TYPE_LEVEL_HIGH:
 139                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
 140                                                       false);
 141                 break;
 142         case IRQ_TYPE_LEVEL_LOW:
 143                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
 144                                                       false);
 145                 break;
 146         case IRQ_TYPE_EDGE_RISING:
 147                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 148                                                       false);
 149                 break;
 150         case IRQ_TYPE_EDGE_FALLING:
 151                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
 152                                                       false);
 153                 break;
 154         case IRQ_TYPE_EDGE_BOTH:
 155                 if (!p->config.has_both_edge_trigger)
 156                         return -EINVAL;
 157                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 158                                                       true);
 159                 break;
 160         default:
 161                 return -EINVAL;
 162         }
 163         return 0;
 164 }
 165
 166 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
 167 {
 168         struct gpio_rcar_priv *p = dev_id;
 169         u32 pending;
 170         unsigned int offset, irqs_handled = 0;
 171
 172         while ((pending = gpio_rcar_read(p, INTDT))) {
 173                 offset = __ffs(pending);
 174                 gpio_rcar_write(p, INTCLR, BIT(offset));
 175                 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
 176                 irqs_handled++;
 177         }
 178
 179         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 180 }
 181
 182 static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
 183 {
 184         return container_of(chip, struct gpio_rcar_priv, gpio_chip);
 185 }
 186
 187 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 188                                                        unsigned int gpio,
 189                                                        bool output)
 190 {
 191         struct gpio_rcar_priv *p = gpio_to_priv(chip);
 192         unsigned long flags;
 193
 194         /* follow steps in the GPIO documentation for
 195          * "Setting General Output Mode" and
 196          * "Setting General Input Mode"
 197          */
 198
 199         spin_lock_irqsave(&p->lock, flags);
 200
 201         /* Configure postive logic in POSNEG */
 202         gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 203
 204         /* Select "General Input/Output Mode" in IOINTSEL */
 205         gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 206
 207         /* Select Input Mode or Output Mode in INOUTSEL */
 208         gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 209
 210         spin_unlock_irqrestore(&p->lock, flags);
 211 }
 212
 213 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 214 {
 215         return pinctrl_request_gpio(chip->base + offset);
 216 }
 217
 218 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 219 {
 220         pinctrl_free_gpio(chip->base + offset);
 221
 222         /* Set the GPIO as an input to ensure that the next GPIO request won't
 223          * drive the GPIO pin as an output.
 224          */
 225         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 226 }
 227
 228 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 229 {
 230         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 231         return 0;
 232 }
 233
 234 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
 235 {
 236         u32 bit = BIT(offset);
 237
 238         /* testing on r8a7790 shows that INDT does not show correct pin state
 239          * when configured as output, so use OUTDT in case of output pins */
 240         if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
 241                 return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
 242         else
 243                 return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
 244 }
 245
 246 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
 247 {
 248         struct gpio_rcar_priv *p = gpio_to_priv(chip);
 249         unsigned long flags;
 250
 251         spin_lock_irqsave(&p->lock, flags);
 252         gpio_rcar_modify_bit(p, OUTDT, offset, value);
 253         spin_unlock_irqrestore(&p->lock, flags);
 254 }
 255
 256 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 257                                       int value)
 258 {
 259         /* write GPIO value to output before selecting output mode of pin */
 260         gpio_rcar_set(chip, offset, value);
 261         gpio_rcar_config_general_input_output_mode(chip, offset, true);
 262         return 0;
 263 }
 264
 265 static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
 266 {
 267         return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
 268 }
 269
 270 static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq,
 271                                  irq_hw_number_t hwirq)
 272 {
 273         struct gpio_rcar_priv *p = h->host_data;
 274
 275         dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq);
 276
 277         irq_set_chip_data(irq, h->host_data);
 278         irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
 279         set_irq_flags(irq, IRQF_VALID); /* kill me now */
 280         return 0;
 281 }
 282
 283 static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
 284         .map    = gpio_rcar_irq_domain_map,
 285 };
 286
 287 static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
 288 {
 289         struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
 290         struct device_node *np = p->pdev->dev.of_node;
 291         struct of_phandle_args args;
 292         int ret;
 293
 294         if (pdata) {
 295                 p->config = *pdata;
 296         } else if (IS_ENABLED(CONFIG_OF) && np) {
 297                 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
 298                                                        &args);
 299                 p->config.number_of_pins = ret == 0 ? args.args[2]
 300                                          : RCAR_MAX_GPIO_PER_BANK;
 301                 p->config.gpio_base = -1;
 302         }
 303
 304         if (p->config.number_of_pins == 0 ||
 305             p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
 306                 dev_warn(&p->pdev->dev,
 307                          "Invalid number of gpio lines %u, using %u\n",
 308                          p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
 309                 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
 310         }
 311 }
 312
 313 static int gpio_rcar_probe(struct platform_device *pdev)
 314 {
 315         struct gpio_rcar_priv *p;
 316         struct resource *io, *irq;
 317         struct gpio_chip *gpio_chip;
 318         struct irq_chip *irq_chip;
 319         const char *name = dev_name(&pdev->dev);
 320         int ret;
 321
 322         p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
 323         if (!p) {
 324                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 325                 ret = -ENOMEM;
 326                 goto err0;
 327         }
 328
 329         p->pdev = pdev;
 330         spin_lock_init(&p->lock);
 331
 332         /* Get device configuration from DT node or platform data. */
 333         gpio_rcar_parse_pdata(p);
 334
 335         platform_set_drvdata(pdev, p);
 336
 337         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 338         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 339
 340         if (!io || !irq) {
 341                 dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
 342                 ret = -EINVAL;
 343                 goto err0;
 344         }
 345
 346         p->base = devm_ioremap_nocache(&pdev->dev, io->start,
 347                                        resource_size(io));
 348         if (!p->base) {
 349                 dev_err(&pdev->dev, "failed to remap I/O memory\n");
 350                 ret = -ENXIO;
 351                 goto err0;
 352         }
 353
 354         gpio_chip = &p->gpio_chip;
 355         gpio_chip->request = gpio_rcar_request;
 356         gpio_chip->free = gpio_rcar_free;
 357         gpio_chip->direction_input = gpio_rcar_direction_input;
 358         gpio_chip->get = gpio_rcar_get;
 359         gpio_chip->direction_output = gpio_rcar_direction_output;
 360         gpio_chip->set = gpio_rcar_set;
 361         gpio_chip->to_irq = gpio_rcar_to_irq;
 362         gpio_chip->label = name;
 363         gpio_chip->dev = &pdev->dev;
 364         gpio_chip->owner = THIS_MODULE;
 365         gpio_chip->base = p->config.gpio_base;
 366         gpio_chip->ngpio = p->config.number_of_pins;
 367
 368         irq_chip = &p->irq_chip;
 369         irq_chip->name = name;
 370         irq_chip->irq_mask = gpio_rcar_irq_disable;
 371         irq_chip->irq_unmask = gpio_rcar_irq_enable;
 372         irq_chip->irq_enable = gpio_rcar_irq_enable;
 373         irq_chip->irq_disable = gpio_rcar_irq_disable;
 374         irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 375         irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
 376
 377         p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 378                                               p->config.number_of_pins,
 379                                               p->config.irq_base,
 380                                               &gpio_rcar_irq_domain_ops, p);
 381         if (!p->irq_domain) {
 382                 ret = -ENXIO;
 383                 dev_err(&pdev->dev, "cannot initialize irq domain\n");
 384                 goto err1;
 385         }
 386
 387         if (devm_request_irq(&pdev->dev, irq->start,
 388                              gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
 389                 dev_err(&pdev->dev, "failed to request IRQ\n");
 390                 ret = -ENOENT;
 391                 goto err1;
 392         }
 393
 394         ret = gpiochip_add(gpio_chip);
 395         if (ret) {
 396                 dev_err(&pdev->dev, "failed to add GPIO controller\n");
 397                 goto err1;
 398         }
 399
 400         dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
 401
 402         /* warn in case of mismatch if irq base is specified */
 403         if (p->config.irq_base) {
 404                 ret = irq_find_mapping(p->irq_domain, 0);
 405                 if (p->config.irq_base != ret)
 406                         dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
 407                                  p->config.irq_base, ret);
 408         }
 409
 410         if (p->config.pctl_name) {
 411                 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
 412                                              gpio_chip->base, gpio_chip->ngpio);
 413                 if (ret < 0)
 414                         dev_warn(&pdev->dev, "failed to add pin range\n");
 415         }
 416
 417         return 0;
 418
 419 err1:
 420         irq_domain_remove(p->irq_domain);
 421 err0:
 422         return ret;
 423 }
 424
 425 static int gpio_rcar_remove(struct platform_device *pdev)
 426 {
 427         struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
 428         int ret;
 429
 430         ret = gpiochip_remove(&p->gpio_chip);
 431         if (ret)
 432                 return ret;
 433
 434         irq_domain_remove(p->irq_domain);
 435         return 0;
 436 }
 437
 438 #ifdef CONFIG_OF
 439 static const struct of_device_id gpio_rcar_of_table[] = {
 440         {
 441                 .compatible = "renesas,gpio-rcar",
 442         },
 443         { },
 444 };
 445
 446 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 447 #endif
 448
 449 static struct platform_driver gpio_rcar_device_driver = {
 450         .probe          = gpio_rcar_probe,
 451         .remove         = gpio_rcar_remove,
 452         .driver         = {
 453                 .name   = "gpio_rcar",
 454                 .of_match_table = of_match_ptr(gpio_rcar_of_table),
 455         }
 456 };
 457
 458 module_platform_driver(gpio_rcar_device_driver);
 459
 460 MODULE_AUTHOR("Magnus Damm");
 461 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
 462 MODULE_LICENSE("GPL v2");