drivers/gpio/gpio-pmic-eic-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Spreadtrum Communications Inc.
   4  * Copyright (C) 2018 Linaro Ltd.
   5  */
   6
   7 #include <linux/gpio/driver.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14
  15 /* EIC registers definition */
  16 #define SPRD_PMIC_EIC_DATA              0x0
  17 #define SPRD_PMIC_EIC_DMSK              0x4
  18 #define SPRD_PMIC_EIC_IEV               0x14
  19 #define SPRD_PMIC_EIC_IE                0x18
  20 #define SPRD_PMIC_EIC_RIS               0x1c
  21 #define SPRD_PMIC_EIC_MIS               0x20
  22 #define SPRD_PMIC_EIC_IC                0x24
  23 #define SPRD_PMIC_EIC_TRIG              0x28
  24 #define SPRD_PMIC_EIC_CTRL0             0x40
  25
  26 /*
  27  * The PMIC EIC controller only has one bank, and each bank now can contain
  28  * 16 EICs.
  29  */
  30 #define SPRD_PMIC_EIC_PER_BANK_NR       16
  31 #define SPRD_PMIC_EIC_NR                SPRD_PMIC_EIC_PER_BANK_NR
  32 #define SPRD_PMIC_EIC_DATA_MASK         GENMASK(15, 0)
  33 #define SPRD_PMIC_EIC_BIT(x)            ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
  34 #define SPRD_PMIC_EIC_DBNC_MASK         GENMASK(11, 0)
  35
  36 /*
  37  * These registers are modified under the irq bus lock and cached to avoid
  38  * unnecessary writes in bus_sync_unlock.
  39  */
  40 enum {
  41         REG_IEV,
  42         REG_IE,
  43         REG_TRIG,
  44         CACHE_NR_REGS
  45 };
  46
  47 /**
  48  * struct sprd_pmic_eic - PMIC EIC controller
  49  * @chip: the gpio_chip structure.
  50  * @intc: the irq_chip structure.
  51  * @regmap: the regmap from the parent device.
  52  * @offset: the EIC controller's offset address of the PMIC.
  53  * @reg: the array to cache the EIC registers.
  54  * @buslock: for bus lock/sync and unlock.
  55  * @irq: the interrupt number of the PMIC EIC conteroller.
  56  */
  57 struct sprd_pmic_eic {
  58         struct gpio_chip chip;
  59         struct irq_chip intc;
  60         struct regmap *map;
  61         u32 offset;
  62         u8 reg[CACHE_NR_REGS];
  63         struct mutex buslock;
  64         int irq;
  65 };
  66
  67 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
  68                                  u16 reg, unsigned int val)
  69 {
  70         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  71         u32 shift = SPRD_PMIC_EIC_BIT(offset);
  72
  73         regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
  74                            BIT(shift), val << shift);
  75 }
  76
  77 static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
  78                               u16 reg)
  79 {
  80         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  81         u32 value;
  82         int ret;
  83
  84         ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
  85         if (ret)
  86                 return ret;
  87
  88         return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
  89 }
  90
  91 static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
  92 {
  93         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
  94         return 0;
  95 }
  96
  97 static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
  98 {
  99         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
 100 }
 101
 102 static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
 103 {
 104         return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
 105 }
 106
 107 static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
 108                                          unsigned int offset)
 109 {
 110         /* EICs are always input, nothing need to do here. */
 111         return 0;
 112 }
 113
 114 static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
 115                               int value)
 116 {
 117         /* EICs are always input, nothing need to do here. */
 118 }
 119
 120 static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
 121                                       unsigned int offset,
 122                                       unsigned int debounce)
 123 {
 124         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
 125         u32 reg, value;
 126         int ret;
 127
 128         reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
 129         ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
 130         if (ret)
 131                 return ret;
 132
 133         value &= ~SPRD_PMIC_EIC_DBNC_MASK;
 134         value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
 135         return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
 136 }
 137
 138 static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
 139                                     unsigned long config)
 140 {
 141         unsigned long param = pinconf_to_config_param(config);
 142         u32 arg = pinconf_to_config_argument(config);
 143
 144         if (param == PIN_CONFIG_INPUT_DEBOUNCE)
 145                 return sprd_pmic_eic_set_debounce(chip, offset, arg);
 146
 147         return -ENOTSUPP;
 148 }
 149
 150 static void sprd_pmic_eic_irq_mask(struct irq_data *data)
 151 {
 152         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 153         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
 154
 155         pmic_eic->reg[REG_IE] = 0;
 156         pmic_eic->reg[REG_TRIG] = 0;
 157 }
 158
 159 static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
 160 {
 161         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 162         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
 163
 164         pmic_eic->reg[REG_IE] = 1;
 165         pmic_eic->reg[REG_TRIG] = 1;
 166 }
 167
 168 static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
 169                                       unsigned int flow_type)
 170 {
 171         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 172         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
 173
 174         switch (flow_type) {
 175         case IRQ_TYPE_LEVEL_HIGH:
 176                 pmic_eic->reg[REG_IEV] = 1;
 177                 break;
 178         case IRQ_TYPE_LEVEL_LOW:
 179                 pmic_eic->reg[REG_IEV] = 0;
 180                 break;
 181         default:
 182                 return -ENOTSUPP;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static void sprd_pmic_eic_bus_lock(struct irq_data *data)
 189 {
 190         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 191         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
 192
 193         mutex_lock(&pmic_eic->buslock);
 194 }
 195
 196 static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
 197 {
 198         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 199         struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
 200         u32 offset = irqd_to_hwirq(data);
 201
 202         /* Set irq type */
 203         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
 204                              pmic_eic->reg[REG_IEV]);
 205         /* Set irq unmask */
 206         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
 207                              pmic_eic->reg[REG_IE]);
 208         /* Generate trigger start pulse for debounce EIC */
 209         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
 210                              pmic_eic->reg[REG_TRIG]);
 211
 212         mutex_unlock(&pmic_eic->buslock);
 213 }
 214
 215 static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
 216 {
 217         struct sprd_pmic_eic *pmic_eic = data;
 218         struct gpio_chip *chip = &pmic_eic->chip;
 219         unsigned long status;
 220         u32 n, girq, val;
 221         int ret;
 222
 223         ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
 224                           &val);
 225         if (ret)
 226                 return IRQ_RETVAL(ret);
 227
 228         status = val & SPRD_PMIC_EIC_DATA_MASK;
 229
 230         for_each_set_bit(n, &status, chip->ngpio) {
 231                 /* Clear the interrupt */
 232                 sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);
 233
 234                 girq = irq_find_mapping(chip->irq.domain, n);
 235                 handle_nested_irq(girq);
 236         }
 237
 238         return IRQ_HANDLED;
 239 }
 240
 241 static int sprd_pmic_eic_probe(struct platform_device *pdev)
 242 {
 243         struct gpio_irq_chip *irq;
 244         struct sprd_pmic_eic *pmic_eic;
 245         int ret;
 246
 247         pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
 248         if (!pmic_eic)
 249                 return -ENOMEM;
 250
 251         mutex_init(&pmic_eic->buslock);
 252
 253         pmic_eic->irq = platform_get_irq(pdev, 0);
 254         if (pmic_eic->irq < 0) {
 255                 dev_err(&pdev->dev, "Failed to get PMIC EIC interrupt.\n");
 256                 return pmic_eic->irq;
 257         }
 258
 259         pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
 260         if (!pmic_eic->map)
 261                 return -ENODEV;
 262
 263         ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
 264         if (ret) {
 265                 dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
 266                 return ret;
 267         }
 268
 269         ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
 270                                         sprd_pmic_eic_irq_handler,
 271                                         IRQF_TRIGGER_LOW |
 272                                         IRQF_ONESHOT | IRQF_NO_SUSPEND,
 273                                         dev_name(&pdev->dev), pmic_eic);
 274         if (ret) {
 275                 dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
 276                 return ret;
 277         }
 278
 279         pmic_eic->chip.label = dev_name(&pdev->dev);
 280         pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
 281         pmic_eic->chip.base = -1;
 282         pmic_eic->chip.parent = &pdev->dev;
 283         pmic_eic->chip.of_node = pdev->dev.of_node;
 284         pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
 285         pmic_eic->chip.request = sprd_pmic_eic_request;
 286         pmic_eic->chip.free = sprd_pmic_eic_free;
 287         pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
 288         pmic_eic->chip.set = sprd_pmic_eic_set;
 289         pmic_eic->chip.get = sprd_pmic_eic_get;
 290
 291         pmic_eic->intc.name = dev_name(&pdev->dev);
 292         pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
 293         pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
 294         pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
 295         pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
 296         pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
 297         pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
 298
 299         irq = &pmic_eic->chip.irq;
 300         irq->chip = &pmic_eic->intc;
 301         irq->threaded = true;
 302
 303         ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
 304         if (ret < 0) {
 305                 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
 306                 return ret;
 307         }
 308
 309         platform_set_drvdata(pdev, pmic_eic);
 310         return 0;
 311 }
 312
 313 static const struct of_device_id sprd_pmic_eic_of_match[] = {
 314         { .compatible = "sprd,sc27xx-eic", },
 315         { /* end of list */ }
 316 };
 317 MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
 318
 319 static struct platform_driver sprd_pmic_eic_driver = {
 320         .probe = sprd_pmic_eic_probe,
 321         .driver = {
 322                 .name = "sprd-pmic-eic",
 323                 .of_match_table = sprd_pmic_eic_of_match,
 324         },
 325 };
 326
 327 module_platform_driver(sprd_pmic_eic_driver);
 328
 329 MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
 330 MODULE_LICENSE("GPL v2");