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xfs: add full xfs_dqblk verifier
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob8fb8c737fffefa18ac3ae716474a40002a36ff05
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
46 #include <asm/apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
51 #include <asm/gart.h>
52 #include <asm/dma.h>
53
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
57
58 #define AMD_IOMMU_MAPPING_ERROR 0
59
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
62 #define LOOP_TIMEOUT 100000
63
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
86
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * general struct to manage commands send to an IOMMU
107 */
108 struct iommu_cmd {
109 u32 data[4];
110 };
111
112 struct kmem_cache *amd_iommu_irq_cache;
113
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118
119 /*
120 * Data container for a dma_ops specific protection domain
121 */
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
128 };
129
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
132
133 /****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
141 {
142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
157 }
158
159 static inline u16 get_pci_device_id(struct device *dev)
160 {
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164 }
165
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168 {
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179 }
180
181 static inline int get_device_id(struct device *dev)
182 {
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191 }
192
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194 {
195 return container_of(dom, struct protection_domain, domain);
196 }
197
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199 {
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202 }
203
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
205 {
206 struct iommu_dev_data *dev_data;
207
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
209 if (!dev_data)
210 return NULL;
211
212 dev_data->devid = devid;
213 ratelimit_default_init(&dev_data->rs);
214
215 llist_add(&dev_data->dev_data_list, &dev_data_list);
216 return dev_data;
217 }
218
219 static struct iommu_dev_data *search_dev_data(u16 devid)
220 {
221 struct iommu_dev_data *dev_data;
222 struct llist_node *node;
223
224 if (llist_empty(&dev_data_list))
225 return NULL;
226
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
229 if (dev_data->devid == devid)
230 return dev_data;
231 }
232
233 return NULL;
234 }
235
236 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
237 {
238 *(u16 *)data = alias;
239 return 0;
240 }
241
242 static u16 get_alias(struct device *dev)
243 {
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
246
247 /* The callers make sure that get_device_id() does not fail here */
248 devid = get_device_id(dev);
249 ivrs_alias = amd_iommu_alias_table[devid];
250 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
251
252 if (ivrs_alias == pci_alias)
253 return ivrs_alias;
254
255 /*
256 * DMA alias showdown
257 *
258 * The IVRS is fairly reliable in telling us about aliases, but it
259 * can't know about every screwy device. If we don't have an IVRS
260 * reported alias, use the PCI reported alias. In that case we may
261 * still need to initialize the rlookup and dev_table entries if the
262 * alias is to a non-existent device.
263 */
264 if (ivrs_alias == devid) {
265 if (!amd_iommu_rlookup_table[pci_alias]) {
266 amd_iommu_rlookup_table[pci_alias] =
267 amd_iommu_rlookup_table[devid];
268 memcpy(amd_iommu_dev_table[pci_alias].data,
269 amd_iommu_dev_table[devid].data,
270 sizeof(amd_iommu_dev_table[pci_alias].data));
271 }
272
273 return pci_alias;
274 }
275
276 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
277 "for device %s[%04x:%04x], kernel reported alias "
278 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
279 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
280 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
281 PCI_FUNC(pci_alias));
282
283 /*
284 * If we don't have a PCI DMA alias and the IVRS alias is on the same
285 * bus, then the IVRS table may know about a quirk that we don't.
286 */
287 if (pci_alias == devid &&
288 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
289 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
290 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
291 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
292 dev_name(dev));
293 }
294
295 return ivrs_alias;
296 }
297
298 static struct iommu_dev_data *find_dev_data(u16 devid)
299 {
300 struct iommu_dev_data *dev_data;
301 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
302
303 dev_data = search_dev_data(devid);
304
305 if (dev_data == NULL) {
306 dev_data = alloc_dev_data(devid);
307 if (!dev_data)
308 return NULL;
309
310 if (translation_pre_enabled(iommu))
311 dev_data->defer_attach = true;
312 }
313
314 return dev_data;
315 }
316
317 struct iommu_dev_data *get_dev_data(struct device *dev)
318 {
319 return dev->archdata.iommu;
320 }
321 EXPORT_SYMBOL(get_dev_data);
322
323 /*
324 * Find or create an IOMMU group for a acpihid device.
325 */
326 static struct iommu_group *acpihid_device_group(struct device *dev)
327 {
328 struct acpihid_map_entry *p, *entry = NULL;
329 int devid;
330
331 devid = get_acpihid_device_id(dev, &entry);
332 if (devid < 0)
333 return ERR_PTR(devid);
334
335 list_for_each_entry(p, &acpihid_map, list) {
336 if ((devid == p->devid) && p->group)
337 entry->group = p->group;
338 }
339
340 if (!entry->group)
341 entry->group = generic_device_group(dev);
342 else
343 iommu_group_ref_get(entry->group);
344
345 return entry->group;
346 }
347
348 static bool pci_iommuv2_capable(struct pci_dev *pdev)
349 {
350 static const int caps[] = {
351 PCI_EXT_CAP_ID_ATS,
352 PCI_EXT_CAP_ID_PRI,
353 PCI_EXT_CAP_ID_PASID,
354 };
355 int i, pos;
356
357 for (i = 0; i < 3; ++i) {
358 pos = pci_find_ext_capability(pdev, caps[i]);
359 if (pos == 0)
360 return false;
361 }
362
363 return true;
364 }
365
366 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
367 {
368 struct iommu_dev_data *dev_data;
369
370 dev_data = get_dev_data(&pdev->dev);
371
372 return dev_data->errata & (1 << erratum) ? true : false;
373 }
374
375 /*
376 * This function checks if the driver got a valid device from the caller to
377 * avoid dereferencing invalid pointers.
378 */
379 static bool check_device(struct device *dev)
380 {
381 int devid;
382
383 if (!dev || !dev->dma_mask)
384 return false;
385
386 devid = get_device_id(dev);
387 if (devid < 0)
388 return false;
389
390 /* Out of our scope? */
391 if (devid > amd_iommu_last_bdf)
392 return false;
393
394 if (amd_iommu_rlookup_table[devid] == NULL)
395 return false;
396
397 return true;
398 }
399
400 static void init_iommu_group(struct device *dev)
401 {
402 struct iommu_group *group;
403
404 group = iommu_group_get_for_dev(dev);
405 if (IS_ERR(group))
406 return;
407
408 iommu_group_put(group);
409 }
410
411 static int iommu_init_device(struct device *dev)
412 {
413 struct iommu_dev_data *dev_data;
414 struct amd_iommu *iommu;
415 int devid;
416
417 if (dev->archdata.iommu)
418 return 0;
419
420 devid = get_device_id(dev);
421 if (devid < 0)
422 return devid;
423
424 iommu = amd_iommu_rlookup_table[devid];
425
426 dev_data = find_dev_data(devid);
427 if (!dev_data)
428 return -ENOMEM;
429
430 dev_data->alias = get_alias(dev);
431
432 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
433 struct amd_iommu *iommu;
434
435 iommu = amd_iommu_rlookup_table[dev_data->devid];
436 dev_data->iommu_v2 = iommu->is_iommu_v2;
437 }
438
439 dev->archdata.iommu = dev_data;
440
441 iommu_device_link(&iommu->iommu, dev);
442
443 return 0;
444 }
445
446 static void iommu_ignore_device(struct device *dev)
447 {
448 u16 alias;
449 int devid;
450
451 devid = get_device_id(dev);
452 if (devid < 0)
453 return;
454
455 alias = get_alias(dev);
456
457 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
458 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
459
460 amd_iommu_rlookup_table[devid] = NULL;
461 amd_iommu_rlookup_table[alias] = NULL;
462 }
463
464 static void iommu_uninit_device(struct device *dev)
465 {
466 struct iommu_dev_data *dev_data;
467 struct amd_iommu *iommu;
468 int devid;
469
470 devid = get_device_id(dev);
471 if (devid < 0)
472 return;
473
474 iommu = amd_iommu_rlookup_table[devid];
475
476 dev_data = search_dev_data(devid);
477 if (!dev_data)
478 return;
479
480 if (dev_data->domain)
481 detach_device(dev);
482
483 iommu_device_unlink(&iommu->iommu, dev);
484
485 iommu_group_remove_device(dev);
486
487 /* Remove dma-ops */
488 dev->dma_ops = NULL;
489
490 /*
491 * We keep dev_data around for unplugged devices and reuse it when the
492 * device is re-plugged - not doing so would introduce a ton of races.
493 */
494 }
495
496 /****************************************************************************
497 *
498 * Interrupt handling functions
499 *
500 ****************************************************************************/
501
502 static void dump_dte_entry(u16 devid)
503 {
504 int i;
505
506 for (i = 0; i < 4; ++i)
507 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
508 amd_iommu_dev_table[devid].data[i]);
509 }
510
511 static void dump_command(unsigned long phys_addr)
512 {
513 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
514 int i;
515
516 for (i = 0; i < 4; ++i)
517 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
518 }
519
520 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
521 u64 address, int flags)
522 {
523 struct iommu_dev_data *dev_data = NULL;
524 struct pci_dev *pdev;
525
526 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
527 devid & 0xff);
528 if (pdev)
529 dev_data = get_dev_data(&pdev->dev);
530
531 if (dev_data && __ratelimit(&dev_data->rs)) {
532 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
533 domain_id, address, flags);
534 } else if (printk_ratelimit()) {
535 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
537 domain_id, address, flags);
538 }
539
540 if (pdev)
541 pci_dev_put(pdev);
542 }
543
544 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
545 {
546 struct device *dev = iommu->iommu.dev;
547 int type, devid, domid, flags;
548 volatile u32 *event = __evt;
549 int count = 0;
550 u64 address;
551
552 retry:
553 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
554 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
555 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
556 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
557 address = (u64)(((u64)event[3]) << 32) | event[2];
558
559 if (type == 0) {
560 /* Did we hit the erratum? */
561 if (++count == LOOP_TIMEOUT) {
562 pr_err("AMD-Vi: No event written to event log\n");
563 return;
564 }
565 udelay(1);
566 goto retry;
567 }
568
569 if (type == EVENT_TYPE_IO_FAULT) {
570 amd_iommu_report_page_fault(devid, domid, address, flags);
571 return;
572 } else {
573 dev_err(dev, "AMD-Vi: Event logged [");
574 }
575
576 switch (type) {
577 case EVENT_TYPE_ILL_DEV:
578 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
579 "address=0x%016llx flags=0x%04x]\n",
580 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
581 address, flags);
582 dump_dte_entry(devid);
583 break;
584 case EVENT_TYPE_DEV_TAB_ERR:
585 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
586 "address=0x%016llx flags=0x%04x]\n",
587 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
588 address, flags);
589 break;
590 case EVENT_TYPE_PAGE_TAB_ERR:
591 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
592 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
593 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
594 domid, address, flags);
595 break;
596 case EVENT_TYPE_ILL_CMD:
597 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
598 dump_command(address);
599 break;
600 case EVENT_TYPE_CMD_HARD_ERR:
601 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx "
602 "flags=0x%04x]\n", address, flags);
603 break;
604 case EVENT_TYPE_IOTLB_INV_TO:
605 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
606 "address=0x%016llx]\n",
607 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
608 address);
609 break;
610 case EVENT_TYPE_INV_DEV_REQ:
611 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
612 "address=0x%016llx flags=0x%04x]\n",
613 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 address, flags);
615 break;
616 default:
617 dev_err(dev, KERN_ERR "UNKNOWN event[0]=0x%08x event[1]=0x%08x "
618 "event[2]=0x%08x event[3]=0x%08x\n",
619 event[0], event[1], event[2], event[3]);
620 }
621
622 memset(__evt, 0, 4 * sizeof(u32));
623 }
624
625 static void iommu_poll_events(struct amd_iommu *iommu)
626 {
627 u32 head, tail;
628
629 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
630 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
631
632 while (head != tail) {
633 iommu_print_event(iommu, iommu->evt_buf + head);
634 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
635 }
636
637 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
638 }
639
640 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
641 {
642 struct amd_iommu_fault fault;
643
644 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
645 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
646 return;
647 }
648
649 fault.address = raw[1];
650 fault.pasid = PPR_PASID(raw[0]);
651 fault.device_id = PPR_DEVID(raw[0]);
652 fault.tag = PPR_TAG(raw[0]);
653 fault.flags = PPR_FLAGS(raw[0]);
654
655 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
656 }
657
658 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
659 {
660 u32 head, tail;
661
662 if (iommu->ppr_log == NULL)
663 return;
664
665 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
666 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
667
668 while (head != tail) {
669 volatile u64 *raw;
670 u64 entry[2];
671 int i;
672
673 raw = (u64 *)(iommu->ppr_log + head);
674
675 /*
676 * Hardware bug: Interrupt may arrive before the entry is
677 * written to memory. If this happens we need to wait for the
678 * entry to arrive.
679 */
680 for (i = 0; i < LOOP_TIMEOUT; ++i) {
681 if (PPR_REQ_TYPE(raw[0]) != 0)
682 break;
683 udelay(1);
684 }
685
686 /* Avoid memcpy function-call overhead */
687 entry[0] = raw[0];
688 entry[1] = raw[1];
689
690 /*
691 * To detect the hardware bug we need to clear the entry
692 * back to zero.
693 */
694 raw[0] = raw[1] = 0UL;
695
696 /* Update head pointer of hardware ring-buffer */
697 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
698 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
699
700 /* Handle PPR entry */
701 iommu_handle_ppr_entry(iommu, entry);
702
703 /* Refresh ring-buffer information */
704 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
705 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
706 }
707 }
708
709 #ifdef CONFIG_IRQ_REMAP
710 static int (*iommu_ga_log_notifier)(u32);
711
712 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
713 {
714 iommu_ga_log_notifier = notifier;
715
716 return 0;
717 }
718 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
719
720 static void iommu_poll_ga_log(struct amd_iommu *iommu)
721 {
722 u32 head, tail, cnt = 0;
723
724 if (iommu->ga_log == NULL)
725 return;
726
727 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
728 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
729
730 while (head != tail) {
731 volatile u64 *raw;
732 u64 log_entry;
733
734 raw = (u64 *)(iommu->ga_log + head);
735 cnt++;
736
737 /* Avoid memcpy function-call overhead */
738 log_entry = *raw;
739
740 /* Update head pointer of hardware ring-buffer */
741 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
742 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
743
744 /* Handle GA entry */
745 switch (GA_REQ_TYPE(log_entry)) {
746 case GA_GUEST_NR:
747 if (!iommu_ga_log_notifier)
748 break;
749
750 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
751 __func__, GA_DEVID(log_entry),
752 GA_TAG(log_entry));
753
754 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
755 pr_err("AMD-Vi: GA log notifier failed.\n");
756 break;
757 default:
758 break;
759 }
760 }
761 }
762 #endif /* CONFIG_IRQ_REMAP */
763
764 #define AMD_IOMMU_INT_MASK \
765 (MMIO_STATUS_EVT_INT_MASK | \
766 MMIO_STATUS_PPR_INT_MASK | \
767 MMIO_STATUS_GALOG_INT_MASK)
768
769 irqreturn_t amd_iommu_int_thread(int irq, void *data)
770 {
771 struct amd_iommu *iommu = (struct amd_iommu *) data;
772 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
773
774 while (status & AMD_IOMMU_INT_MASK) {
775 /* Enable EVT and PPR and GA interrupts again */
776 writel(AMD_IOMMU_INT_MASK,
777 iommu->mmio_base + MMIO_STATUS_OFFSET);
778
779 if (status & MMIO_STATUS_EVT_INT_MASK) {
780 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
781 iommu_poll_events(iommu);
782 }
783
784 if (status & MMIO_STATUS_PPR_INT_MASK) {
785 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
786 iommu_poll_ppr_log(iommu);
787 }
788
789 #ifdef CONFIG_IRQ_REMAP
790 if (status & MMIO_STATUS_GALOG_INT_MASK) {
791 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
792 iommu_poll_ga_log(iommu);
793 }
794 #endif
795
796 /*
797 * Hardware bug: ERBT1312
798 * When re-enabling interrupt (by writing 1
799 * to clear the bit), the hardware might also try to set
800 * the interrupt bit in the event status register.
801 * In this scenario, the bit will be set, and disable
802 * subsequent interrupts.
803 *
804 * Workaround: The IOMMU driver should read back the
805 * status register and check if the interrupt bits are cleared.
806 * If not, driver will need to go through the interrupt handler
807 * again and re-clear the bits
808 */
809 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
810 }
811 return IRQ_HANDLED;
812 }
813
814 irqreturn_t amd_iommu_int_handler(int irq, void *data)
815 {
816 return IRQ_WAKE_THREAD;
817 }
818
819 /****************************************************************************
820 *
821 * IOMMU command queuing functions
822 *
823 ****************************************************************************/
824
825 static int wait_on_sem(volatile u64 *sem)
826 {
827 int i = 0;
828
829 while (*sem == 0 && i < LOOP_TIMEOUT) {
830 udelay(1);
831 i += 1;
832 }
833
834 if (i == LOOP_TIMEOUT) {
835 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
836 return -EIO;
837 }
838
839 return 0;
840 }
841
842 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
843 struct iommu_cmd *cmd)
844 {
845 u8 *target;
846
847 target = iommu->cmd_buf + iommu->cmd_buf_tail;
848
849 iommu->cmd_buf_tail += sizeof(*cmd);
850 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
851
852 /* Copy command to buffer */
853 memcpy(target, cmd, sizeof(*cmd));
854
855 /* Tell the IOMMU about it */
856 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
857 }
858
859 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
860 {
861 u64 paddr = iommu_virt_to_phys((void *)address);
862
863 WARN_ON(address & 0x7ULL);
864
865 memset(cmd, 0, sizeof(*cmd));
866 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
867 cmd->data[1] = upper_32_bits(paddr);
868 cmd->data[2] = 1;
869 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
870 }
871
872 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
873 {
874 memset(cmd, 0, sizeof(*cmd));
875 cmd->data[0] = devid;
876 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
877 }
878
879 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
880 size_t size, u16 domid, int pde)
881 {
882 u64 pages;
883 bool s;
884
885 pages = iommu_num_pages(address, size, PAGE_SIZE);
886 s = false;
887
888 if (pages > 1) {
889 /*
890 * If we have to flush more than one page, flush all
891 * TLB entries for this domain
892 */
893 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
894 s = true;
895 }
896
897 address &= PAGE_MASK;
898
899 memset(cmd, 0, sizeof(*cmd));
900 cmd->data[1] |= domid;
901 cmd->data[2] = lower_32_bits(address);
902 cmd->data[3] = upper_32_bits(address);
903 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
904 if (s) /* size bit - we flush more than one 4kb page */
905 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
906 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
907 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
908 }
909
910 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
911 u64 address, size_t size)
912 {
913 u64 pages;
914 bool s;
915
916 pages = iommu_num_pages(address, size, PAGE_SIZE);
917 s = false;
918
919 if (pages > 1) {
920 /*
921 * If we have to flush more than one page, flush all
922 * TLB entries for this domain
923 */
924 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
925 s = true;
926 }
927
928 address &= PAGE_MASK;
929
930 memset(cmd, 0, sizeof(*cmd));
931 cmd->data[0] = devid;
932 cmd->data[0] |= (qdep & 0xff) << 24;
933 cmd->data[1] = devid;
934 cmd->data[2] = lower_32_bits(address);
935 cmd->data[3] = upper_32_bits(address);
936 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
937 if (s)
938 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
939 }
940
941 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
942 u64 address, bool size)
943 {
944 memset(cmd, 0, sizeof(*cmd));
945
946 address &= ~(0xfffULL);
947
948 cmd->data[0] = pasid;
949 cmd->data[1] = domid;
950 cmd->data[2] = lower_32_bits(address);
951 cmd->data[3] = upper_32_bits(address);
952 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
953 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
954 if (size)
955 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
956 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
957 }
958
959 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
960 int qdep, u64 address, bool size)
961 {
962 memset(cmd, 0, sizeof(*cmd));
963
964 address &= ~(0xfffULL);
965
966 cmd->data[0] = devid;
967 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
968 cmd->data[0] |= (qdep & 0xff) << 24;
969 cmd->data[1] = devid;
970 cmd->data[1] |= (pasid & 0xff) << 16;
971 cmd->data[2] = lower_32_bits(address);
972 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
973 cmd->data[3] = upper_32_bits(address);
974 if (size)
975 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
976 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
977 }
978
979 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
980 int status, int tag, bool gn)
981 {
982 memset(cmd, 0, sizeof(*cmd));
983
984 cmd->data[0] = devid;
985 if (gn) {
986 cmd->data[1] = pasid;
987 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
988 }
989 cmd->data[3] = tag & 0x1ff;
990 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
991
992 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
993 }
994
995 static void build_inv_all(struct iommu_cmd *cmd)
996 {
997 memset(cmd, 0, sizeof(*cmd));
998 CMD_SET_TYPE(cmd, CMD_INV_ALL);
999 }
1000
1001 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1002 {
1003 memset(cmd, 0, sizeof(*cmd));
1004 cmd->data[0] = devid;
1005 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1006 }
1007
1008 /*
1009 * Writes the command to the IOMMUs command buffer and informs the
1010 * hardware about the new command.
1011 */
1012 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1013 struct iommu_cmd *cmd,
1014 bool sync)
1015 {
1016 unsigned int count = 0;
1017 u32 left, next_tail;
1018
1019 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1020 again:
1021 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1022
1023 if (left <= 0x20) {
1024 /* Skip udelay() the first time around */
1025 if (count++) {
1026 if (count == LOOP_TIMEOUT) {
1027 pr_err("AMD-Vi: Command buffer timeout\n");
1028 return -EIO;
1029 }
1030
1031 udelay(1);
1032 }
1033
1034 /* Update head and recheck remaining space */
1035 iommu->cmd_buf_head = readl(iommu->mmio_base +
1036 MMIO_CMD_HEAD_OFFSET);
1037
1038 goto again;
1039 }
1040
1041 copy_cmd_to_buffer(iommu, cmd);
1042
1043 /* Do we need to make sure all commands are processed? */
1044 iommu->need_sync = sync;
1045
1046 return 0;
1047 }
1048
1049 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1050 struct iommu_cmd *cmd,
1051 bool sync)
1052 {
1053 unsigned long flags;
1054 int ret;
1055
1056 raw_spin_lock_irqsave(&iommu->lock, flags);
1057 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1058 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1059
1060 return ret;
1061 }
1062
1063 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1064 {
1065 return iommu_queue_command_sync(iommu, cmd, true);
1066 }
1067
1068 /*
1069 * This function queues a completion wait command into the command
1070 * buffer of an IOMMU
1071 */
1072 static int iommu_completion_wait(struct amd_iommu *iommu)
1073 {
1074 struct iommu_cmd cmd;
1075 unsigned long flags;
1076 int ret;
1077
1078 if (!iommu->need_sync)
1079 return 0;
1080
1081
1082 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1083
1084 raw_spin_lock_irqsave(&iommu->lock, flags);
1085
1086 iommu->cmd_sem = 0;
1087
1088 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1089 if (ret)
1090 goto out_unlock;
1091
1092 ret = wait_on_sem(&iommu->cmd_sem);
1093
1094 out_unlock:
1095 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1096
1097 return ret;
1098 }
1099
1100 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1101 {
1102 struct iommu_cmd cmd;
1103
1104 build_inv_dte(&cmd, devid);
1105
1106 return iommu_queue_command(iommu, &cmd);
1107 }
1108
1109 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1110 {
1111 u32 devid;
1112
1113 for (devid = 0; devid <= 0xffff; ++devid)
1114 iommu_flush_dte(iommu, devid);
1115
1116 iommu_completion_wait(iommu);
1117 }
1118
1119 /*
1120 * This function uses heavy locking and may disable irqs for some time. But
1121 * this is no issue because it is only called during resume.
1122 */
1123 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1124 {
1125 u32 dom_id;
1126
1127 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1128 struct iommu_cmd cmd;
1129 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1130 dom_id, 1);
1131 iommu_queue_command(iommu, &cmd);
1132 }
1133
1134 iommu_completion_wait(iommu);
1135 }
1136
1137 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1138 {
1139 struct iommu_cmd cmd;
1140
1141 build_inv_all(&cmd);
1142
1143 iommu_queue_command(iommu, &cmd);
1144 iommu_completion_wait(iommu);
1145 }
1146
1147 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1148 {
1149 struct iommu_cmd cmd;
1150
1151 build_inv_irt(&cmd, devid);
1152
1153 iommu_queue_command(iommu, &cmd);
1154 }
1155
1156 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1157 {
1158 u32 devid;
1159
1160 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1161 iommu_flush_irt(iommu, devid);
1162
1163 iommu_completion_wait(iommu);
1164 }
1165
1166 void iommu_flush_all_caches(struct amd_iommu *iommu)
1167 {
1168 if (iommu_feature(iommu, FEATURE_IA)) {
1169 amd_iommu_flush_all(iommu);
1170 } else {
1171 amd_iommu_flush_dte_all(iommu);
1172 amd_iommu_flush_irt_all(iommu);
1173 amd_iommu_flush_tlb_all(iommu);
1174 }
1175 }
1176
1177 /*
1178 * Command send function for flushing on-device TLB
1179 */
1180 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1181 u64 address, size_t size)
1182 {
1183 struct amd_iommu *iommu;
1184 struct iommu_cmd cmd;
1185 int qdep;
1186
1187 qdep = dev_data->ats.qdep;
1188 iommu = amd_iommu_rlookup_table[dev_data->devid];
1189
1190 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1191
1192 return iommu_queue_command(iommu, &cmd);
1193 }
1194
1195 /*
1196 * Command send function for invalidating a device table entry
1197 */
1198 static int device_flush_dte(struct iommu_dev_data *dev_data)
1199 {
1200 struct amd_iommu *iommu;
1201 u16 alias;
1202 int ret;
1203
1204 iommu = amd_iommu_rlookup_table[dev_data->devid];
1205 alias = dev_data->alias;
1206
1207 ret = iommu_flush_dte(iommu, dev_data->devid);
1208 if (!ret && alias != dev_data->devid)
1209 ret = iommu_flush_dte(iommu, alias);
1210 if (ret)
1211 return ret;
1212
1213 if (dev_data->ats.enabled)
1214 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1215
1216 return ret;
1217 }
1218
1219 /*
1220 * TLB invalidation function which is called from the mapping functions.
1221 * It invalidates a single PTE if the range to flush is within a single
1222 * page. Otherwise it flushes the whole TLB of the IOMMU.
1223 */
1224 static void __domain_flush_pages(struct protection_domain *domain,
1225 u64 address, size_t size, int pde)
1226 {
1227 struct iommu_dev_data *dev_data;
1228 struct iommu_cmd cmd;
1229 int ret = 0, i;
1230
1231 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1232
1233 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1234 if (!domain->dev_iommu[i])
1235 continue;
1236
1237 /*
1238 * Devices of this domain are behind this IOMMU
1239 * We need a TLB flush
1240 */
1241 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1242 }
1243
1244 list_for_each_entry(dev_data, &domain->dev_list, list) {
1245
1246 if (!dev_data->ats.enabled)
1247 continue;
1248
1249 ret |= device_flush_iotlb(dev_data, address, size);
1250 }
1251
1252 WARN_ON(ret);
1253 }
1254
1255 static void domain_flush_pages(struct protection_domain *domain,
1256 u64 address, size_t size)
1257 {
1258 __domain_flush_pages(domain, address, size, 0);
1259 }
1260
1261 /* Flush the whole IO/TLB for a given protection domain */
1262 static void domain_flush_tlb(struct protection_domain *domain)
1263 {
1264 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1265 }
1266
1267 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1268 static void domain_flush_tlb_pde(struct protection_domain *domain)
1269 {
1270 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1271 }
1272
1273 static void domain_flush_complete(struct protection_domain *domain)
1274 {
1275 int i;
1276
1277 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1278 if (domain && !domain->dev_iommu[i])
1279 continue;
1280
1281 /*
1282 * Devices of this domain are behind this IOMMU
1283 * We need to wait for completion of all commands.
1284 */
1285 iommu_completion_wait(amd_iommus[i]);
1286 }
1287 }
1288
1289
1290 /*
1291 * This function flushes the DTEs for all devices in domain
1292 */
1293 static void domain_flush_devices(struct protection_domain *domain)
1294 {
1295 struct iommu_dev_data *dev_data;
1296
1297 list_for_each_entry(dev_data, &domain->dev_list, list)
1298 device_flush_dte(dev_data);
1299 }
1300
1301 /****************************************************************************
1302 *
1303 * The functions below are used the create the page table mappings for
1304 * unity mapped regions.
1305 *
1306 ****************************************************************************/
1307
1308 /*
1309 * This function is used to add another level to an IO page table. Adding
1310 * another level increases the size of the address space by 9 bits to a size up
1311 * to 64 bits.
1312 */
1313 static bool increase_address_space(struct protection_domain *domain,
1314 gfp_t gfp)
1315 {
1316 u64 *pte;
1317
1318 if (domain->mode == PAGE_MODE_6_LEVEL)
1319 /* address space already 64 bit large */
1320 return false;
1321
1322 pte = (void *)get_zeroed_page(gfp);
1323 if (!pte)
1324 return false;
1325
1326 *pte = PM_LEVEL_PDE(domain->mode,
1327 iommu_virt_to_phys(domain->pt_root));
1328 domain->pt_root = pte;
1329 domain->mode += 1;
1330 domain->updated = true;
1331
1332 return true;
1333 }
1334
1335 static u64 *alloc_pte(struct protection_domain *domain,
1336 unsigned long address,
1337 unsigned long page_size,
1338 u64 **pte_page,
1339 gfp_t gfp)
1340 {
1341 int level, end_lvl;
1342 u64 *pte, *page;
1343
1344 BUG_ON(!is_power_of_2(page_size));
1345
1346 while (address > PM_LEVEL_SIZE(domain->mode))
1347 increase_address_space(domain, gfp);
1348
1349 level = domain->mode - 1;
1350 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1351 address = PAGE_SIZE_ALIGN(address, page_size);
1352 end_lvl = PAGE_SIZE_LEVEL(page_size);
1353
1354 while (level > end_lvl) {
1355 u64 __pte, __npte;
1356
1357 __pte = *pte;
1358
1359 if (!IOMMU_PTE_PRESENT(__pte)) {
1360 page = (u64 *)get_zeroed_page(gfp);
1361 if (!page)
1362 return NULL;
1363
1364 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1365
1366 /* pte could have been changed somewhere. */
1367 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1368 free_page((unsigned long)page);
1369 continue;
1370 }
1371 }
1372
1373 /* No level skipping support yet */
1374 if (PM_PTE_LEVEL(*pte) != level)
1375 return NULL;
1376
1377 level -= 1;
1378
1379 pte = IOMMU_PTE_PAGE(*pte);
1380
1381 if (pte_page && level == end_lvl)
1382 *pte_page = pte;
1383
1384 pte = &pte[PM_LEVEL_INDEX(level, address)];
1385 }
1386
1387 return pte;
1388 }
1389
1390 /*
1391 * This function checks if there is a PTE for a given dma address. If
1392 * there is one, it returns the pointer to it.
1393 */
1394 static u64 *fetch_pte(struct protection_domain *domain,
1395 unsigned long address,
1396 unsigned long *page_size)
1397 {
1398 int level;
1399 u64 *pte;
1400
1401 if (address > PM_LEVEL_SIZE(domain->mode))
1402 return NULL;
1403
1404 level = domain->mode - 1;
1405 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1406 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1407
1408 while (level > 0) {
1409
1410 /* Not Present */
1411 if (!IOMMU_PTE_PRESENT(*pte))
1412 return NULL;
1413
1414 /* Large PTE */
1415 if (PM_PTE_LEVEL(*pte) == 7 ||
1416 PM_PTE_LEVEL(*pte) == 0)
1417 break;
1418
1419 /* No level skipping support yet */
1420 if (PM_PTE_LEVEL(*pte) != level)
1421 return NULL;
1422
1423 level -= 1;
1424
1425 /* Walk to the next level */
1426 pte = IOMMU_PTE_PAGE(*pte);
1427 pte = &pte[PM_LEVEL_INDEX(level, address)];
1428 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1429 }
1430
1431 if (PM_PTE_LEVEL(*pte) == 0x07) {
1432 unsigned long pte_mask;
1433
1434 /*
1435 * If we have a series of large PTEs, make
1436 * sure to return a pointer to the first one.
1437 */
1438 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1439 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1440 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1441 }
1442
1443 return pte;
1444 }
1445
1446 /*
1447 * Generic mapping functions. It maps a physical address into a DMA
1448 * address space. It allocates the page table pages if necessary.
1449 * In the future it can be extended to a generic mapping function
1450 * supporting all features of AMD IOMMU page tables like level skipping
1451 * and full 64 bit address spaces.
1452 */
1453 static int iommu_map_page(struct protection_domain *dom,
1454 unsigned long bus_addr,
1455 unsigned long phys_addr,
1456 unsigned long page_size,
1457 int prot,
1458 gfp_t gfp)
1459 {
1460 u64 __pte, *pte;
1461 int i, count;
1462
1463 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1464 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1465
1466 if (!(prot & IOMMU_PROT_MASK))
1467 return -EINVAL;
1468
1469 count = PAGE_SIZE_PTE_COUNT(page_size);
1470 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1471
1472 if (!pte)
1473 return -ENOMEM;
1474
1475 for (i = 0; i < count; ++i)
1476 if (IOMMU_PTE_PRESENT(pte[i]))
1477 return -EBUSY;
1478
1479 if (count > 1) {
1480 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1481 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1482 } else
1483 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1484
1485 if (prot & IOMMU_PROT_IR)
1486 __pte |= IOMMU_PTE_IR;
1487 if (prot & IOMMU_PROT_IW)
1488 __pte |= IOMMU_PTE_IW;
1489
1490 for (i = 0; i < count; ++i)
1491 pte[i] = __pte;
1492
1493 update_domain(dom);
1494
1495 return 0;
1496 }
1497
1498 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1499 unsigned long bus_addr,
1500 unsigned long page_size)
1501 {
1502 unsigned long long unmapped;
1503 unsigned long unmap_size;
1504 u64 *pte;
1505
1506 BUG_ON(!is_power_of_2(page_size));
1507
1508 unmapped = 0;
1509
1510 while (unmapped < page_size) {
1511
1512 pte = fetch_pte(dom, bus_addr, &unmap_size);
1513
1514 if (pte) {
1515 int i, count;
1516
1517 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1518 for (i = 0; i < count; i++)
1519 pte[i] = 0ULL;
1520 }
1521
1522 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1523 unmapped += unmap_size;
1524 }
1525
1526 BUG_ON(unmapped && !is_power_of_2(unmapped));
1527
1528 return unmapped;
1529 }
1530
1531 /****************************************************************************
1532 *
1533 * The next functions belong to the address allocator for the dma_ops
1534 * interface functions.
1535 *
1536 ****************************************************************************/
1537
1538
1539 static unsigned long dma_ops_alloc_iova(struct device *dev,
1540 struct dma_ops_domain *dma_dom,
1541 unsigned int pages, u64 dma_mask)
1542 {
1543 unsigned long pfn = 0;
1544
1545 pages = __roundup_pow_of_two(pages);
1546
1547 if (dma_mask > DMA_BIT_MASK(32))
1548 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1549 IOVA_PFN(DMA_BIT_MASK(32)), false);
1550
1551 if (!pfn)
1552 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1553 IOVA_PFN(dma_mask), true);
1554
1555 return (pfn << PAGE_SHIFT);
1556 }
1557
1558 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1559 unsigned long address,
1560 unsigned int pages)
1561 {
1562 pages = __roundup_pow_of_two(pages);
1563 address >>= PAGE_SHIFT;
1564
1565 free_iova_fast(&dma_dom->iovad, address, pages);
1566 }
1567
1568 /****************************************************************************
1569 *
1570 * The next functions belong to the domain allocation. A domain is
1571 * allocated for every IOMMU as the default domain. If device isolation
1572 * is enabled, every device get its own domain. The most important thing
1573 * about domains is the page table mapping the DMA address space they
1574 * contain.
1575 *
1576 ****************************************************************************/
1577
1578 /*
1579 * This function adds a protection domain to the global protection domain list
1580 */
1581 static void add_domain_to_list(struct protection_domain *domain)
1582 {
1583 unsigned long flags;
1584
1585 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1586 list_add(&domain->list, &amd_iommu_pd_list);
1587 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1588 }
1589
1590 /*
1591 * This function removes a protection domain to the global
1592 * protection domain list
1593 */
1594 static void del_domain_from_list(struct protection_domain *domain)
1595 {
1596 unsigned long flags;
1597
1598 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1599 list_del(&domain->list);
1600 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1601 }
1602
1603 static u16 domain_id_alloc(void)
1604 {
1605 int id;
1606
1607 spin_lock(&pd_bitmap_lock);
1608 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1609 BUG_ON(id == 0);
1610 if (id > 0 && id < MAX_DOMAIN_ID)
1611 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1612 else
1613 id = 0;
1614 spin_unlock(&pd_bitmap_lock);
1615
1616 return id;
1617 }
1618
1619 static void domain_id_free(int id)
1620 {
1621 spin_lock(&pd_bitmap_lock);
1622 if (id > 0 && id < MAX_DOMAIN_ID)
1623 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1624 spin_unlock(&pd_bitmap_lock);
1625 }
1626
1627 #define DEFINE_FREE_PT_FN(LVL, FN) \
1628 static void free_pt_##LVL (unsigned long __pt) \
1629 { \
1630 unsigned long p; \
1631 u64 *pt; \
1632 int i; \
1633 \
1634 pt = (u64 *)__pt; \
1635 \
1636 for (i = 0; i < 512; ++i) { \
1637 /* PTE present? */ \
1638 if (!IOMMU_PTE_PRESENT(pt[i])) \
1639 continue; \
1640 \
1641 /* Large PTE? */ \
1642 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1643 PM_PTE_LEVEL(pt[i]) == 7) \
1644 continue; \
1645 \
1646 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1647 FN(p); \
1648 } \
1649 free_page((unsigned long)pt); \
1650 }
1651
1652 DEFINE_FREE_PT_FN(l2, free_page)
1653 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1654 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1655 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1656 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1657
1658 static void free_pagetable(struct protection_domain *domain)
1659 {
1660 unsigned long root = (unsigned long)domain->pt_root;
1661
1662 switch (domain->mode) {
1663 case PAGE_MODE_NONE:
1664 break;
1665 case PAGE_MODE_1_LEVEL:
1666 free_page(root);
1667 break;
1668 case PAGE_MODE_2_LEVEL:
1669 free_pt_l2(root);
1670 break;
1671 case PAGE_MODE_3_LEVEL:
1672 free_pt_l3(root);
1673 break;
1674 case PAGE_MODE_4_LEVEL:
1675 free_pt_l4(root);
1676 break;
1677 case PAGE_MODE_5_LEVEL:
1678 free_pt_l5(root);
1679 break;
1680 case PAGE_MODE_6_LEVEL:
1681 free_pt_l6(root);
1682 break;
1683 default:
1684 BUG();
1685 }
1686 }
1687
1688 static void free_gcr3_tbl_level1(u64 *tbl)
1689 {
1690 u64 *ptr;
1691 int i;
1692
1693 for (i = 0; i < 512; ++i) {
1694 if (!(tbl[i] & GCR3_VALID))
1695 continue;
1696
1697 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1698
1699 free_page((unsigned long)ptr);
1700 }
1701 }
1702
1703 static void free_gcr3_tbl_level2(u64 *tbl)
1704 {
1705 u64 *ptr;
1706 int i;
1707
1708 for (i = 0; i < 512; ++i) {
1709 if (!(tbl[i] & GCR3_VALID))
1710 continue;
1711
1712 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1713
1714 free_gcr3_tbl_level1(ptr);
1715 }
1716 }
1717
1718 static void free_gcr3_table(struct protection_domain *domain)
1719 {
1720 if (domain->glx == 2)
1721 free_gcr3_tbl_level2(domain->gcr3_tbl);
1722 else if (domain->glx == 1)
1723 free_gcr3_tbl_level1(domain->gcr3_tbl);
1724 else
1725 BUG_ON(domain->glx != 0);
1726
1727 free_page((unsigned long)domain->gcr3_tbl);
1728 }
1729
1730 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1731 {
1732 domain_flush_tlb(&dom->domain);
1733 domain_flush_complete(&dom->domain);
1734 }
1735
1736 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1737 {
1738 struct dma_ops_domain *dom;
1739
1740 dom = container_of(iovad, struct dma_ops_domain, iovad);
1741
1742 dma_ops_domain_flush_tlb(dom);
1743 }
1744
1745 /*
1746 * Free a domain, only used if something went wrong in the
1747 * allocation path and we need to free an already allocated page table
1748 */
1749 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1750 {
1751 if (!dom)
1752 return;
1753
1754 del_domain_from_list(&dom->domain);
1755
1756 put_iova_domain(&dom->iovad);
1757
1758 free_pagetable(&dom->domain);
1759
1760 if (dom->domain.id)
1761 domain_id_free(dom->domain.id);
1762
1763 kfree(dom);
1764 }
1765
1766 /*
1767 * Allocates a new protection domain usable for the dma_ops functions.
1768 * It also initializes the page table and the address allocator data
1769 * structures required for the dma_ops interface
1770 */
1771 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1772 {
1773 struct dma_ops_domain *dma_dom;
1774
1775 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1776 if (!dma_dom)
1777 return NULL;
1778
1779 if (protection_domain_init(&dma_dom->domain))
1780 goto free_dma_dom;
1781
1782 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1783 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1784 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1785 if (!dma_dom->domain.pt_root)
1786 goto free_dma_dom;
1787
1788 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1789
1790 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1791 goto free_dma_dom;
1792
1793 /* Initialize reserved ranges */
1794 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1795
1796 add_domain_to_list(&dma_dom->domain);
1797
1798 return dma_dom;
1799
1800 free_dma_dom:
1801 dma_ops_domain_free(dma_dom);
1802
1803 return NULL;
1804 }
1805
1806 /*
1807 * little helper function to check whether a given protection domain is a
1808 * dma_ops domain
1809 */
1810 static bool dma_ops_domain(struct protection_domain *domain)
1811 {
1812 return domain->flags & PD_DMA_OPS_MASK;
1813 }
1814
1815 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1816 bool ats, bool ppr)
1817 {
1818 u64 pte_root = 0;
1819 u64 flags = 0;
1820
1821 if (domain->mode != PAGE_MODE_NONE)
1822 pte_root = iommu_virt_to_phys(domain->pt_root);
1823
1824 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1825 << DEV_ENTRY_MODE_SHIFT;
1826 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1827
1828 flags = amd_iommu_dev_table[devid].data[1];
1829
1830 if (ats)
1831 flags |= DTE_FLAG_IOTLB;
1832
1833 if (ppr) {
1834 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1835
1836 if (iommu_feature(iommu, FEATURE_EPHSUP))
1837 pte_root |= 1ULL << DEV_ENTRY_PPR;
1838 }
1839
1840 if (domain->flags & PD_IOMMUV2_MASK) {
1841 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1842 u64 glx = domain->glx;
1843 u64 tmp;
1844
1845 pte_root |= DTE_FLAG_GV;
1846 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1847
1848 /* First mask out possible old values for GCR3 table */
1849 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1850 flags &= ~tmp;
1851
1852 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1853 flags &= ~tmp;
1854
1855 /* Encode GCR3 table into DTE */
1856 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1857 pte_root |= tmp;
1858
1859 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1860 flags |= tmp;
1861
1862 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1863 flags |= tmp;
1864 }
1865
1866 flags &= ~DEV_DOMID_MASK;
1867 flags |= domain->id;
1868
1869 amd_iommu_dev_table[devid].data[1] = flags;
1870 amd_iommu_dev_table[devid].data[0] = pte_root;
1871 }
1872
1873 static void clear_dte_entry(u16 devid)
1874 {
1875 /* remove entry from the device table seen by the hardware */
1876 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1877 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1878
1879 amd_iommu_apply_erratum_63(devid);
1880 }
1881
1882 static void do_attach(struct iommu_dev_data *dev_data,
1883 struct protection_domain *domain)
1884 {
1885 struct amd_iommu *iommu;
1886 u16 alias;
1887 bool ats;
1888
1889 iommu = amd_iommu_rlookup_table[dev_data->devid];
1890 alias = dev_data->alias;
1891 ats = dev_data->ats.enabled;
1892
1893 /* Update data structures */
1894 dev_data->domain = domain;
1895 list_add(&dev_data->list, &domain->dev_list);
1896
1897 /* Do reference counting */
1898 domain->dev_iommu[iommu->index] += 1;
1899 domain->dev_cnt += 1;
1900
1901 /* Update device table */
1902 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1903 if (alias != dev_data->devid)
1904 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1905
1906 device_flush_dte(dev_data);
1907 }
1908
1909 static void do_detach(struct iommu_dev_data *dev_data)
1910 {
1911 struct amd_iommu *iommu;
1912 u16 alias;
1913
1914 /*
1915 * First check if the device is still attached. It might already
1916 * be detached from its domain because the generic
1917 * iommu_detach_group code detached it and we try again here in
1918 * our alias handling.
1919 */
1920 if (!dev_data->domain)
1921 return;
1922
1923 iommu = amd_iommu_rlookup_table[dev_data->devid];
1924 alias = dev_data->alias;
1925
1926 /* decrease reference counters */
1927 dev_data->domain->dev_iommu[iommu->index] -= 1;
1928 dev_data->domain->dev_cnt -= 1;
1929
1930 /* Update data structures */
1931 dev_data->domain = NULL;
1932 list_del(&dev_data->list);
1933 clear_dte_entry(dev_data->devid);
1934 if (alias != dev_data->devid)
1935 clear_dte_entry(alias);
1936
1937 /* Flush the DTE entry */
1938 device_flush_dte(dev_data);
1939 }
1940
1941 /*
1942 * If a device is not yet associated with a domain, this function does
1943 * assigns it visible for the hardware
1944 */
1945 static int __attach_device(struct iommu_dev_data *dev_data,
1946 struct protection_domain *domain)
1947 {
1948 int ret;
1949
1950 /*
1951 * Must be called with IRQs disabled. Warn here to detect early
1952 * when its not.
1953 */
1954 WARN_ON(!irqs_disabled());
1955
1956 /* lock domain */
1957 spin_lock(&domain->lock);
1958
1959 ret = -EBUSY;
1960 if (dev_data->domain != NULL)
1961 goto out_unlock;
1962
1963 /* Attach alias group root */
1964 do_attach(dev_data, domain);
1965
1966 ret = 0;
1967
1968 out_unlock:
1969
1970 /* ready */
1971 spin_unlock(&domain->lock);
1972
1973 return ret;
1974 }
1975
1976
1977 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1978 {
1979 pci_disable_ats(pdev);
1980 pci_disable_pri(pdev);
1981 pci_disable_pasid(pdev);
1982 }
1983
1984 /* FIXME: Change generic reset-function to do the same */
1985 static int pri_reset_while_enabled(struct pci_dev *pdev)
1986 {
1987 u16 control;
1988 int pos;
1989
1990 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1991 if (!pos)
1992 return -EINVAL;
1993
1994 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1995 control |= PCI_PRI_CTRL_RESET;
1996 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1997
1998 return 0;
1999 }
2000
2001 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2002 {
2003 bool reset_enable;
2004 int reqs, ret;
2005
2006 /* FIXME: Hardcode number of outstanding requests for now */
2007 reqs = 32;
2008 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2009 reqs = 1;
2010 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2011
2012 /* Only allow access to user-accessible pages */
2013 ret = pci_enable_pasid(pdev, 0);
2014 if (ret)
2015 goto out_err;
2016
2017 /* First reset the PRI state of the device */
2018 ret = pci_reset_pri(pdev);
2019 if (ret)
2020 goto out_err;
2021
2022 /* Enable PRI */
2023 ret = pci_enable_pri(pdev, reqs);
2024 if (ret)
2025 goto out_err;
2026
2027 if (reset_enable) {
2028 ret = pri_reset_while_enabled(pdev);
2029 if (ret)
2030 goto out_err;
2031 }
2032
2033 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2034 if (ret)
2035 goto out_err;
2036
2037 return 0;
2038
2039 out_err:
2040 pci_disable_pri(pdev);
2041 pci_disable_pasid(pdev);
2042
2043 return ret;
2044 }
2045
2046 /* FIXME: Move this to PCI code */
2047 #define PCI_PRI_TLP_OFF (1 << 15)
2048
2049 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2050 {
2051 u16 status;
2052 int pos;
2053
2054 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2055 if (!pos)
2056 return false;
2057
2058 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2059
2060 return (status & PCI_PRI_TLP_OFF) ? true : false;
2061 }
2062
2063 /*
2064 * If a device is not yet associated with a domain, this function
2065 * assigns it visible for the hardware
2066 */
2067 static int attach_device(struct device *dev,
2068 struct protection_domain *domain)
2069 {
2070 struct pci_dev *pdev;
2071 struct iommu_dev_data *dev_data;
2072 unsigned long flags;
2073 int ret;
2074
2075 dev_data = get_dev_data(dev);
2076
2077 if (!dev_is_pci(dev))
2078 goto skip_ats_check;
2079
2080 pdev = to_pci_dev(dev);
2081 if (domain->flags & PD_IOMMUV2_MASK) {
2082 if (!dev_data->passthrough)
2083 return -EINVAL;
2084
2085 if (dev_data->iommu_v2) {
2086 if (pdev_iommuv2_enable(pdev) != 0)
2087 return -EINVAL;
2088
2089 dev_data->ats.enabled = true;
2090 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2091 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2092 }
2093 } else if (amd_iommu_iotlb_sup &&
2094 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2095 dev_data->ats.enabled = true;
2096 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2097 }
2098
2099 skip_ats_check:
2100 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2101 ret = __attach_device(dev_data, domain);
2102 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2103
2104 /*
2105 * We might boot into a crash-kernel here. The crashed kernel
2106 * left the caches in the IOMMU dirty. So we have to flush
2107 * here to evict all dirty stuff.
2108 */
2109 domain_flush_tlb_pde(domain);
2110
2111 return ret;
2112 }
2113
2114 /*
2115 * Removes a device from a protection domain (unlocked)
2116 */
2117 static void __detach_device(struct iommu_dev_data *dev_data)
2118 {
2119 struct protection_domain *domain;
2120
2121 /*
2122 * Must be called with IRQs disabled. Warn here to detect early
2123 * when its not.
2124 */
2125 WARN_ON(!irqs_disabled());
2126
2127 if (WARN_ON(!dev_data->domain))
2128 return;
2129
2130 domain = dev_data->domain;
2131
2132 spin_lock(&domain->lock);
2133
2134 do_detach(dev_data);
2135
2136 spin_unlock(&domain->lock);
2137 }
2138
2139 /*
2140 * Removes a device from a protection domain (with devtable_lock held)
2141 */
2142 static void detach_device(struct device *dev)
2143 {
2144 struct protection_domain *domain;
2145 struct iommu_dev_data *dev_data;
2146 unsigned long flags;
2147
2148 dev_data = get_dev_data(dev);
2149 domain = dev_data->domain;
2150
2151 /* lock device table */
2152 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2153 __detach_device(dev_data);
2154 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2155
2156 if (!dev_is_pci(dev))
2157 return;
2158
2159 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2160 pdev_iommuv2_disable(to_pci_dev(dev));
2161 else if (dev_data->ats.enabled)
2162 pci_disable_ats(to_pci_dev(dev));
2163
2164 dev_data->ats.enabled = false;
2165 }
2166
2167 static int amd_iommu_add_device(struct device *dev)
2168 {
2169 struct iommu_dev_data *dev_data;
2170 struct iommu_domain *domain;
2171 struct amd_iommu *iommu;
2172 int ret, devid;
2173
2174 if (!check_device(dev) || get_dev_data(dev))
2175 return 0;
2176
2177 devid = get_device_id(dev);
2178 if (devid < 0)
2179 return devid;
2180
2181 iommu = amd_iommu_rlookup_table[devid];
2182
2183 ret = iommu_init_device(dev);
2184 if (ret) {
2185 if (ret != -ENOTSUPP)
2186 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2187 dev_name(dev));
2188
2189 iommu_ignore_device(dev);
2190 dev->dma_ops = &dma_direct_ops;
2191 goto out;
2192 }
2193 init_iommu_group(dev);
2194
2195 dev_data = get_dev_data(dev);
2196
2197 BUG_ON(!dev_data);
2198
2199 if (iommu_pass_through || dev_data->iommu_v2)
2200 iommu_request_dm_for_dev(dev);
2201
2202 /* Domains are initialized for this device - have a look what we ended up with */
2203 domain = iommu_get_domain_for_dev(dev);
2204 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2205 dev_data->passthrough = true;
2206 else
2207 dev->dma_ops = &amd_iommu_dma_ops;
2208
2209 out:
2210 iommu_completion_wait(iommu);
2211
2212 return 0;
2213 }
2214
2215 static void amd_iommu_remove_device(struct device *dev)
2216 {
2217 struct amd_iommu *iommu;
2218 int devid;
2219
2220 if (!check_device(dev))
2221 return;
2222
2223 devid = get_device_id(dev);
2224 if (devid < 0)
2225 return;
2226
2227 iommu = amd_iommu_rlookup_table[devid];
2228
2229 iommu_uninit_device(dev);
2230 iommu_completion_wait(iommu);
2231 }
2232
2233 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2234 {
2235 if (dev_is_pci(dev))
2236 return pci_device_group(dev);
2237
2238 return acpihid_device_group(dev);
2239 }
2240
2241 /*****************************************************************************
2242 *
2243 * The next functions belong to the dma_ops mapping/unmapping code.
2244 *
2245 *****************************************************************************/
2246
2247 /*
2248 * In the dma_ops path we only have the struct device. This function
2249 * finds the corresponding IOMMU, the protection domain and the
2250 * requestor id for a given device.
2251 * If the device is not yet associated with a domain this is also done
2252 * in this function.
2253 */
2254 static struct protection_domain *get_domain(struct device *dev)
2255 {
2256 struct protection_domain *domain;
2257 struct iommu_domain *io_domain;
2258
2259 if (!check_device(dev))
2260 return ERR_PTR(-EINVAL);
2261
2262 domain = get_dev_data(dev)->domain;
2263 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2264 get_dev_data(dev)->defer_attach = false;
2265 io_domain = iommu_get_domain_for_dev(dev);
2266 domain = to_pdomain(io_domain);
2267 attach_device(dev, domain);
2268 }
2269 if (domain == NULL)
2270 return ERR_PTR(-EBUSY);
2271
2272 if (!dma_ops_domain(domain))
2273 return ERR_PTR(-EBUSY);
2274
2275 return domain;
2276 }
2277
2278 static void update_device_table(struct protection_domain *domain)
2279 {
2280 struct iommu_dev_data *dev_data;
2281
2282 list_for_each_entry(dev_data, &domain->dev_list, list) {
2283 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2284 dev_data->iommu_v2);
2285
2286 if (dev_data->devid == dev_data->alias)
2287 continue;
2288
2289 /* There is an alias, update device table entry for it */
2290 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2291 dev_data->iommu_v2);
2292 }
2293 }
2294
2295 static void update_domain(struct protection_domain *domain)
2296 {
2297 if (!domain->updated)
2298 return;
2299
2300 update_device_table(domain);
2301
2302 domain_flush_devices(domain);
2303 domain_flush_tlb_pde(domain);
2304
2305 domain->updated = false;
2306 }
2307
2308 static int dir2prot(enum dma_data_direction direction)
2309 {
2310 if (direction == DMA_TO_DEVICE)
2311 return IOMMU_PROT_IR;
2312 else if (direction == DMA_FROM_DEVICE)
2313 return IOMMU_PROT_IW;
2314 else if (direction == DMA_BIDIRECTIONAL)
2315 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2316 else
2317 return 0;
2318 }
2319
2320 /*
2321 * This function contains common code for mapping of a physically
2322 * contiguous memory region into DMA address space. It is used by all
2323 * mapping functions provided with this IOMMU driver.
2324 * Must be called with the domain lock held.
2325 */
2326 static dma_addr_t __map_single(struct device *dev,
2327 struct dma_ops_domain *dma_dom,
2328 phys_addr_t paddr,
2329 size_t size,
2330 enum dma_data_direction direction,
2331 u64 dma_mask)
2332 {
2333 dma_addr_t offset = paddr & ~PAGE_MASK;
2334 dma_addr_t address, start, ret;
2335 unsigned int pages;
2336 int prot = 0;
2337 int i;
2338
2339 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2340 paddr &= PAGE_MASK;
2341
2342 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2343 if (address == AMD_IOMMU_MAPPING_ERROR)
2344 goto out;
2345
2346 prot = dir2prot(direction);
2347
2348 start = address;
2349 for (i = 0; i < pages; ++i) {
2350 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2351 PAGE_SIZE, prot, GFP_ATOMIC);
2352 if (ret)
2353 goto out_unmap;
2354
2355 paddr += PAGE_SIZE;
2356 start += PAGE_SIZE;
2357 }
2358 address += offset;
2359
2360 if (unlikely(amd_iommu_np_cache)) {
2361 domain_flush_pages(&dma_dom->domain, address, size);
2362 domain_flush_complete(&dma_dom->domain);
2363 }
2364
2365 out:
2366 return address;
2367
2368 out_unmap:
2369
2370 for (--i; i >= 0; --i) {
2371 start -= PAGE_SIZE;
2372 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2373 }
2374
2375 domain_flush_tlb(&dma_dom->domain);
2376 domain_flush_complete(&dma_dom->domain);
2377
2378 dma_ops_free_iova(dma_dom, address, pages);
2379
2380 return AMD_IOMMU_MAPPING_ERROR;
2381 }
2382
2383 /*
2384 * Does the reverse of the __map_single function. Must be called with
2385 * the domain lock held too
2386 */
2387 static void __unmap_single(struct dma_ops_domain *dma_dom,
2388 dma_addr_t dma_addr,
2389 size_t size,
2390 int dir)
2391 {
2392 dma_addr_t i, start;
2393 unsigned int pages;
2394
2395 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2396 dma_addr &= PAGE_MASK;
2397 start = dma_addr;
2398
2399 for (i = 0; i < pages; ++i) {
2400 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2401 start += PAGE_SIZE;
2402 }
2403
2404 if (amd_iommu_unmap_flush) {
2405 dma_ops_free_iova(dma_dom, dma_addr, pages);
2406 domain_flush_tlb(&dma_dom->domain);
2407 domain_flush_complete(&dma_dom->domain);
2408 } else {
2409 pages = __roundup_pow_of_two(pages);
2410 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2411 }
2412 }
2413
2414 /*
2415 * The exported map_single function for dma_ops.
2416 */
2417 static dma_addr_t map_page(struct device *dev, struct page *page,
2418 unsigned long offset, size_t size,
2419 enum dma_data_direction dir,
2420 unsigned long attrs)
2421 {
2422 phys_addr_t paddr = page_to_phys(page) + offset;
2423 struct protection_domain *domain;
2424 struct dma_ops_domain *dma_dom;
2425 u64 dma_mask;
2426
2427 domain = get_domain(dev);
2428 if (PTR_ERR(domain) == -EINVAL)
2429 return (dma_addr_t)paddr;
2430 else if (IS_ERR(domain))
2431 return AMD_IOMMU_MAPPING_ERROR;
2432
2433 dma_mask = *dev->dma_mask;
2434 dma_dom = to_dma_ops_domain(domain);
2435
2436 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2437 }
2438
2439 /*
2440 * The exported unmap_single function for dma_ops.
2441 */
2442 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2443 enum dma_data_direction dir, unsigned long attrs)
2444 {
2445 struct protection_domain *domain;
2446 struct dma_ops_domain *dma_dom;
2447
2448 domain = get_domain(dev);
2449 if (IS_ERR(domain))
2450 return;
2451
2452 dma_dom = to_dma_ops_domain(domain);
2453
2454 __unmap_single(dma_dom, dma_addr, size, dir);
2455 }
2456
2457 static int sg_num_pages(struct device *dev,
2458 struct scatterlist *sglist,
2459 int nelems)
2460 {
2461 unsigned long mask, boundary_size;
2462 struct scatterlist *s;
2463 int i, npages = 0;
2464
2465 mask = dma_get_seg_boundary(dev);
2466 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2467 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2468
2469 for_each_sg(sglist, s, nelems, i) {
2470 int p, n;
2471
2472 s->dma_address = npages << PAGE_SHIFT;
2473 p = npages % boundary_size;
2474 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2475 if (p + n > boundary_size)
2476 npages += boundary_size - p;
2477 npages += n;
2478 }
2479
2480 return npages;
2481 }
2482
2483 /*
2484 * The exported map_sg function for dma_ops (handles scatter-gather
2485 * lists).
2486 */
2487 static int map_sg(struct device *dev, struct scatterlist *sglist,
2488 int nelems, enum dma_data_direction direction,
2489 unsigned long attrs)
2490 {
2491 int mapped_pages = 0, npages = 0, prot = 0, i;
2492 struct protection_domain *domain;
2493 struct dma_ops_domain *dma_dom;
2494 struct scatterlist *s;
2495 unsigned long address;
2496 u64 dma_mask;
2497
2498 domain = get_domain(dev);
2499 if (IS_ERR(domain))
2500 return 0;
2501
2502 dma_dom = to_dma_ops_domain(domain);
2503 dma_mask = *dev->dma_mask;
2504
2505 npages = sg_num_pages(dev, sglist, nelems);
2506
2507 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2508 if (address == AMD_IOMMU_MAPPING_ERROR)
2509 goto out_err;
2510
2511 prot = dir2prot(direction);
2512
2513 /* Map all sg entries */
2514 for_each_sg(sglist, s, nelems, i) {
2515 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2516
2517 for (j = 0; j < pages; ++j) {
2518 unsigned long bus_addr, phys_addr;
2519 int ret;
2520
2521 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2522 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2523 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2524 if (ret)
2525 goto out_unmap;
2526
2527 mapped_pages += 1;
2528 }
2529 }
2530
2531 /* Everything is mapped - write the right values into s->dma_address */
2532 for_each_sg(sglist, s, nelems, i) {
2533 s->dma_address += address + s->offset;
2534 s->dma_length = s->length;
2535 }
2536
2537 return nelems;
2538
2539 out_unmap:
2540 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2541 dev_name(dev), npages);
2542
2543 for_each_sg(sglist, s, nelems, i) {
2544 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2545
2546 for (j = 0; j < pages; ++j) {
2547 unsigned long bus_addr;
2548
2549 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2550 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2551
2552 if (--mapped_pages)
2553 goto out_free_iova;
2554 }
2555 }
2556
2557 out_free_iova:
2558 free_iova_fast(&dma_dom->iovad, address, npages);
2559
2560 out_err:
2561 return 0;
2562 }
2563
2564 /*
2565 * The exported map_sg function for dma_ops (handles scatter-gather
2566 * lists).
2567 */
2568 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2569 int nelems, enum dma_data_direction dir,
2570 unsigned long attrs)
2571 {
2572 struct protection_domain *domain;
2573 struct dma_ops_domain *dma_dom;
2574 unsigned long startaddr;
2575 int npages = 2;
2576
2577 domain = get_domain(dev);
2578 if (IS_ERR(domain))
2579 return;
2580
2581 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2582 dma_dom = to_dma_ops_domain(domain);
2583 npages = sg_num_pages(dev, sglist, nelems);
2584
2585 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2586 }
2587
2588 /*
2589 * The exported alloc_coherent function for dma_ops.
2590 */
2591 static void *alloc_coherent(struct device *dev, size_t size,
2592 dma_addr_t *dma_addr, gfp_t flag,
2593 unsigned long attrs)
2594 {
2595 u64 dma_mask = dev->coherent_dma_mask;
2596 struct protection_domain *domain = get_domain(dev);
2597 bool is_direct = false;
2598 void *virt_addr;
2599
2600 if (IS_ERR(domain)) {
2601 if (PTR_ERR(domain) != -EINVAL)
2602 return NULL;
2603 is_direct = true;
2604 }
2605
2606 virt_addr = dma_direct_alloc(dev, size, dma_addr, flag, attrs);
2607 if (!virt_addr || is_direct)
2608 return virt_addr;
2609
2610 if (!dma_mask)
2611 dma_mask = *dev->dma_mask;
2612
2613 *dma_addr = __map_single(dev, to_dma_ops_domain(domain),
2614 virt_to_phys(virt_addr), PAGE_ALIGN(size),
2615 DMA_BIDIRECTIONAL, dma_mask);
2616 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2617 goto out_free;
2618 return virt_addr;
2619
2620 out_free:
2621 dma_direct_free(dev, size, virt_addr, *dma_addr, attrs);
2622 return NULL;
2623 }
2624
2625 /*
2626 * The exported free_coherent function for dma_ops.
2627 */
2628 static void free_coherent(struct device *dev, size_t size,
2629 void *virt_addr, dma_addr_t dma_addr,
2630 unsigned long attrs)
2631 {
2632 struct protection_domain *domain = get_domain(dev);
2633
2634 size = PAGE_ALIGN(size);
2635
2636 if (!IS_ERR(domain)) {
2637 struct dma_ops_domain *dma_dom = to_dma_ops_domain(domain);
2638
2639 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2640 }
2641
2642 dma_direct_free(dev, size, virt_addr, dma_addr, attrs);
2643 }
2644
2645 /*
2646 * This function is called by the DMA layer to find out if we can handle a
2647 * particular device. It is part of the dma_ops.
2648 */
2649 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2650 {
2651 if (!dma_direct_supported(dev, mask))
2652 return 0;
2653 return check_device(dev);
2654 }
2655
2656 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2657 {
2658 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2659 }
2660
2661 static const struct dma_map_ops amd_iommu_dma_ops = {
2662 .alloc = alloc_coherent,
2663 .free = free_coherent,
2664 .map_page = map_page,
2665 .unmap_page = unmap_page,
2666 .map_sg = map_sg,
2667 .unmap_sg = unmap_sg,
2668 .dma_supported = amd_iommu_dma_supported,
2669 .mapping_error = amd_iommu_mapping_error,
2670 };
2671
2672 static int init_reserved_iova_ranges(void)
2673 {
2674 struct pci_dev *pdev = NULL;
2675 struct iova *val;
2676
2677 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2678
2679 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2680 &reserved_rbtree_key);
2681
2682 /* MSI memory range */
2683 val = reserve_iova(&reserved_iova_ranges,
2684 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2685 if (!val) {
2686 pr_err("Reserving MSI range failed\n");
2687 return -ENOMEM;
2688 }
2689
2690 /* HT memory range */
2691 val = reserve_iova(&reserved_iova_ranges,
2692 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2693 if (!val) {
2694 pr_err("Reserving HT range failed\n");
2695 return -ENOMEM;
2696 }
2697
2698 /*
2699 * Memory used for PCI resources
2700 * FIXME: Check whether we can reserve the PCI-hole completly
2701 */
2702 for_each_pci_dev(pdev) {
2703 int i;
2704
2705 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2706 struct resource *r = &pdev->resource[i];
2707
2708 if (!(r->flags & IORESOURCE_MEM))
2709 continue;
2710
2711 val = reserve_iova(&reserved_iova_ranges,
2712 IOVA_PFN(r->start),
2713 IOVA_PFN(r->end));
2714 if (!val) {
2715 pr_err("Reserve pci-resource range failed\n");
2716 return -ENOMEM;
2717 }
2718 }
2719 }
2720
2721 return 0;
2722 }
2723
2724 int __init amd_iommu_init_api(void)
2725 {
2726 int ret, err = 0;
2727
2728 ret = iova_cache_get();
2729 if (ret)
2730 return ret;
2731
2732 ret = init_reserved_iova_ranges();
2733 if (ret)
2734 return ret;
2735
2736 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2737 if (err)
2738 return err;
2739 #ifdef CONFIG_ARM_AMBA
2740 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2741 if (err)
2742 return err;
2743 #endif
2744 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2745 if (err)
2746 return err;
2747
2748 return 0;
2749 }
2750
2751 int __init amd_iommu_init_dma_ops(void)
2752 {
2753 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2754 iommu_detected = 1;
2755
2756 /*
2757 * In case we don't initialize SWIOTLB (actually the common case
2758 * when AMD IOMMU is enabled and SME is not active), make sure there
2759 * are global dma_ops set as a fall-back for devices not handled by
2760 * this driver (for example non-PCI devices). When SME is active,
2761 * make sure that swiotlb variable remains set so the global dma_ops
2762 * continue to be SWIOTLB.
2763 */
2764 if (!swiotlb)
2765 dma_ops = &dma_direct_ops;
2766
2767 if (amd_iommu_unmap_flush)
2768 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2769 else
2770 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2771
2772 return 0;
2773
2774 }
2775
2776 /*****************************************************************************
2777 *
2778 * The following functions belong to the exported interface of AMD IOMMU
2779 *
2780 * This interface allows access to lower level functions of the IOMMU
2781 * like protection domain handling and assignement of devices to domains
2782 * which is not possible with the dma_ops interface.
2783 *
2784 *****************************************************************************/
2785
2786 static void cleanup_domain(struct protection_domain *domain)
2787 {
2788 struct iommu_dev_data *entry;
2789 unsigned long flags;
2790
2791 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2792
2793 while (!list_empty(&domain->dev_list)) {
2794 entry = list_first_entry(&domain->dev_list,
2795 struct iommu_dev_data, list);
2796 __detach_device(entry);
2797 }
2798
2799 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2800 }
2801
2802 static void protection_domain_free(struct protection_domain *domain)
2803 {
2804 if (!domain)
2805 return;
2806
2807 del_domain_from_list(domain);
2808
2809 if (domain->id)
2810 domain_id_free(domain->id);
2811
2812 kfree(domain);
2813 }
2814
2815 static int protection_domain_init(struct protection_domain *domain)
2816 {
2817 spin_lock_init(&domain->lock);
2818 mutex_init(&domain->api_lock);
2819 domain->id = domain_id_alloc();
2820 if (!domain->id)
2821 return -ENOMEM;
2822 INIT_LIST_HEAD(&domain->dev_list);
2823
2824 return 0;
2825 }
2826
2827 static struct protection_domain *protection_domain_alloc(void)
2828 {
2829 struct protection_domain *domain;
2830
2831 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2832 if (!domain)
2833 return NULL;
2834
2835 if (protection_domain_init(domain))
2836 goto out_err;
2837
2838 add_domain_to_list(domain);
2839
2840 return domain;
2841
2842 out_err:
2843 kfree(domain);
2844
2845 return NULL;
2846 }
2847
2848 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2849 {
2850 struct protection_domain *pdomain;
2851 struct dma_ops_domain *dma_domain;
2852
2853 switch (type) {
2854 case IOMMU_DOMAIN_UNMANAGED:
2855 pdomain = protection_domain_alloc();
2856 if (!pdomain)
2857 return NULL;
2858
2859 pdomain->mode = PAGE_MODE_3_LEVEL;
2860 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2861 if (!pdomain->pt_root) {
2862 protection_domain_free(pdomain);
2863 return NULL;
2864 }
2865
2866 pdomain->domain.geometry.aperture_start = 0;
2867 pdomain->domain.geometry.aperture_end = ~0ULL;
2868 pdomain->domain.geometry.force_aperture = true;
2869
2870 break;
2871 case IOMMU_DOMAIN_DMA:
2872 dma_domain = dma_ops_domain_alloc();
2873 if (!dma_domain) {
2874 pr_err("AMD-Vi: Failed to allocate\n");
2875 return NULL;
2876 }
2877 pdomain = &dma_domain->domain;
2878 break;
2879 case IOMMU_DOMAIN_IDENTITY:
2880 pdomain = protection_domain_alloc();
2881 if (!pdomain)
2882 return NULL;
2883
2884 pdomain->mode = PAGE_MODE_NONE;
2885 break;
2886 default:
2887 return NULL;
2888 }
2889
2890 return &pdomain->domain;
2891 }
2892
2893 static void amd_iommu_domain_free(struct iommu_domain *dom)
2894 {
2895 struct protection_domain *domain;
2896 struct dma_ops_domain *dma_dom;
2897
2898 domain = to_pdomain(dom);
2899
2900 if (domain->dev_cnt > 0)
2901 cleanup_domain(domain);
2902
2903 BUG_ON(domain->dev_cnt != 0);
2904
2905 if (!dom)
2906 return;
2907
2908 switch (dom->type) {
2909 case IOMMU_DOMAIN_DMA:
2910 /* Now release the domain */
2911 dma_dom = to_dma_ops_domain(domain);
2912 dma_ops_domain_free(dma_dom);
2913 break;
2914 default:
2915 if (domain->mode != PAGE_MODE_NONE)
2916 free_pagetable(domain);
2917
2918 if (domain->flags & PD_IOMMUV2_MASK)
2919 free_gcr3_table(domain);
2920
2921 protection_domain_free(domain);
2922 break;
2923 }
2924 }
2925
2926 static void amd_iommu_detach_device(struct iommu_domain *dom,
2927 struct device *dev)
2928 {
2929 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2930 struct amd_iommu *iommu;
2931 int devid;
2932
2933 if (!check_device(dev))
2934 return;
2935
2936 devid = get_device_id(dev);
2937 if (devid < 0)
2938 return;
2939
2940 if (dev_data->domain != NULL)
2941 detach_device(dev);
2942
2943 iommu = amd_iommu_rlookup_table[devid];
2944 if (!iommu)
2945 return;
2946
2947 #ifdef CONFIG_IRQ_REMAP
2948 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2949 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2950 dev_data->use_vapic = 0;
2951 #endif
2952
2953 iommu_completion_wait(iommu);
2954 }
2955
2956 static int amd_iommu_attach_device(struct iommu_domain *dom,
2957 struct device *dev)
2958 {
2959 struct protection_domain *domain = to_pdomain(dom);
2960 struct iommu_dev_data *dev_data;
2961 struct amd_iommu *iommu;
2962 int ret;
2963
2964 if (!check_device(dev))
2965 return -EINVAL;
2966
2967 dev_data = dev->archdata.iommu;
2968
2969 iommu = amd_iommu_rlookup_table[dev_data->devid];
2970 if (!iommu)
2971 return -EINVAL;
2972
2973 if (dev_data->domain)
2974 detach_device(dev);
2975
2976 ret = attach_device(dev, domain);
2977
2978 #ifdef CONFIG_IRQ_REMAP
2979 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2980 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2981 dev_data->use_vapic = 1;
2982 else
2983 dev_data->use_vapic = 0;
2984 }
2985 #endif
2986
2987 iommu_completion_wait(iommu);
2988
2989 return ret;
2990 }
2991
2992 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2993 phys_addr_t paddr, size_t page_size, int iommu_prot)
2994 {
2995 struct protection_domain *domain = to_pdomain(dom);
2996 int prot = 0;
2997 int ret;
2998
2999 if (domain->mode == PAGE_MODE_NONE)
3000 return -EINVAL;
3001
3002 if (iommu_prot & IOMMU_READ)
3003 prot |= IOMMU_PROT_IR;
3004 if (iommu_prot & IOMMU_WRITE)
3005 prot |= IOMMU_PROT_IW;
3006
3007 mutex_lock(&domain->api_lock);
3008 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3009 mutex_unlock(&domain->api_lock);
3010
3011 return ret;
3012 }
3013
3014 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3015 size_t page_size)
3016 {
3017 struct protection_domain *domain = to_pdomain(dom);
3018 size_t unmap_size;
3019
3020 if (domain->mode == PAGE_MODE_NONE)
3021 return 0;
3022
3023 mutex_lock(&domain->api_lock);
3024 unmap_size = iommu_unmap_page(domain, iova, page_size);
3025 mutex_unlock(&domain->api_lock);
3026
3027 return unmap_size;
3028 }
3029
3030 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3031 dma_addr_t iova)
3032 {
3033 struct protection_domain *domain = to_pdomain(dom);
3034 unsigned long offset_mask, pte_pgsize;
3035 u64 *pte, __pte;
3036
3037 if (domain->mode == PAGE_MODE_NONE)
3038 return iova;
3039
3040 pte = fetch_pte(domain, iova, &pte_pgsize);
3041
3042 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3043 return 0;
3044
3045 offset_mask = pte_pgsize - 1;
3046 __pte = *pte & PM_ADDR_MASK;
3047
3048 return (__pte & ~offset_mask) | (iova & offset_mask);
3049 }
3050
3051 static bool amd_iommu_capable(enum iommu_cap cap)
3052 {
3053 switch (cap) {
3054 case IOMMU_CAP_CACHE_COHERENCY:
3055 return true;
3056 case IOMMU_CAP_INTR_REMAP:
3057 return (irq_remapping_enabled == 1);
3058 case IOMMU_CAP_NOEXEC:
3059 return false;
3060 }
3061
3062 return false;
3063 }
3064
3065 static void amd_iommu_get_resv_regions(struct device *dev,
3066 struct list_head *head)
3067 {
3068 struct iommu_resv_region *region;
3069 struct unity_map_entry *entry;
3070 int devid;
3071
3072 devid = get_device_id(dev);
3073 if (devid < 0)
3074 return;
3075
3076 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3077 size_t length;
3078 int prot = 0;
3079
3080 if (devid < entry->devid_start || devid > entry->devid_end)
3081 continue;
3082
3083 length = entry->address_end - entry->address_start;
3084 if (entry->prot & IOMMU_PROT_IR)
3085 prot |= IOMMU_READ;
3086 if (entry->prot & IOMMU_PROT_IW)
3087 prot |= IOMMU_WRITE;
3088
3089 region = iommu_alloc_resv_region(entry->address_start,
3090 length, prot,
3091 IOMMU_RESV_DIRECT);
3092 if (!region) {
3093 pr_err("Out of memory allocating dm-regions for %s\n",
3094 dev_name(dev));
3095 return;
3096 }
3097 list_add_tail(&region->list, head);
3098 }
3099
3100 region = iommu_alloc_resv_region(MSI_RANGE_START,
3101 MSI_RANGE_END - MSI_RANGE_START + 1,
3102 0, IOMMU_RESV_MSI);
3103 if (!region)
3104 return;
3105 list_add_tail(&region->list, head);
3106
3107 region = iommu_alloc_resv_region(HT_RANGE_START,
3108 HT_RANGE_END - HT_RANGE_START + 1,
3109 0, IOMMU_RESV_RESERVED);
3110 if (!region)
3111 return;
3112 list_add_tail(&region->list, head);
3113 }
3114
3115 static void amd_iommu_put_resv_regions(struct device *dev,
3116 struct list_head *head)
3117 {
3118 struct iommu_resv_region *entry, *next;
3119
3120 list_for_each_entry_safe(entry, next, head, list)
3121 kfree(entry);
3122 }
3123
3124 static void amd_iommu_apply_resv_region(struct device *dev,
3125 struct iommu_domain *domain,
3126 struct iommu_resv_region *region)
3127 {
3128 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3129 unsigned long start, end;
3130
3131 start = IOVA_PFN(region->start);
3132 end = IOVA_PFN(region->start + region->length - 1);
3133
3134 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3135 }
3136
3137 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3138 struct device *dev)
3139 {
3140 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3141 return dev_data->defer_attach;
3142 }
3143
3144 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3145 {
3146 struct protection_domain *dom = to_pdomain(domain);
3147
3148 domain_flush_tlb_pde(dom);
3149 domain_flush_complete(dom);
3150 }
3151
3152 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3153 unsigned long iova, size_t size)
3154 {
3155 }
3156
3157 const struct iommu_ops amd_iommu_ops = {
3158 .capable = amd_iommu_capable,
3159 .domain_alloc = amd_iommu_domain_alloc,
3160 .domain_free = amd_iommu_domain_free,
3161 .attach_dev = amd_iommu_attach_device,
3162 .detach_dev = amd_iommu_detach_device,
3163 .map = amd_iommu_map,
3164 .unmap = amd_iommu_unmap,
3165 .map_sg = default_iommu_map_sg,
3166 .iova_to_phys = amd_iommu_iova_to_phys,
3167 .add_device = amd_iommu_add_device,
3168 .remove_device = amd_iommu_remove_device,
3169 .device_group = amd_iommu_device_group,
3170 .get_resv_regions = amd_iommu_get_resv_regions,
3171 .put_resv_regions = amd_iommu_put_resv_regions,
3172 .apply_resv_region = amd_iommu_apply_resv_region,
3173 .is_attach_deferred = amd_iommu_is_attach_deferred,
3174 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3175 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3176 .iotlb_range_add = amd_iommu_iotlb_range_add,
3177 .iotlb_sync = amd_iommu_flush_iotlb_all,
3178 };
3179
3180 /*****************************************************************************
3181 *
3182 * The next functions do a basic initialization of IOMMU for pass through
3183 * mode
3184 *
3185 * In passthrough mode the IOMMU is initialized and enabled but not used for
3186 * DMA-API translation.
3187 *
3188 *****************************************************************************/
3189
3190 /* IOMMUv2 specific functions */
3191 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3192 {
3193 return atomic_notifier_chain_register(&ppr_notifier, nb);
3194 }
3195 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3196
3197 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3198 {
3199 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3200 }
3201 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3202
3203 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3204 {
3205 struct protection_domain *domain = to_pdomain(dom);
3206 unsigned long flags;
3207
3208 spin_lock_irqsave(&domain->lock, flags);
3209
3210 /* Update data structure */
3211 domain->mode = PAGE_MODE_NONE;
3212 domain->updated = true;
3213
3214 /* Make changes visible to IOMMUs */
3215 update_domain(domain);
3216
3217 /* Page-table is not visible to IOMMU anymore, so free it */
3218 free_pagetable(domain);
3219
3220 spin_unlock_irqrestore(&domain->lock, flags);
3221 }
3222 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3223
3224 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3225 {
3226 struct protection_domain *domain = to_pdomain(dom);
3227 unsigned long flags;
3228 int levels, ret;
3229
3230 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3231 return -EINVAL;
3232
3233 /* Number of GCR3 table levels required */
3234 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3235 levels += 1;
3236
3237 if (levels > amd_iommu_max_glx_val)
3238 return -EINVAL;
3239
3240 spin_lock_irqsave(&domain->lock, flags);
3241
3242 /*
3243 * Save us all sanity checks whether devices already in the
3244 * domain support IOMMUv2. Just force that the domain has no
3245 * devices attached when it is switched into IOMMUv2 mode.
3246 */
3247 ret = -EBUSY;
3248 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3249 goto out;
3250
3251 ret = -ENOMEM;
3252 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3253 if (domain->gcr3_tbl == NULL)
3254 goto out;
3255
3256 domain->glx = levels;
3257 domain->flags |= PD_IOMMUV2_MASK;
3258 domain->updated = true;
3259
3260 update_domain(domain);
3261
3262 ret = 0;
3263
3264 out:
3265 spin_unlock_irqrestore(&domain->lock, flags);
3266
3267 return ret;
3268 }
3269 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3270
3271 static int __flush_pasid(struct protection_domain *domain, int pasid,
3272 u64 address, bool size)
3273 {
3274 struct iommu_dev_data *dev_data;
3275 struct iommu_cmd cmd;
3276 int i, ret;
3277
3278 if (!(domain->flags & PD_IOMMUV2_MASK))
3279 return -EINVAL;
3280
3281 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3282
3283 /*
3284 * IOMMU TLB needs to be flushed before Device TLB to
3285 * prevent device TLB refill from IOMMU TLB
3286 */
3287 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3288 if (domain->dev_iommu[i] == 0)
3289 continue;
3290
3291 ret = iommu_queue_command(amd_iommus[i], &cmd);
3292 if (ret != 0)
3293 goto out;
3294 }
3295
3296 /* Wait until IOMMU TLB flushes are complete */
3297 domain_flush_complete(domain);
3298
3299 /* Now flush device TLBs */
3300 list_for_each_entry(dev_data, &domain->dev_list, list) {
3301 struct amd_iommu *iommu;
3302 int qdep;
3303
3304 /*
3305 There might be non-IOMMUv2 capable devices in an IOMMUv2
3306 * domain.
3307 */
3308 if (!dev_data->ats.enabled)
3309 continue;
3310
3311 qdep = dev_data->ats.qdep;
3312 iommu = amd_iommu_rlookup_table[dev_data->devid];
3313
3314 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3315 qdep, address, size);
3316
3317 ret = iommu_queue_command(iommu, &cmd);
3318 if (ret != 0)
3319 goto out;
3320 }
3321
3322 /* Wait until all device TLBs are flushed */
3323 domain_flush_complete(domain);
3324
3325 ret = 0;
3326
3327 out:
3328
3329 return ret;
3330 }
3331
3332 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3333 u64 address)
3334 {
3335 return __flush_pasid(domain, pasid, address, false);
3336 }
3337
3338 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3339 u64 address)
3340 {
3341 struct protection_domain *domain = to_pdomain(dom);
3342 unsigned long flags;
3343 int ret;
3344
3345 spin_lock_irqsave(&domain->lock, flags);
3346 ret = __amd_iommu_flush_page(domain, pasid, address);
3347 spin_unlock_irqrestore(&domain->lock, flags);
3348
3349 return ret;
3350 }
3351 EXPORT_SYMBOL(amd_iommu_flush_page);
3352
3353 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3354 {
3355 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3356 true);
3357 }
3358
3359 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3360 {
3361 struct protection_domain *domain = to_pdomain(dom);
3362 unsigned long flags;
3363 int ret;
3364
3365 spin_lock_irqsave(&domain->lock, flags);
3366 ret = __amd_iommu_flush_tlb(domain, pasid);
3367 spin_unlock_irqrestore(&domain->lock, flags);
3368
3369 return ret;
3370 }
3371 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3372
3373 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3374 {
3375 int index;
3376 u64 *pte;
3377
3378 while (true) {
3379
3380 index = (pasid >> (9 * level)) & 0x1ff;
3381 pte = &root[index];
3382
3383 if (level == 0)
3384 break;
3385
3386 if (!(*pte & GCR3_VALID)) {
3387 if (!alloc)
3388 return NULL;
3389
3390 root = (void *)get_zeroed_page(GFP_ATOMIC);
3391 if (root == NULL)
3392 return NULL;
3393
3394 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3395 }
3396
3397 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3398
3399 level -= 1;
3400 }
3401
3402 return pte;
3403 }
3404
3405 static int __set_gcr3(struct protection_domain *domain, int pasid,
3406 unsigned long cr3)
3407 {
3408 u64 *pte;
3409
3410 if (domain->mode != PAGE_MODE_NONE)
3411 return -EINVAL;
3412
3413 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3414 if (pte == NULL)
3415 return -ENOMEM;
3416
3417 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3418
3419 return __amd_iommu_flush_tlb(domain, pasid);
3420 }
3421
3422 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3423 {
3424 u64 *pte;
3425
3426 if (domain->mode != PAGE_MODE_NONE)
3427 return -EINVAL;
3428
3429 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3430 if (pte == NULL)
3431 return 0;
3432
3433 *pte = 0;
3434
3435 return __amd_iommu_flush_tlb(domain, pasid);
3436 }
3437
3438 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3439 unsigned long cr3)
3440 {
3441 struct protection_domain *domain = to_pdomain(dom);
3442 unsigned long flags;
3443 int ret;
3444
3445 spin_lock_irqsave(&domain->lock, flags);
3446 ret = __set_gcr3(domain, pasid, cr3);
3447 spin_unlock_irqrestore(&domain->lock, flags);
3448
3449 return ret;
3450 }
3451 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3452
3453 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3454 {
3455 struct protection_domain *domain = to_pdomain(dom);
3456 unsigned long flags;
3457 int ret;
3458
3459 spin_lock_irqsave(&domain->lock, flags);
3460 ret = __clear_gcr3(domain, pasid);
3461 spin_unlock_irqrestore(&domain->lock, flags);
3462
3463 return ret;
3464 }
3465 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3466
3467 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3468 int status, int tag)
3469 {
3470 struct iommu_dev_data *dev_data;
3471 struct amd_iommu *iommu;
3472 struct iommu_cmd cmd;
3473
3474 dev_data = get_dev_data(&pdev->dev);
3475 iommu = amd_iommu_rlookup_table[dev_data->devid];
3476
3477 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3478 tag, dev_data->pri_tlp);
3479
3480 return iommu_queue_command(iommu, &cmd);
3481 }
3482 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3483
3484 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3485 {
3486 struct protection_domain *pdomain;
3487
3488 pdomain = get_domain(&pdev->dev);
3489 if (IS_ERR(pdomain))
3490 return NULL;
3491
3492 /* Only return IOMMUv2 domains */
3493 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3494 return NULL;
3495
3496 return &pdomain->domain;
3497 }
3498 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3499
3500 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3501 {
3502 struct iommu_dev_data *dev_data;
3503
3504 if (!amd_iommu_v2_supported())
3505 return;
3506
3507 dev_data = get_dev_data(&pdev->dev);
3508 dev_data->errata |= (1 << erratum);
3509 }
3510 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3511
3512 int amd_iommu_device_info(struct pci_dev *pdev,
3513 struct amd_iommu_device_info *info)
3514 {
3515 int max_pasids;
3516 int pos;
3517
3518 if (pdev == NULL || info == NULL)
3519 return -EINVAL;
3520
3521 if (!amd_iommu_v2_supported())
3522 return -EINVAL;
3523
3524 memset(info, 0, sizeof(*info));
3525
3526 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3527 if (pos)
3528 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3529
3530 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3531 if (pos)
3532 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3533
3534 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3535 if (pos) {
3536 int features;
3537
3538 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3539 max_pasids = min(max_pasids, (1 << 20));
3540
3541 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3542 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3543
3544 features = pci_pasid_features(pdev);
3545 if (features & PCI_PASID_CAP_EXEC)
3546 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3547 if (features & PCI_PASID_CAP_PRIV)
3548 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3549 }
3550
3551 return 0;
3552 }
3553 EXPORT_SYMBOL(amd_iommu_device_info);
3554
3555 #ifdef CONFIG_IRQ_REMAP
3556
3557 /*****************************************************************************
3558 *
3559 * Interrupt Remapping Implementation
3560 *
3561 *****************************************************************************/
3562
3563 static struct irq_chip amd_ir_chip;
3564 static DEFINE_SPINLOCK(iommu_table_lock);
3565
3566 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3567 {
3568 u64 dte;
3569
3570 dte = amd_iommu_dev_table[devid].data[2];
3571 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3572 dte |= iommu_virt_to_phys(table->table);
3573 dte |= DTE_IRQ_REMAP_INTCTL;
3574 dte |= DTE_IRQ_TABLE_LEN;
3575 dte |= DTE_IRQ_REMAP_ENABLE;
3576
3577 amd_iommu_dev_table[devid].data[2] = dte;
3578 }
3579
3580 static struct irq_remap_table *get_irq_table(u16 devid)
3581 {
3582 struct irq_remap_table *table;
3583
3584 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3585 "%s: no iommu for devid %x\n", __func__, devid))
3586 return NULL;
3587
3588 table = irq_lookup_table[devid];
3589 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3590 return NULL;
3591
3592 return table;
3593 }
3594
3595 static struct irq_remap_table *__alloc_irq_table(void)
3596 {
3597 struct irq_remap_table *table;
3598
3599 table = kzalloc(sizeof(*table), GFP_KERNEL);
3600 if (!table)
3601 return NULL;
3602
3603 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3604 if (!table->table) {
3605 kfree(table);
3606 return NULL;
3607 }
3608 raw_spin_lock_init(&table->lock);
3609
3610 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3611 memset(table->table, 0,
3612 MAX_IRQS_PER_TABLE * sizeof(u32));
3613 else
3614 memset(table->table, 0,
3615 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3616 return table;
3617 }
3618
3619 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3620 struct irq_remap_table *table)
3621 {
3622 irq_lookup_table[devid] = table;
3623 set_dte_irq_entry(devid, table);
3624 iommu_flush_dte(iommu, devid);
3625 }
3626
3627 static struct irq_remap_table *alloc_irq_table(u16 devid)
3628 {
3629 struct irq_remap_table *table = NULL;
3630 struct irq_remap_table *new_table = NULL;
3631 struct amd_iommu *iommu;
3632 unsigned long flags;
3633 u16 alias;
3634
3635 spin_lock_irqsave(&iommu_table_lock, flags);
3636
3637 iommu = amd_iommu_rlookup_table[devid];
3638 if (!iommu)
3639 goto out_unlock;
3640
3641 table = irq_lookup_table[devid];
3642 if (table)
3643 goto out_unlock;
3644
3645 alias = amd_iommu_alias_table[devid];
3646 table = irq_lookup_table[alias];
3647 if (table) {
3648 set_remap_table_entry(iommu, devid, table);
3649 goto out_wait;
3650 }
3651 spin_unlock_irqrestore(&iommu_table_lock, flags);
3652
3653 /* Nothing there yet, allocate new irq remapping table */
3654 new_table = __alloc_irq_table();
3655 if (!new_table)
3656 return NULL;
3657
3658 spin_lock_irqsave(&iommu_table_lock, flags);
3659
3660 table = irq_lookup_table[devid];
3661 if (table)
3662 goto out_unlock;
3663
3664 table = irq_lookup_table[alias];
3665 if (table) {
3666 set_remap_table_entry(iommu, devid, table);
3667 goto out_wait;
3668 }
3669
3670 table = new_table;
3671 new_table = NULL;
3672
3673 set_remap_table_entry(iommu, devid, table);
3674 if (devid != alias)
3675 set_remap_table_entry(iommu, alias, table);
3676
3677 out_wait:
3678 iommu_completion_wait(iommu);
3679
3680 out_unlock:
3681 spin_unlock_irqrestore(&iommu_table_lock, flags);
3682
3683 if (new_table) {
3684 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3685 kfree(new_table);
3686 }
3687 return table;
3688 }
3689
3690 static int alloc_irq_index(u16 devid, int count, bool align)
3691 {
3692 struct irq_remap_table *table;
3693 int index, c, alignment = 1;
3694 unsigned long flags;
3695 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3696
3697 if (!iommu)
3698 return -ENODEV;
3699
3700 table = alloc_irq_table(devid);
3701 if (!table)
3702 return -ENODEV;
3703
3704 if (align)
3705 alignment = roundup_pow_of_two(count);
3706
3707 raw_spin_lock_irqsave(&table->lock, flags);
3708
3709 /* Scan table for free entries */
3710 for (index = ALIGN(table->min_index, alignment), c = 0;
3711 index < MAX_IRQS_PER_TABLE;) {
3712 if (!iommu->irte_ops->is_allocated(table, index)) {
3713 c += 1;
3714 } else {
3715 c = 0;
3716 index = ALIGN(index + 1, alignment);
3717 continue;
3718 }
3719
3720 if (c == count) {
3721 for (; c != 0; --c)
3722 iommu->irte_ops->set_allocated(table, index - c + 1);
3723
3724 index -= count - 1;
3725 goto out;
3726 }
3727
3728 index++;
3729 }
3730
3731 index = -ENOSPC;
3732
3733 out:
3734 raw_spin_unlock_irqrestore(&table->lock, flags);
3735
3736 return index;
3737 }
3738
3739 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3740 struct amd_ir_data *data)
3741 {
3742 struct irq_remap_table *table;
3743 struct amd_iommu *iommu;
3744 unsigned long flags;
3745 struct irte_ga *entry;
3746
3747 iommu = amd_iommu_rlookup_table[devid];
3748 if (iommu == NULL)
3749 return -EINVAL;
3750
3751 table = get_irq_table(devid);
3752 if (!table)
3753 return -ENOMEM;
3754
3755 raw_spin_lock_irqsave(&table->lock, flags);
3756
3757 entry = (struct irte_ga *)table->table;
3758 entry = &entry[index];
3759 entry->lo.fields_remap.valid = 0;
3760 entry->hi.val = irte->hi.val;
3761 entry->lo.val = irte->lo.val;
3762 entry->lo.fields_remap.valid = 1;
3763 if (data)
3764 data->ref = entry;
3765
3766 raw_spin_unlock_irqrestore(&table->lock, flags);
3767
3768 iommu_flush_irt(iommu, devid);
3769 iommu_completion_wait(iommu);
3770
3771 return 0;
3772 }
3773
3774 static int modify_irte(u16 devid, int index, union irte *irte)
3775 {
3776 struct irq_remap_table *table;
3777 struct amd_iommu *iommu;
3778 unsigned long flags;
3779
3780 iommu = amd_iommu_rlookup_table[devid];
3781 if (iommu == NULL)
3782 return -EINVAL;
3783
3784 table = get_irq_table(devid);
3785 if (!table)
3786 return -ENOMEM;
3787
3788 raw_spin_lock_irqsave(&table->lock, flags);
3789 table->table[index] = irte->val;
3790 raw_spin_unlock_irqrestore(&table->lock, flags);
3791
3792 iommu_flush_irt(iommu, devid);
3793 iommu_completion_wait(iommu);
3794
3795 return 0;
3796 }
3797
3798 static void free_irte(u16 devid, int index)
3799 {
3800 struct irq_remap_table *table;
3801 struct amd_iommu *iommu;
3802 unsigned long flags;
3803
3804 iommu = amd_iommu_rlookup_table[devid];
3805 if (iommu == NULL)
3806 return;
3807
3808 table = get_irq_table(devid);
3809 if (!table)
3810 return;
3811
3812 raw_spin_lock_irqsave(&table->lock, flags);
3813 iommu->irte_ops->clear_allocated(table, index);
3814 raw_spin_unlock_irqrestore(&table->lock, flags);
3815
3816 iommu_flush_irt(iommu, devid);
3817 iommu_completion_wait(iommu);
3818 }
3819
3820 static void irte_prepare(void *entry,
3821 u32 delivery_mode, u32 dest_mode,
3822 u8 vector, u32 dest_apicid, int devid)
3823 {
3824 union irte *irte = (union irte *) entry;
3825
3826 irte->val = 0;
3827 irte->fields.vector = vector;
3828 irte->fields.int_type = delivery_mode;
3829 irte->fields.destination = dest_apicid;
3830 irte->fields.dm = dest_mode;
3831 irte->fields.valid = 1;
3832 }
3833
3834 static void irte_ga_prepare(void *entry,
3835 u32 delivery_mode, u32 dest_mode,
3836 u8 vector, u32 dest_apicid, int devid)
3837 {
3838 struct irte_ga *irte = (struct irte_ga *) entry;
3839
3840 irte->lo.val = 0;
3841 irte->hi.val = 0;
3842 irte->lo.fields_remap.int_type = delivery_mode;
3843 irte->lo.fields_remap.dm = dest_mode;
3844 irte->hi.fields.vector = vector;
3845 irte->lo.fields_remap.destination = dest_apicid;
3846 irte->lo.fields_remap.valid = 1;
3847 }
3848
3849 static void irte_activate(void *entry, u16 devid, u16 index)
3850 {
3851 union irte *irte = (union irte *) entry;
3852
3853 irte->fields.valid = 1;
3854 modify_irte(devid, index, irte);
3855 }
3856
3857 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3858 {
3859 struct irte_ga *irte = (struct irte_ga *) entry;
3860
3861 irte->lo.fields_remap.valid = 1;
3862 modify_irte_ga(devid, index, irte, NULL);
3863 }
3864
3865 static void irte_deactivate(void *entry, u16 devid, u16 index)
3866 {
3867 union irte *irte = (union irte *) entry;
3868
3869 irte->fields.valid = 0;
3870 modify_irte(devid, index, irte);
3871 }
3872
3873 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3874 {
3875 struct irte_ga *irte = (struct irte_ga *) entry;
3876
3877 irte->lo.fields_remap.valid = 0;
3878 modify_irte_ga(devid, index, irte, NULL);
3879 }
3880
3881 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3882 u8 vector, u32 dest_apicid)
3883 {
3884 union irte *irte = (union irte *) entry;
3885
3886 irte->fields.vector = vector;
3887 irte->fields.destination = dest_apicid;
3888 modify_irte(devid, index, irte);
3889 }
3890
3891 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3892 u8 vector, u32 dest_apicid)
3893 {
3894 struct irte_ga *irte = (struct irte_ga *) entry;
3895
3896 if (!irte->lo.fields_remap.guest_mode) {
3897 irte->hi.fields.vector = vector;
3898 irte->lo.fields_remap.destination = dest_apicid;
3899 modify_irte_ga(devid, index, irte, NULL);
3900 }
3901 }
3902
3903 #define IRTE_ALLOCATED (~1U)
3904 static void irte_set_allocated(struct irq_remap_table *table, int index)
3905 {
3906 table->table[index] = IRTE_ALLOCATED;
3907 }
3908
3909 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3910 {
3911 struct irte_ga *ptr = (struct irte_ga *)table->table;
3912 struct irte_ga *irte = &ptr[index];
3913
3914 memset(&irte->lo.val, 0, sizeof(u64));
3915 memset(&irte->hi.val, 0, sizeof(u64));
3916 irte->hi.fields.vector = 0xff;
3917 }
3918
3919 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3920 {
3921 union irte *ptr = (union irte *)table->table;
3922 union irte *irte = &ptr[index];
3923
3924 return irte->val != 0;
3925 }
3926
3927 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3928 {
3929 struct irte_ga *ptr = (struct irte_ga *)table->table;
3930 struct irte_ga *irte = &ptr[index];
3931
3932 return irte->hi.fields.vector != 0;
3933 }
3934
3935 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3936 {
3937 table->table[index] = 0;
3938 }
3939
3940 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3941 {
3942 struct irte_ga *ptr = (struct irte_ga *)table->table;
3943 struct irte_ga *irte = &ptr[index];
3944
3945 memset(&irte->lo.val, 0, sizeof(u64));
3946 memset(&irte->hi.val, 0, sizeof(u64));
3947 }
3948
3949 static int get_devid(struct irq_alloc_info *info)
3950 {
3951 int devid = -1;
3952
3953 switch (info->type) {
3954 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3955 devid = get_ioapic_devid(info->ioapic_id);
3956 break;
3957 case X86_IRQ_ALLOC_TYPE_HPET:
3958 devid = get_hpet_devid(info->hpet_id);
3959 break;
3960 case X86_IRQ_ALLOC_TYPE_MSI:
3961 case X86_IRQ_ALLOC_TYPE_MSIX:
3962 devid = get_device_id(&info->msi_dev->dev);
3963 break;
3964 default:
3965 BUG_ON(1);
3966 break;
3967 }
3968
3969 return devid;
3970 }
3971
3972 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3973 {
3974 struct amd_iommu *iommu;
3975 int devid;
3976
3977 if (!info)
3978 return NULL;
3979
3980 devid = get_devid(info);
3981 if (devid >= 0) {
3982 iommu = amd_iommu_rlookup_table[devid];
3983 if (iommu)
3984 return iommu->ir_domain;
3985 }
3986
3987 return NULL;
3988 }
3989
3990 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3991 {
3992 struct amd_iommu *iommu;
3993 int devid;
3994
3995 if (!info)
3996 return NULL;
3997
3998 switch (info->type) {
3999 case X86_IRQ_ALLOC_TYPE_MSI:
4000 case X86_IRQ_ALLOC_TYPE_MSIX:
4001 devid = get_device_id(&info->msi_dev->dev);
4002 if (devid < 0)
4003 return NULL;
4004
4005 iommu = amd_iommu_rlookup_table[devid];
4006 if (iommu)
4007 return iommu->msi_domain;
4008 break;
4009 default:
4010 break;
4011 }
4012
4013 return NULL;
4014 }
4015
4016 struct irq_remap_ops amd_iommu_irq_ops = {
4017 .prepare = amd_iommu_prepare,
4018 .enable = amd_iommu_enable,
4019 .disable = amd_iommu_disable,
4020 .reenable = amd_iommu_reenable,
4021 .enable_faulting = amd_iommu_enable_faulting,
4022 .get_ir_irq_domain = get_ir_irq_domain,
4023 .get_irq_domain = get_irq_domain,
4024 };
4025
4026 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4027 struct irq_cfg *irq_cfg,
4028 struct irq_alloc_info *info,
4029 int devid, int index, int sub_handle)
4030 {
4031 struct irq_2_irte *irte_info = &data->irq_2_irte;
4032 struct msi_msg *msg = &data->msi_entry;
4033 struct IO_APIC_route_entry *entry;
4034 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4035
4036 if (!iommu)
4037 return;
4038
4039 data->irq_2_irte.devid = devid;
4040 data->irq_2_irte.index = index + sub_handle;
4041 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4042 apic->irq_dest_mode, irq_cfg->vector,
4043 irq_cfg->dest_apicid, devid);
4044
4045 switch (info->type) {
4046 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4047 /* Setup IOAPIC entry */
4048 entry = info->ioapic_entry;
4049 info->ioapic_entry = NULL;
4050 memset(entry, 0, sizeof(*entry));
4051 entry->vector = index;
4052 entry->mask = 0;
4053 entry->trigger = info->ioapic_trigger;
4054 entry->polarity = info->ioapic_polarity;
4055 /* Mask level triggered irqs. */
4056 if (info->ioapic_trigger)
4057 entry->mask = 1;
4058 break;
4059
4060 case X86_IRQ_ALLOC_TYPE_HPET:
4061 case X86_IRQ_ALLOC_TYPE_MSI:
4062 case X86_IRQ_ALLOC_TYPE_MSIX:
4063 msg->address_hi = MSI_ADDR_BASE_HI;
4064 msg->address_lo = MSI_ADDR_BASE_LO;
4065 msg->data = irte_info->index;
4066 break;
4067
4068 default:
4069 BUG_ON(1);
4070 break;
4071 }
4072 }
4073
4074 struct amd_irte_ops irte_32_ops = {
4075 .prepare = irte_prepare,
4076 .activate = irte_activate,
4077 .deactivate = irte_deactivate,
4078 .set_affinity = irte_set_affinity,
4079 .set_allocated = irte_set_allocated,
4080 .is_allocated = irte_is_allocated,
4081 .clear_allocated = irte_clear_allocated,
4082 };
4083
4084 struct amd_irte_ops irte_128_ops = {
4085 .prepare = irte_ga_prepare,
4086 .activate = irte_ga_activate,
4087 .deactivate = irte_ga_deactivate,
4088 .set_affinity = irte_ga_set_affinity,
4089 .set_allocated = irte_ga_set_allocated,
4090 .is_allocated = irte_ga_is_allocated,
4091 .clear_allocated = irte_ga_clear_allocated,
4092 };
4093
4094 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4095 unsigned int nr_irqs, void *arg)
4096 {
4097 struct irq_alloc_info *info = arg;
4098 struct irq_data *irq_data;
4099 struct amd_ir_data *data = NULL;
4100 struct irq_cfg *cfg;
4101 int i, ret, devid;
4102 int index;
4103
4104 if (!info)
4105 return -EINVAL;
4106 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4107 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4108 return -EINVAL;
4109
4110 /*
4111 * With IRQ remapping enabled, don't need contiguous CPU vectors
4112 * to support multiple MSI interrupts.
4113 */
4114 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4115 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4116
4117 devid = get_devid(info);
4118 if (devid < 0)
4119 return -EINVAL;
4120
4121 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4122 if (ret < 0)
4123 return ret;
4124
4125 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4126 struct irq_remap_table *table;
4127 struct amd_iommu *iommu;
4128
4129 table = alloc_irq_table(devid);
4130 if (table) {
4131 if (!table->min_index) {
4132 /*
4133 * Keep the first 32 indexes free for IOAPIC
4134 * interrupts.
4135 */
4136 table->min_index = 32;
4137 iommu = amd_iommu_rlookup_table[devid];
4138 for (i = 0; i < 32; ++i)
4139 iommu->irte_ops->set_allocated(table, i);
4140 }
4141 WARN_ON(table->min_index != 32);
4142 index = info->ioapic_pin;
4143 } else {
4144 index = -ENOMEM;
4145 }
4146 } else {
4147 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4148
4149 index = alloc_irq_index(devid, nr_irqs, align);
4150 }
4151 if (index < 0) {
4152 pr_warn("Failed to allocate IRTE\n");
4153 ret = index;
4154 goto out_free_parent;
4155 }
4156
4157 for (i = 0; i < nr_irqs; i++) {
4158 irq_data = irq_domain_get_irq_data(domain, virq + i);
4159 cfg = irqd_cfg(irq_data);
4160 if (!irq_data || !cfg) {
4161 ret = -EINVAL;
4162 goto out_free_data;
4163 }
4164
4165 ret = -ENOMEM;
4166 data = kzalloc(sizeof(*data), GFP_KERNEL);
4167 if (!data)
4168 goto out_free_data;
4169
4170 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4171 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4172 else
4173 data->entry = kzalloc(sizeof(struct irte_ga),
4174 GFP_KERNEL);
4175 if (!data->entry) {
4176 kfree(data);
4177 goto out_free_data;
4178 }
4179
4180 irq_data->hwirq = (devid << 16) + i;
4181 irq_data->chip_data = data;
4182 irq_data->chip = &amd_ir_chip;
4183 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4184 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4185 }
4186
4187 return 0;
4188
4189 out_free_data:
4190 for (i--; i >= 0; i--) {
4191 irq_data = irq_domain_get_irq_data(domain, virq + i);
4192 if (irq_data)
4193 kfree(irq_data->chip_data);
4194 }
4195 for (i = 0; i < nr_irqs; i++)
4196 free_irte(devid, index + i);
4197 out_free_parent:
4198 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4199 return ret;
4200 }
4201
4202 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4203 unsigned int nr_irqs)
4204 {
4205 struct irq_2_irte *irte_info;
4206 struct irq_data *irq_data;
4207 struct amd_ir_data *data;
4208 int i;
4209
4210 for (i = 0; i < nr_irqs; i++) {
4211 irq_data = irq_domain_get_irq_data(domain, virq + i);
4212 if (irq_data && irq_data->chip_data) {
4213 data = irq_data->chip_data;
4214 irte_info = &data->irq_2_irte;
4215 free_irte(irte_info->devid, irte_info->index);
4216 kfree(data->entry);
4217 kfree(data);
4218 }
4219 }
4220 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4221 }
4222
4223 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4224 struct amd_ir_data *ir_data,
4225 struct irq_2_irte *irte_info,
4226 struct irq_cfg *cfg);
4227
4228 static int irq_remapping_activate(struct irq_domain *domain,
4229 struct irq_data *irq_data, bool reserve)
4230 {
4231 struct amd_ir_data *data = irq_data->chip_data;
4232 struct irq_2_irte *irte_info = &data->irq_2_irte;
4233 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4234 struct irq_cfg *cfg = irqd_cfg(irq_data);
4235
4236 if (!iommu)
4237 return 0;
4238
4239 iommu->irte_ops->activate(data->entry, irte_info->devid,
4240 irte_info->index);
4241 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4242 return 0;
4243 }
4244
4245 static void irq_remapping_deactivate(struct irq_domain *domain,
4246 struct irq_data *irq_data)
4247 {
4248 struct amd_ir_data *data = irq_data->chip_data;
4249 struct irq_2_irte *irte_info = &data->irq_2_irte;
4250 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4251
4252 if (iommu)
4253 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4254 irte_info->index);
4255 }
4256
4257 static const struct irq_domain_ops amd_ir_domain_ops = {
4258 .alloc = irq_remapping_alloc,
4259 .free = irq_remapping_free,
4260 .activate = irq_remapping_activate,
4261 .deactivate = irq_remapping_deactivate,
4262 };
4263
4264 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4265 {
4266 struct amd_iommu *iommu;
4267 struct amd_iommu_pi_data *pi_data = vcpu_info;
4268 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4269 struct amd_ir_data *ir_data = data->chip_data;
4270 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4271 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4272 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4273
4274 /* Note:
4275 * This device has never been set up for guest mode.
4276 * we should not modify the IRTE
4277 */
4278 if (!dev_data || !dev_data->use_vapic)
4279 return 0;
4280
4281 pi_data->ir_data = ir_data;
4282
4283 /* Note:
4284 * SVM tries to set up for VAPIC mode, but we are in
4285 * legacy mode. So, we force legacy mode instead.
4286 */
4287 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4288 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4289 __func__);
4290 pi_data->is_guest_mode = false;
4291 }
4292
4293 iommu = amd_iommu_rlookup_table[irte_info->devid];
4294 if (iommu == NULL)
4295 return -EINVAL;
4296
4297 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4298 if (pi_data->is_guest_mode) {
4299 /* Setting */
4300 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4301 irte->hi.fields.vector = vcpu_pi_info->vector;
4302 irte->lo.fields_vapic.ga_log_intr = 1;
4303 irte->lo.fields_vapic.guest_mode = 1;
4304 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4305
4306 ir_data->cached_ga_tag = pi_data->ga_tag;
4307 } else {
4308 /* Un-Setting */
4309 struct irq_cfg *cfg = irqd_cfg(data);
4310
4311 irte->hi.val = 0;
4312 irte->lo.val = 0;
4313 irte->hi.fields.vector = cfg->vector;
4314 irte->lo.fields_remap.guest_mode = 0;
4315 irte->lo.fields_remap.destination = cfg->dest_apicid;
4316 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4317 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4318
4319 /*
4320 * This communicates the ga_tag back to the caller
4321 * so that it can do all the necessary clean up.
4322 */
4323 ir_data->cached_ga_tag = 0;
4324 }
4325
4326 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4327 }
4328
4329
4330 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4331 struct amd_ir_data *ir_data,
4332 struct irq_2_irte *irte_info,
4333 struct irq_cfg *cfg)
4334 {
4335
4336 /*
4337 * Atomically updates the IRTE with the new destination, vector
4338 * and flushes the interrupt entry cache.
4339 */
4340 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4341 irte_info->index, cfg->vector,
4342 cfg->dest_apicid);
4343 }
4344
4345 static int amd_ir_set_affinity(struct irq_data *data,
4346 const struct cpumask *mask, bool force)
4347 {
4348 struct amd_ir_data *ir_data = data->chip_data;
4349 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4350 struct irq_cfg *cfg = irqd_cfg(data);
4351 struct irq_data *parent = data->parent_data;
4352 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4353 int ret;
4354
4355 if (!iommu)
4356 return -ENODEV;
4357
4358 ret = parent->chip->irq_set_affinity(parent, mask, force);
4359 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4360 return ret;
4361
4362 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4363 /*
4364 * After this point, all the interrupts will start arriving
4365 * at the new destination. So, time to cleanup the previous
4366 * vector allocation.
4367 */
4368 send_cleanup_vector(cfg);
4369
4370 return IRQ_SET_MASK_OK_DONE;
4371 }
4372
4373 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4374 {
4375 struct amd_ir_data *ir_data = irq_data->chip_data;
4376
4377 *msg = ir_data->msi_entry;
4378 }
4379
4380 static struct irq_chip amd_ir_chip = {
4381 .name = "AMD-IR",
4382 .irq_ack = ir_ack_apic_edge,
4383 .irq_set_affinity = amd_ir_set_affinity,
4384 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4385 .irq_compose_msi_msg = ir_compose_msi_msg,
4386 };
4387
4388 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4389 {
4390 struct fwnode_handle *fn;
4391
4392 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4393 if (!fn)
4394 return -ENOMEM;
4395 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4396 irq_domain_free_fwnode(fn);
4397 if (!iommu->ir_domain)
4398 return -ENOMEM;
4399
4400 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4401 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4402 "AMD-IR-MSI",
4403 iommu->index);
4404 return 0;
4405 }
4406
4407 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4408 {
4409 unsigned long flags;
4410 struct amd_iommu *iommu;
4411 struct irq_remap_table *table;
4412 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4413 int devid = ir_data->irq_2_irte.devid;
4414 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4415 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4416
4417 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4418 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4419 return 0;
4420
4421 iommu = amd_iommu_rlookup_table[devid];
4422 if (!iommu)
4423 return -ENODEV;
4424
4425 table = get_irq_table(devid);
4426 if (!table)
4427 return -ENODEV;
4428
4429 raw_spin_lock_irqsave(&table->lock, flags);
4430
4431 if (ref->lo.fields_vapic.guest_mode) {
4432 if (cpu >= 0)
4433 ref->lo.fields_vapic.destination = cpu;
4434 ref->lo.fields_vapic.is_run = is_run;
4435 barrier();
4436 }
4437
4438 raw_spin_unlock_irqrestore(&table->lock, flags);
4439
4440 iommu_flush_irt(iommu, devid);
4441 iommu_completion_wait(iommu);
4442 return 0;
4443 }
4444 EXPORT_SYMBOL(amd_iommu_update_ga);
4445 #endif
Linux with added FPC-III support