drivers/net/dsa/mv88e6xxx/global2.h

   1 /*
   2  * Marvell 88E6xxx Switch Global 2 Registers support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   7  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #ifndef _MV88E6XXX_GLOBAL2_H
  16 #define _MV88E6XXX_GLOBAL2_H
  17
  18 #include "chip.h"
  19
  20 /* Offset 0x00: Interrupt Source Register */
  21 #define MV88E6XXX_G2_INT_SRC                    0x00
  22 #define MV88E6XXX_G2_INT_SRC_WDOG               0x8000
  23 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT          0x4000
  24 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH    0x2000
  25 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT         0x1000
  26 #define MV88E6352_G2_INT_SRC_SERDES             0x0800
  27 #define MV88E6352_G2_INT_SRC_PHY                0x001f
  28 #define MV88E6390_G2_INT_SRC_PHY                0x07fe
  29
  30 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG        15
  31
  32 /* Offset 0x01: Interrupt Mask Register */
  33 #define MV88E6XXX_G2_INT_MASK                   0x01
  34 #define MV88E6XXX_G2_INT_MASK_WDOG              0x8000
  35 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT         0x4000
  36 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH   0x2000
  37 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT        0x1000
  38 #define MV88E6352_G2_INT_MASK_SERDES            0x0800
  39 #define MV88E6352_G2_INT_MASK_PHY               0x001f
  40 #define MV88E6390_G2_INT_MASK_PHY               0x07fe
  41
  42 /* Offset 0x02: MGMT Enable Register 2x */
  43 #define MV88E6XXX_G2_MGMT_EN_2X         0x02
  44
  45 /* Offset 0x03: MGMT Enable Register 0x */
  46 #define MV88E6XXX_G2_MGMT_EN_0X         0x03
  47
  48 /* Offset 0x04: Flow Control Delay Register */
  49 #define MV88E6XXX_G2_FLOW_CTL   0x04
  50
  51 /* Offset 0x05: Switch Management Register */
  52 #define MV88E6XXX_G2_SWITCH_MGMT                        0x05
  53 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA    0x8000
  54 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS          0x4000
  55 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG           0x2000
  56 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI     0x0080
  57 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU               0x0008
  58
  59 /* Offset 0x06: Device Mapping Table Register */
  60 #define MV88E6XXX_G2_DEVICE_MAPPING             0x06
  61 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE      0x8000
  62 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK    0x1f00
  63 #define MV88E6XXX_G2_DEVICE_MAPPING_PORT_MASK   0x000f
  64
  65 /* Offset 0x07: Trunk Mask Table Register */
  66 #define MV88E6XXX_G2_TRUNK_MASK                 0x07
  67 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE          0x8000
  68 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK        0x7000
  69 #define MV88E6XXX_G2_TRUNK_MASK_HASH            0x0800
  70
  71 /* Offset 0x08: Trunk Mapping Table Register */
  72 #define MV88E6XXX_G2_TRUNK_MAPPING              0x08
  73 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE       0x8000
  74 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK      0x7800
  75
  76 /* Offset 0x09: Ingress Rate Command Register */
  77 #define MV88E6XXX_G2_IRL_CMD                    0x09
  78 #define MV88E6XXX_G2_IRL_CMD_BUSY               0x8000
  79 #define MV88E6352_G2_IRL_CMD_OP_MASK            0x7000
  80 #define MV88E6352_G2_IRL_CMD_OP_NOOP            0x0000
  81 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL        0x1000
  82 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES        0x2000
  83 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG       0x3000
  84 #define MV88E6352_G2_IRL_CMD_OP_READ_REG        0x4000
  85 #define MV88E6390_G2_IRL_CMD_OP_MASK            0x6000
  86 #define MV88E6390_G2_IRL_CMD_OP_READ_REG        0x0000
  87 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL        0x2000
  88 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES        0x4000
  89 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG       0x6000
  90 #define MV88E6352_G2_IRL_CMD_PORT_MASK          0x0f00
  91 #define MV88E6390_G2_IRL_CMD_PORT_MASK          0x1f00
  92 #define MV88E6XXX_G2_IRL_CMD_RES_MASK           0x00e0
  93 #define MV88E6XXX_G2_IRL_CMD_REG_MASK           0x000f
  94
  95 /* Offset 0x0A: Ingress Rate Data Register */
  96 #define MV88E6XXX_G2_IRL_DATA           0x0a
  97 #define MV88E6XXX_G2_IRL_DATA_MASK      0xffff
  98
  99 /* Offset 0x0B: Cross-chip Port VLAN Register */
 100 #define MV88E6XXX_G2_PVT_ADDR                   0x0b
 101 #define MV88E6XXX_G2_PVT_ADDR_BUSY              0x8000
 102 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK           0x7000
 103 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES      0x1000
 104 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN    0x3000
 105 #define MV88E6XXX_G2_PVT_ADDR_OP_READ           0x4000
 106 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK          0x01ff
 107
 108 /* Offset 0x0C: Cross-chip Port VLAN Data Register */
 109 #define MV88E6XXX_G2_PVT_DATA           0x0c
 110 #define MV88E6XXX_G2_PVT_DATA_MASK      0x7f
 111
 112 /* Offset 0x0D: Switch MAC/WoL/WoF Register */
 113 #define MV88E6XXX_G2_SWITCH_MAC                 0x0d
 114 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE          0x8000
 115 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK        0x1f00
 116 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK       0x00ff
 117
 118 /* Offset 0x0E: ATU Stats Register */
 119 #define MV88E6XXX_G2_ATU_STATS          0x0e
 120
 121 /* Offset 0x0F: Priority Override Table */
 122 #define MV88E6XXX_G2_PRIO_OVERRIDE              0x0f
 123 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE       0x8000
 124 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET      0x1000
 125 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK     0x0f00
 126 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN    0x0080
 127 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
 128 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN      0x0008
 129 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK    0x0007
 130
 131 /* Offset 0x14: EEPROM Command */
 132 #define MV88E6XXX_G2_EEPROM_CMD                 0x14
 133 #define MV88E6XXX_G2_EEPROM_CMD_BUSY            0x8000
 134 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK         0x7000
 135 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE        0x3000
 136 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ         0x4000
 137 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD         0x6000
 138 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING         0x0800
 139 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN        0x0400
 140 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK       0x00ff
 141 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK       0x00ff
 142
 143 /* Offset 0x15: EEPROM Data */
 144 #define MV88E6352_G2_EEPROM_DATA        0x15
 145 #define MV88E6352_G2_EEPROM_DATA_MASK   0xffff
 146
 147 /* Offset 0x15: EEPROM Addr */
 148 #define MV88E6390_G2_EEPROM_ADDR        0x15
 149 #define MV88E6390_G2_EEPROM_ADDR_MASK   0xffff
 150
 151 /* Offset 0x16: AVB Command Register */
 152 #define MV88E6352_G2_AVB_CMD                    0x16
 153 #define MV88E6352_G2_AVB_CMD_BUSY               0x8000
 154 #define MV88E6352_G2_AVB_CMD_OP_READ            0x4000
 155 #define MV88E6352_G2_AVB_CMD_OP_READ_INCR       0x6000
 156 #define MV88E6352_G2_AVB_CMD_OP_WRITE           0x3000
 157 #define MV88E6390_G2_AVB_CMD_OP_READ            0x0000
 158 #define MV88E6390_G2_AVB_CMD_OP_READ_INCR       0x4000
 159 #define MV88E6390_G2_AVB_CMD_OP_WRITE           0x6000
 160 #define MV88E6352_G2_AVB_CMD_PORT_MASK          0x0f00
 161 #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL     0xe
 162 #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL     0xf
 163 #define MV88E6390_G2_AVB_CMD_PORT_MASK          0x1f00
 164 #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL     0x1e
 165 #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL     0x1f
 166 #define MV88E6352_G2_AVB_CMD_BLOCK_PTP          0
 167 #define MV88E6352_G2_AVB_CMD_BLOCK_AVB          1
 168 #define MV88E6352_G2_AVB_CMD_BLOCK_QAV          2
 169 #define MV88E6352_G2_AVB_CMD_BLOCK_QVB          3
 170 #define MV88E6352_G2_AVB_CMD_BLOCK_MASK         0x00e0
 171 #define MV88E6352_G2_AVB_CMD_ADDR_MASK          0x001f
 172
 173 /* Offset 0x17: AVB Data Register */
 174 #define MV88E6352_G2_AVB_DATA           0x17
 175
 176 /* Offset 0x18: SMI PHY Command Register */
 177 #define MV88E6XXX_G2_SMI_PHY_CMD                        0x18
 178 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY                   0x8000
 179 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK              0x6000
 180 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL          0x0000
 181 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL          0x2000
 182 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP             0x4000
 183 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK              0x1000
 184 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45                0x0000
 185 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22                0x1000
 186 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK                0x0c00
 187 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA       0x0400
 188 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA        0x0800
 189 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR       0x0000
 190 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA       0x0400
 191 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC    0x0800
 192 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA        0x0c00
 193 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK          0x03e0
 194 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK          0x001f
 195 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK         0x03ff
 196
 197 /* Offset 0x19: SMI PHY Data Register */
 198 #define MV88E6XXX_G2_SMI_PHY_DATA       0x19
 199
 200 /* Offset 0x1A: Scratch and Misc. Register */
 201 #define MV88E6XXX_G2_SCRATCH_MISC_MISC          0x1a
 202 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE        0x8000
 203 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK      0x7f00
 204 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK     0x00ff
 205
 206 /* Offset 0x1B: Watch Dog Control Register */
 207 #define MV88E6352_G2_WDOG_CTL                   0x1b
 208 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT      0x0080
 209 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT       0x0040
 210 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE         0x0020
 211 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY    0x0010
 212 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE     0x0008
 213 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ         0x0004
 214 #define MV88E6352_G2_WDOG_CTL_HISTORY           0x0002
 215 #define MV88E6352_G2_WDOG_CTL_SWRESET           0x0001
 216
 217 /* Offset 0x1B: Watch Dog Control Register */
 218 #define MV88E6390_G2_WDOG_CTL                           0x1b
 219 #define MV88E6390_G2_WDOG_CTL_UPDATE                    0x8000
 220 #define MV88E6390_G2_WDOG_CTL_PTR_MASK                  0x7f00
 221 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE            0x0000
 222 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS               0x1000
 223 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE            0x1100
 224 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT                 0x1200
 225 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY               0x1300
 226 #define MV88E6390_G2_WDOG_CTL_DATA_MASK                 0x00ff
 227 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH               0x0008
 228 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER          0x0004
 229 #define MV88E6390_G2_WDOG_CTL_EGRESS                    0x0002
 230 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ                 0x0001
 231
 232 /* Offset 0x1C: QoS Weights Register */
 233 #define MV88E6XXX_G2_QOS_WEIGHTS                0x1c
 234 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE         0x8000
 235 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK       0x3f00
 236 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK       0x7f00
 237 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK      0x00ff
 238
 239 /* Offset 0x1D: Misc Register */
 240 #define MV88E6XXX_G2_MISC               0x1d
 241 #define MV88E6XXX_G2_MISC_5_BIT_PORT    0x4000
 242 #define MV88E6352_G2_NOEGR_POLICY       0x2000
 243 #define MV88E6390_G2_LAG_ID_4           0x2000
 244
 245 /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
 246 /* Offset 0x02: Misc Configuration */
 247 #define MV88E6352_G2_SCRATCH_MISC_CFG           0x02
 248 #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80
 249 /* Offset 0x60-0x61: GPIO Configuration */
 250 #define MV88E6352_G2_SCRATCH_GPIO_CFG0          0x60
 251 #define MV88E6352_G2_SCRATCH_GPIO_CFG1          0x61
 252 /* Offset 0x62-0x63: GPIO Direction */
 253 #define MV88E6352_G2_SCRATCH_GPIO_DIR0          0x62
 254 #define MV88E6352_G2_SCRATCH_GPIO_DIR1          0x63
 255 #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT       0
 256 #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN        1
 257 /* Offset 0x64-0x65: GPIO Data */
 258 #define MV88E6352_G2_SCRATCH_GPIO_DATA0         0x64
 259 #define MV88E6352_G2_SCRATCH_GPIO_DATA1         0x65
 260 /* Offset 0x68-0x6F: GPIO Pin Control */
 261 #define MV88E6352_G2_SCRATCH_GPIO_PCTL0         0x68
 262 #define MV88E6352_G2_SCRATCH_GPIO_PCTL1         0x69
 263 #define MV88E6352_G2_SCRATCH_GPIO_PCTL2         0x6A
 264 #define MV88E6352_G2_SCRATCH_GPIO_PCTL3         0x6B
 265 #define MV88E6352_G2_SCRATCH_GPIO_PCTL4         0x6C
 266 #define MV88E6352_G2_SCRATCH_GPIO_PCTL5         0x6D
 267 #define MV88E6352_G2_SCRATCH_GPIO_PCTL6         0x6E
 268 #define MV88E6352_G2_SCRATCH_GPIO_PCTL7         0x6F
 269 #define MV88E6352_G2_SCRATCH_CONFIG_DATA0       0x70
 270 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1       0x71
 271 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU        BIT(2)
 272 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2       0x72
 273 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK  0x3
 274
 275 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO     0
 276 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG     1
 277 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ    2
 278
 279 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
 280
 281 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
 282 {
 283         return 0;
 284 }
 285
 286 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
 287 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
 288 int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update);
 289 int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
 290
 291 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
 292 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
 293
 294 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
 295                               struct mii_bus *bus,
 296                               int addr, int reg, u16 *val);
 297 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
 298                                struct mii_bus *bus,
 299                                int addr, int reg, u16 val);
 300 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
 301
 302 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
 303                              struct ethtool_eeprom *eeprom, u8 *data);
 304 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
 305                              struct ethtool_eeprom *eeprom, u8 *data);
 306
 307 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
 308                               struct ethtool_eeprom *eeprom, u8 *data);
 309 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
 310                               struct ethtool_eeprom *eeprom, u8 *data);
 311
 312 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
 313                            int src_port, u16 data);
 314 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
 315
 316 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip);
 317 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
 318 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
 319
 320 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
 321                                 struct mii_bus *bus);
 322 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
 323                                 struct mii_bus *bus);
 324
 325 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
 326 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
 327
 328 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
 329
 330 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
 331 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
 332
 333 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
 334 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
 335
 336 extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
 337
 338 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
 339                                       bool external);
 340
 341 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
 342
 343 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
 344 {
 345         if (chip->info->global2_addr) {
 346                 dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
 347                 return -EOPNOTSUPP;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
 354 {
 355         return -EOPNOTSUPP;
 356 }
 357
 358 static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
 359 {
 360         return -EOPNOTSUPP;
 361 }
 362
 363 static inline int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
 364 {
 365         return -EOPNOTSUPP;
 366 }
 367
 368 static inline int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
 369 {
 370         return -EOPNOTSUPP;
 371 }
 372
 373 static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,
 374                                             int port)
 375 {
 376         return -EOPNOTSUPP;
 377 }
 378
 379 static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,
 380                                             int port)
 381 {
 382         return -EOPNOTSUPP;
 383 }
 384
 385 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
 386                                             struct mii_bus *bus,
 387                                             int addr, int reg, u16 *val)
 388 {
 389         return -EOPNOTSUPP;
 390 }
 391
 392 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
 393                                              struct mii_bus *bus,
 394                                              int addr, int reg, u16 val)
 395 {
 396         return -EOPNOTSUPP;
 397 }
 398
 399 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip,
 400                                               u8 *addr)
 401 {
 402         return -EOPNOTSUPP;
 403 }
 404
 405 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
 406                                            struct ethtool_eeprom *eeprom,
 407                                            u8 *data)
 408 {
 409         return -EOPNOTSUPP;
 410 }
 411
 412 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
 413                                            struct ethtool_eeprom *eeprom,
 414                                            u8 *data)
 415 {
 416         return -EOPNOTSUPP;
 417 }
 418
 419 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
 420                                             struct ethtool_eeprom *eeprom,
 421                                             u8 *data)
 422 {
 423         return -EOPNOTSUPP;
 424 }
 425
 426 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
 427                                             struct ethtool_eeprom *eeprom,
 428                                             u8 *data)
 429 {
 430         return -EOPNOTSUPP;
 431 }
 432
 433 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
 434                                          int src_dev, int src_port, u16 data)
 435 {
 436         return -EOPNOTSUPP;
 437 }
 438
 439 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
 440 {
 441         return -EOPNOTSUPP;
 442 }
 443
 444 static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
 445 {
 446         return -EOPNOTSUPP;
 447 }
 448
 449 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
 450 {
 451         return -EOPNOTSUPP;
 452 }
 453
 454 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
 455 {
 456 }
 457
 458 static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
 459                                               struct mii_bus *bus)
 460 {
 461         return 0;
 462 }
 463
 464 static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
 465                                               struct mii_bus *bus)
 466 {
 467 }
 468
 469 static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
 470 {
 471         return -EOPNOTSUPP;
 472 }
 473
 474 static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
 475 {
 476         return -EOPNOTSUPP;
 477 }
 478
 479 static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
 480 {
 481         return -EOPNOTSUPP;
 482 }
 483
 484 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
 485 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
 486
 487 static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {};
 488 static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {};
 489
 490 static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {};
 491
 492 static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
 493                                                     bool external)
 494 {
 495         return -EOPNOTSUPP;
 496 }
 497
 498 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
 499
 500 #endif /* _MV88E6XXX_GLOBAL2_H */