drivers/net/dsa/mv88e6xxx/ptp.h

   1 /*
   2  * Marvell 88E6xxx Switch PTP support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2017 National Instruments
   7  *      Erik Hons <erik.hons@ni.com>
   8  *      Brandon Streiff <brandon.streiff@ni.com>
   9  *      Dane Wagner <dane.wagner@ni.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #ifndef _MV88E6XXX_PTP_H
  18 #define _MV88E6XXX_PTP_H
  19
  20 #include "chip.h"
  21
  22 /* Offset 0x00: TAI Global Config */
  23 #define MV88E6XXX_TAI_CFG                       0x00
  24 #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE         0x8000
  25 #define MV88E6XXX_TAI_CFG_CAP_CTR_START         0x4000
  26 #define MV88E6XXX_TAI_CFG_EVREQ_FALLING         0x2000
  27 #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO        0x1000
  28 #define MV88E6XXX_TAI_CFG_IRL_ENABLE            0x0400
  29 #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN           0x0200
  30 #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN          0x0100
  31 #define MV88E6XXX_TAI_CFG_TRIG_LOCK             0x0080
  32 #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE          0x0008
  33 #define MV88E6XXX_TAI_CFG_MULTI_PTP             0x0004
  34 #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT     0x0002
  35 #define MV88E6XXX_TAI_CFG_TRIG_ENABLE           0x0001
  36
  37 /* Offset 0x01: Timestamp Clock Period (ps) */
  38 #define MV88E6XXX_TAI_CLOCK_PERIOD              0x01
  39
  40 /* Offset 0x02/0x03: Trigger Generation Amount */
  41 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO        0x02
  42 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI        0x03
  43
  44 /* Offset 0x04: Clock Compensation */
  45 #define MV88E6XXX_TAI_TRIG_CLOCK_COMP           0x04
  46
  47 /* Offset 0x05: Trigger Configuration */
  48 #define MV88E6XXX_TAI_TRIG_CFG                  0x05
  49
  50 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
  51 #define MV88E6XXX_TAI_IRL_AMOUNT                0x06
  52
  53 /* Offset 0x07: Ingress Rate Limiter Compensation */
  54 #define MV88E6XXX_TAI_IRL_COMP                  0x07
  55
  56 /* Offset 0x08: Ingress Rate Limiter Compensation */
  57 #define MV88E6XXX_TAI_IRL_COMP_PS               0x08
  58
  59 /* Offset 0x09: Event Status */
  60 #define MV88E6XXX_TAI_EVENT_STATUS              0x09
  61 #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG     0x4000
  62 #define MV88E6XXX_TAI_EVENT_STATUS_ERROR        0x0200
  63 #define MV88E6XXX_TAI_EVENT_STATUS_VALID        0x0100
  64 #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK     0x00ff
  65
  66 /* Offset 0x0A/0x0B: Event Time */
  67 #define MV88E6XXX_TAI_EVENT_TIME_LO             0x0a
  68 #define MV88E6XXX_TAI_EVENT_TYPE_HI             0x0b
  69
  70 /* Offset 0x0E/0x0F: PTP Global Time */
  71 #define MV88E6XXX_TAI_TIME_LO                   0x0e
  72 #define MV88E6XXX_TAI_TIME_HI                   0x0f
  73
  74 /* Offset 0x10/0x11: Trig Generation Time */
  75 #define MV88E6XXX_TAI_TRIG_TIME_LO              0x10
  76 #define MV88E6XXX_TAI_TRIG_TIME_HI              0x11
  77
  78 /* Offset 0x12: Lock Status */
  79 #define MV88E6XXX_TAI_LOCK_STATUS               0x12
  80
  81 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP
  82
  83 long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp);
  84 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip);
  85 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip);
  86
  87 #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip,       \
  88                                       ptp_clock_info)
  89
  90 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */
  91
  92 static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp)
  93 {
  94         return -1;
  95 }
  96
  97 static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
  98 {
  99         return 0;
 100 }
 101
 102 static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
 103 {
 104 }
 105
 106 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */
 107
 108 #endif /* _MV88E6XXX_PTP_H */