arch/x86/kernel/early-quirks.c

   1 /* Various workarounds for chipset bugs.
   2    This code runs very early and can't use the regular PCI subsystem
   3    The entries are keyed to PCI bridges which usually identify chipsets
   4    uniquely.
   5    This is only for whole classes of chipsets with specific problems which
   6    need early invasive action (e.g. before the timers are initialized).
   7    Most PCI device specific workarounds can be done later and should be
   8    in standard PCI quirks
   9    Mainboard specific bugs should be handled by DMI entries.
  10    CPU specific bugs in setup.c */
  11
  12 #include <linux/pci.h>
  13 #include <linux/acpi.h>
  14 #include <linux/pci_ids.h>
  15 #include <drm/i915_drm.h>
  16 #include <asm/pci-direct.h>
  17 #include <asm/dma.h>
  18 #include <asm/io_apic.h>
  19 #include <asm/apic.h>
  20 #include <asm/iommu.h>
  21 #include <asm/gart.h>
  22 #include <asm/irq_remapping.h>
  23
  24 static void __init fix_hypertransport_config(int num, int slot, int func)
  25 {
  26         u32 htcfg;
  27         /*
  28          * we found a hypertransport bus
  29          * make sure that we are broadcasting
  30          * interrupts to all cpus on the ht bus
  31          * if we're using extended apic ids
  32          */
  33         htcfg = read_pci_config(num, slot, func, 0x68);
  34         if (htcfg & (1 << 18)) {
  35                 printk(KERN_INFO "Detected use of extended apic ids "
  36                                  "on hypertransport bus\n");
  37                 if ((htcfg & (1 << 17)) == 0) {
  38                         printk(KERN_INFO "Enabling hypertransport extended "
  39                                          "apic interrupt broadcast\n");
  40                         printk(KERN_INFO "Note this is a bios bug, "
  41                                          "please contact your hw vendor\n");
  42                         htcfg |= (1 << 17);
  43                         write_pci_config(num, slot, func, 0x68, htcfg);
  44                 }
  45         }
  46
  47
  48 }
  49
  50 static void __init via_bugs(int  num, int slot, int func)
  51 {
  52 #ifdef CONFIG_GART_IOMMU
  53         if ((max_pfn > MAX_DMA32_PFN ||  force_iommu) &&
  54             !gart_iommu_aperture_allowed) {
  55                 printk(KERN_INFO
  56                        "Looks like a VIA chipset. Disabling IOMMU."
  57                        " Override with iommu=allowed\n");
  58                 gart_iommu_aperture_disabled = 1;
  59         }
  60 #endif
  61 }
  62
  63 #ifdef CONFIG_ACPI
  64 #ifdef CONFIG_X86_IO_APIC
  65
  66 static int __init nvidia_hpet_check(struct acpi_table_header *header)
  67 {
  68         return 0;
  69 }
  70 #endif /* CONFIG_X86_IO_APIC */
  71 #endif /* CONFIG_ACPI */
  72
  73 static void __init nvidia_bugs(int num, int slot, int func)
  74 {
  75 #ifdef CONFIG_ACPI
  76 #ifdef CONFIG_X86_IO_APIC
  77         /*
  78          * All timer overrides on Nvidia are
  79          * wrong unless HPET is enabled.
  80          * Unfortunately that's not true on many Asus boards.
  81          * We don't know yet how to detect this automatically, but
  82          * at least allow a command line override.
  83          */
  84         if (acpi_use_timer_override)
  85                 return;
  86
  87         if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
  88                 acpi_skip_timer_override = 1;
  89                 printk(KERN_INFO "Nvidia board "
  90                        "detected. Ignoring ACPI "
  91                        "timer override.\n");
  92                 printk(KERN_INFO "If you got timer trouble "
  93                         "try acpi_use_timer_override\n");
  94         }
  95 #endif
  96 #endif
  97         /* RED-PEN skip them on mptables too? */
  98
  99 }
 100
 101 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
 102 static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
 103 {
 104         u32 d;
 105         u8  b;
 106
 107         b = read_pci_config_byte(num, slot, func, 0xac);
 108         b &= ~(1<<5);
 109         write_pci_config_byte(num, slot, func, 0xac, b);
 110
 111         d = read_pci_config(num, slot, func, 0x70);
 112         d |= 1<<8;
 113         write_pci_config(num, slot, func, 0x70, d);
 114
 115         d = read_pci_config(num, slot, func, 0x8);
 116         d &= 0xff;
 117         return d;
 118 }
 119
 120 static void __init ati_bugs(int num, int slot, int func)
 121 {
 122         u32 d;
 123         u8  b;
 124
 125         if (acpi_use_timer_override)
 126                 return;
 127
 128         d = ati_ixp4x0_rev(num, slot, func);
 129         if (d  < 0x82)
 130                 acpi_skip_timer_override = 1;
 131         else {
 132                 /* check for IRQ0 interrupt swap */
 133                 outb(0x72, 0xcd6); b = inb(0xcd7);
 134                 if (!(b & 0x2))
 135                         acpi_skip_timer_override = 1;
 136         }
 137
 138         if (acpi_skip_timer_override) {
 139                 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
 140                 printk(KERN_INFO "Ignoring ACPI timer override.\n");
 141                 printk(KERN_INFO "If you got timer trouble "
 142                        "try acpi_use_timer_override\n");
 143         }
 144 }
 145
 146 static u32 __init ati_sbx00_rev(int num, int slot, int func)
 147 {
 148         u32 d;
 149
 150         d = read_pci_config(num, slot, func, 0x8);
 151         d &= 0xff;
 152
 153         return d;
 154 }
 155
 156 static void __init ati_bugs_contd(int num, int slot, int func)
 157 {
 158         u32 d, rev;
 159
 160         rev = ati_sbx00_rev(num, slot, func);
 161         if (rev >= 0x40)
 162                 acpi_fix_pin2_polarity = 1;
 163
 164         /*
 165          * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
 166          * SB700: revisions 0x39, 0x3a, ...
 167          * SB800: revisions 0x40, 0x41, ...
 168          */
 169         if (rev >= 0x39)
 170                 return;
 171
 172         if (acpi_use_timer_override)
 173                 return;
 174
 175         /* check for IRQ0 interrupt swap */
 176         d = read_pci_config(num, slot, func, 0x64);
 177         if (!(d & (1<<14)))
 178                 acpi_skip_timer_override = 1;
 179
 180         if (acpi_skip_timer_override) {
 181                 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
 182                 printk(KERN_INFO "Ignoring ACPI timer override.\n");
 183                 printk(KERN_INFO "If you got timer trouble "
 184                        "try acpi_use_timer_override\n");
 185         }
 186 }
 187 #else
 188 static void __init ati_bugs(int num, int slot, int func)
 189 {
 190 }
 191
 192 static void __init ati_bugs_contd(int num, int slot, int func)
 193 {
 194 }
 195 #endif
 196
 197 static void __init intel_remapping_check(int num, int slot, int func)
 198 {
 199         u8 revision;
 200         u16 device;
 201
 202         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
 203         revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
 204
 205         /*
 206          * Revision 13 of all triggering devices id in this quirk have
 207          * a problem draining interrupts when irq remapping is enabled,
 208          * and should be flagged as broken.  Additionally revisions 0x12
 209          * and 0x22 of device id 0x3405 has this problem.
 210          */
 211         if (revision == 0x13)
 212                 set_irq_remapping_broken();
 213         else if ((device == 0x3405) &&
 214             ((revision == 0x12) ||
 215              (revision == 0x22)))
 216                 set_irq_remapping_broken();
 217
 218 }
 219
 220 /*
 221  * Systems with Intel graphics controllers set aside memory exclusively
 222  * for gfx driver use.  This memory is not marked in the E820 as reserved
 223  * or as RAM, and so is subject to overlap from E820 manipulation later
 224  * in the boot process.  On some systems, MMIO space is allocated on top,
 225  * despite the efforts of the "RAM buffer" approach, which simply rounds
 226  * memory boundaries up to 64M to try to catch space that may decode
 227  * as RAM and so is not suitable for MMIO.
 228  *
 229  * And yes, so far on current devices the base addr is always under 4G.
 230  */
 231 static u32 __init intel_stolen_base(int num, int slot, int func)
 232 {
 233         u32 base;
 234
 235         /*
 236          * For the PCI IDs in this quirk, the stolen base is always
 237          * in 0x5c, aka the BDSM register (yes that's really what
 238          * it's called).
 239          */
 240         base = read_pci_config(num, slot, func, 0x5c);
 241         base &= ~((1<<20) - 1);
 242
 243         return base;
 244 }
 245
 246 #define KB(x)   ((x) * 1024)
 247 #define MB(x)   (KB (KB (x)))
 248 #define GB(x)   (MB (KB (x)))
 249
 250 static size_t __init gen3_stolen_size(int num, int slot, int func)
 251 {
 252         size_t stolen_size;
 253         u16 gmch_ctrl;
 254
 255         gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
 256
 257         switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 258         case I855_GMCH_GMS_STOLEN_1M:
 259                 stolen_size = MB(1);
 260                 break;
 261         case I855_GMCH_GMS_STOLEN_4M:
 262                 stolen_size = MB(4);
 263                 break;
 264         case I855_GMCH_GMS_STOLEN_8M:
 265                 stolen_size = MB(8);
 266                 break;
 267         case I855_GMCH_GMS_STOLEN_16M:
 268                 stolen_size = MB(16);
 269                 break;
 270         case I855_GMCH_GMS_STOLEN_32M:
 271                 stolen_size = MB(32);
 272                 break;
 273         case I915_GMCH_GMS_STOLEN_48M:
 274                 stolen_size = MB(48);
 275                 break;
 276         case I915_GMCH_GMS_STOLEN_64M:
 277                 stolen_size = MB(64);
 278                 break;
 279         case G33_GMCH_GMS_STOLEN_128M:
 280                 stolen_size = MB(128);
 281                 break;
 282         case G33_GMCH_GMS_STOLEN_256M:
 283                 stolen_size = MB(256);
 284                 break;
 285         case INTEL_GMCH_GMS_STOLEN_96M:
 286                 stolen_size = MB(96);
 287                 break;
 288         case INTEL_GMCH_GMS_STOLEN_160M:
 289                 stolen_size = MB(160);
 290                 break;
 291         case INTEL_GMCH_GMS_STOLEN_224M:
 292                 stolen_size = MB(224);
 293                 break;
 294         case INTEL_GMCH_GMS_STOLEN_352M:
 295                 stolen_size = MB(352);
 296                 break;
 297         default:
 298                 stolen_size = 0;
 299                 break;
 300         }
 301
 302         return stolen_size;
 303 }
 304
 305 static size_t __init gen6_stolen_size(int num, int slot, int func)
 306 {
 307         u16 gmch_ctrl;
 308
 309         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
 310         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
 311         gmch_ctrl &= SNB_GMCH_GMS_MASK;
 312
 313         return gmch_ctrl << 25; /* 32 MB units */
 314 }
 315
 316 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
 317
 318 static struct pci_device_id intel_stolen_ids[] __initdata = {
 319         INTEL_I915G_IDS(gen3_stolen_size),
 320         INTEL_I915GM_IDS(gen3_stolen_size),
 321         INTEL_I945G_IDS(gen3_stolen_size),
 322         INTEL_I945GM_IDS(gen3_stolen_size),
 323         INTEL_VLV_M_IDS(gen3_stolen_size),
 324         INTEL_VLV_D_IDS(gen3_stolen_size),
 325         INTEL_PINEVIEW_IDS(gen3_stolen_size),
 326         INTEL_I965G_IDS(gen3_stolen_size),
 327         INTEL_G33_IDS(gen3_stolen_size),
 328         INTEL_I965GM_IDS(gen3_stolen_size),
 329         INTEL_GM45_IDS(gen3_stolen_size),
 330         INTEL_G45_IDS(gen3_stolen_size),
 331         INTEL_IRONLAKE_D_IDS(gen3_stolen_size),
 332         INTEL_IRONLAKE_M_IDS(gen3_stolen_size),
 333         INTEL_SNB_D_IDS(gen6_stolen_size),
 334         INTEL_SNB_M_IDS(gen6_stolen_size),
 335         INTEL_IVB_M_IDS(gen6_stolen_size),
 336         INTEL_IVB_D_IDS(gen6_stolen_size),
 337         INTEL_HSW_D_IDS(gen6_stolen_size),
 338         INTEL_HSW_M_IDS(gen6_stolen_size),
 339 };
 340
 341 static void __init intel_graphics_stolen(int num, int slot, int func)
 342 {
 343         size_t size;
 344         int i;
 345         u32 start;
 346         u16 device, subvendor, subdevice;
 347
 348         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
 349         subvendor = read_pci_config_16(num, slot, func,
 350                                        PCI_SUBSYSTEM_VENDOR_ID);
 351         subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
 352
 353         for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
 354                 if (intel_stolen_ids[i].device == device) {
 355                         stolen_size_fn stolen_size =
 356                                 (stolen_size_fn)intel_stolen_ids[i].driver_data;
 357                         size = stolen_size(num, slot, func);
 358                         start = intel_stolen_base(num, slot, func);
 359                         if (size && start) {
 360                                 /* Mark this space as reserved */
 361                                 e820_add_region(start, size, E820_RESERVED);
 362                                 sanitize_e820_map(e820.map,
 363                                                   ARRAY_SIZE(e820.map),
 364                                                   &e820.nr_map);
 365                         }
 366                         return;
 367                 }
 368         }
 369 }
 370
 371 #define QFLAG_APPLY_ONCE        0x1
 372 #define QFLAG_APPLIED           0x2
 373 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
 374 struct chipset {
 375         u32 vendor;
 376         u32 device;
 377         u32 class;
 378         u32 class_mask;
 379         u32 flags;
 380         void (*f)(int num, int slot, int func);
 381 };
 382
 383 /*
 384  * Only works for devices on the root bus. If you add any devices
 385  * not on bus 0 readd another loop level in early_quirks(). But
 386  * be careful because at least the Nvidia quirk here relies on
 387  * only matching on bus 0.
 388  */
 389 static struct chipset early_qrk[] __initdata = {
 390         { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
 391           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
 392         { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
 393           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
 394         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
 395           PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
 396         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
 397           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
 398         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 399           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
 400         { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
 401           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
 402         { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
 403           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
 404         { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
 405           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
 406         { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
 407           QFLAG_APPLY_ONCE, intel_graphics_stolen },
 408         {}
 409 };
 410
 411 /**
 412  * check_dev_quirk - apply early quirks to a given PCI device
 413  * @num: bus number
 414  * @slot: slot number
 415  * @func: PCI function
 416  *
 417  * Check the vendor & device ID against the early quirks table.
 418  *
 419  * If the device is single function, let early_quirks() know so we don't
 420  * poke at this device again.
 421  */
 422 static int __init check_dev_quirk(int num, int slot, int func)
 423 {
 424         u16 class;
 425         u16 vendor;
 426         u16 device;
 427         u8 type;
 428         int i;
 429
 430         class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
 431
 432         if (class == 0xffff)
 433                 return -1; /* no class, treat as single function */
 434
 435         vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
 436
 437         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
 438
 439         for (i = 0; early_qrk[i].f != NULL; i++) {
 440                 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
 441                         (early_qrk[i].vendor == vendor)) &&
 442                         ((early_qrk[i].device == PCI_ANY_ID) ||
 443                         (early_qrk[i].device == device)) &&
 444                         (!((early_qrk[i].class ^ class) &
 445                             early_qrk[i].class_mask))) {
 446                                 if ((early_qrk[i].flags &
 447                                      QFLAG_DONE) != QFLAG_DONE)
 448                                         early_qrk[i].f(num, slot, func);
 449                                 early_qrk[i].flags |= QFLAG_APPLIED;
 450                         }
 451         }
 452
 453         type = read_pci_config_byte(num, slot, func,
 454                                     PCI_HEADER_TYPE);
 455         if (!(type & 0x80))
 456                 return -1;
 457
 458         return 0;
 459 }
 460
 461 void __init early_quirks(void)
 462 {
 463         int slot, func;
 464
 465         if (!early_pci_allowed())
 466                 return;
 467
 468         /* Poor man's PCI discovery */
 469         /* Only scan the root bus */
 470         for (slot = 0; slot < 32; slot++)
 471                 for (func = 0; func < 8; func++) {
 472                         /* Only probe function 0 on single fn devices */
 473                         if (check_dev_quirk(0, slot, func))
 474                                 break;
 475                 }
 476 }