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MIPS: Also verify sizeof `elf_fpreg_t' with PTRACE_SETREGSET
[linux/fpc-iii.git] / arch / mips / kernel / ptrace.c
blobaa92e131de57f65f461332bfceed0705bcebba2b
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 Ross Biro
7 * Copyright (C) Linus Torvalds
8 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
9 * Copyright (C) 1996 David S. Miller
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 1999 MIPS Technologies, Inc.
12 * Copyright (C) 2000 Ulf Carlsson
13 *
14 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
15 * binaries.
16 */
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/elf.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/mm.h>
23 #include <linux/errno.h>
24 #include <linux/ptrace.h>
25 #include <linux/regset.h>
26 #include <linux/smp.h>
27 #include <linux/security.h>
28 #include <linux/stddef.h>
29 #include <linux/tracehook.h>
30 #include <linux/audit.h>
31 #include <linux/seccomp.h>
32 #include <linux/ftrace.h>
33
34 #include <asm/byteorder.h>
35 #include <asm/cpu.h>
36 #include <asm/cpu-info.h>
37 #include <asm/dsp.h>
38 #include <asm/fpu.h>
39 #include <asm/mipsregs.h>
40 #include <asm/mipsmtregs.h>
41 #include <asm/pgtable.h>
42 #include <asm/page.h>
43 #include <asm/syscall.h>
44 #include <asm/uaccess.h>
45 #include <asm/bootinfo.h>
46 #include <asm/reg.h>
47
48 #define CREATE_TRACE_POINTS
49 #include <trace/events/syscalls.h>
50
51 static void init_fp_ctx(struct task_struct *target)
52 {
53 /* If FP has been used then the target already has context */
54 if (tsk_used_math(target))
55 return;
56
57 /* Begin with data registers set to all 1s... */
58 memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
59
60 /* FCSR has been preset by `mips_set_personality_nan'. */
61
62 /*
63 * Record that the target has "used" math, such that the context
64 * just initialised, and any modifications made by the caller,
65 * aren't discarded.
66 */
67 set_stopped_child_used_math(target);
68 }
69
70 /*
71 * Called by kernel/ptrace.c when detaching..
72 *
73 * Make sure single step bits etc are not set.
74 */
75 void ptrace_disable(struct task_struct *child)
76 {
77 /* Don't load the watchpoint registers for the ex-child. */
78 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
79 }
80
81 /*
82 * Poke at FCSR according to its mask. Don't set the cause bits as
83 * this is currently not handled correctly in FP context restoration
84 * and will cause an oops if a corresponding enable bit is set.
85 */
86 static void ptrace_setfcr31(struct task_struct *child, u32 value)
87 {
88 u32 fcr31;
89 u32 mask;
90
91 value &= ~FPU_CSR_ALL_X;
92 fcr31 = child->thread.fpu.fcr31;
93 mask = boot_cpu_data.fpu_msk31;
94 child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
95 }
96
97 /*
98 * Read a general register set. We always use the 64-bit format, even
99 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
100 * Registers are sign extended to fill the available space.
101 */
102 int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data)
103 {
104 struct pt_regs *regs;
105 int i;
106
107 if (!access_ok(VERIFY_WRITE, data, 38 * 8))
108 return -EIO;
109
110 regs = task_pt_regs(child);
111
112 for (i = 0; i < 32; i++)
113 __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]);
114 __put_user((long)regs->lo, (__s64 __user *)&data->lo);
115 __put_user((long)regs->hi, (__s64 __user *)&data->hi);
116 __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
117 __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr);
118 __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status);
119 __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause);
120
121 return 0;
122 }
123
124 /*
125 * Write a general register set. As for PTRACE_GETREGS, we always use
126 * the 64-bit format. On a 32-bit kernel only the lower order half
127 * (according to endianness) will be used.
128 */
129 int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
130 {
131 struct pt_regs *regs;
132 int i;
133
134 if (!access_ok(VERIFY_READ, data, 38 * 8))
135 return -EIO;
136
137 regs = task_pt_regs(child);
138
139 for (i = 0; i < 32; i++)
140 __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]);
141 __get_user(regs->lo, (__s64 __user *)&data->lo);
142 __get_user(regs->hi, (__s64 __user *)&data->hi);
143 __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
144
145 /* badvaddr, status, and cause may not be written. */
146
147 return 0;
148 }
149
150 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
151 {
152 int i;
153
154 if (!access_ok(VERIFY_WRITE, data, 33 * 8))
155 return -EIO;
156
157 if (tsk_used_math(child)) {
158 union fpureg *fregs = get_fpu_regs(child);
159 for (i = 0; i < 32; i++)
160 __put_user(get_fpr64(&fregs[i], 0),
161 i + (__u64 __user *)data);
162 } else {
163 for (i = 0; i < 32; i++)
164 __put_user((__u64) -1, i + (__u64 __user *) data);
165 }
166
167 __put_user(child->thread.fpu.fcr31, data + 64);
168 __put_user(boot_cpu_data.fpu_id, data + 65);
169
170 return 0;
171 }
172
173 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
174 {
175 union fpureg *fregs;
176 u64 fpr_val;
177 u32 value;
178 int i;
179
180 if (!access_ok(VERIFY_READ, data, 33 * 8))
181 return -EIO;
182
183 init_fp_ctx(child);
184 fregs = get_fpu_regs(child);
185
186 for (i = 0; i < 32; i++) {
187 __get_user(fpr_val, i + (__u64 __user *)data);
188 set_fpr64(&fregs[i], 0, fpr_val);
189 }
190
191 __get_user(value, data + 64);
192 ptrace_setfcr31(child, value);
193
194 /* FIR may not be written. */
195
196 return 0;
197 }
198
199 int ptrace_get_watch_regs(struct task_struct *child,
200 struct pt_watch_regs __user *addr)
201 {
202 enum pt_watch_style style;
203 int i;
204
205 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
206 return -EIO;
207 if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
208 return -EIO;
209
210 #ifdef CONFIG_32BIT
211 style = pt_watch_style_mips32;
212 #define WATCH_STYLE mips32
213 #else
214 style = pt_watch_style_mips64;
215 #define WATCH_STYLE mips64
216 #endif
217
218 __put_user(style, &addr->style);
219 __put_user(boot_cpu_data.watch_reg_use_cnt,
220 &addr->WATCH_STYLE.num_valid);
221 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
222 __put_user(child->thread.watch.mips3264.watchlo[i],
223 &addr->WATCH_STYLE.watchlo[i]);
224 __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
225 &addr->WATCH_STYLE.watchhi[i]);
226 __put_user(boot_cpu_data.watch_reg_masks[i],
227 &addr->WATCH_STYLE.watch_masks[i]);
228 }
229 for (; i < 8; i++) {
230 __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
231 __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
232 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
233 }
234
235 return 0;
236 }
237
238 int ptrace_set_watch_regs(struct task_struct *child,
239 struct pt_watch_regs __user *addr)
240 {
241 int i;
242 int watch_active = 0;
243 unsigned long lt[NUM_WATCH_REGS];
244 u16 ht[NUM_WATCH_REGS];
245
246 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
247 return -EIO;
248 if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
249 return -EIO;
250 /* Check the values. */
251 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
252 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
253 #ifdef CONFIG_32BIT
254 if (lt[i] & __UA_LIMIT)
255 return -EINVAL;
256 #else
257 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
258 if (lt[i] & 0xffffffff80000000UL)
259 return -EINVAL;
260 } else {
261 if (lt[i] & __UA_LIMIT)
262 return -EINVAL;
263 }
264 #endif
265 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
266 if (ht[i] & ~0xff8)
267 return -EINVAL;
268 }
269 /* Install them. */
270 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
271 if (lt[i] & 7)
272 watch_active = 1;
273 child->thread.watch.mips3264.watchlo[i] = lt[i];
274 /* Set the G bit. */
275 child->thread.watch.mips3264.watchhi[i] = ht[i];
276 }
277
278 if (watch_active)
279 set_tsk_thread_flag(child, TIF_LOAD_WATCH);
280 else
281 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
282
283 return 0;
284 }
285
286 /* regset get/set implementations */
287
288 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
289
290 static int gpr32_get(struct task_struct *target,
291 const struct user_regset *regset,
292 unsigned int pos, unsigned int count,
293 void *kbuf, void __user *ubuf)
294 {
295 struct pt_regs *regs = task_pt_regs(target);
296 u32 uregs[ELF_NGREG] = {};
297 unsigned i;
298
299 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
300 /* k0/k1 are copied as zero. */
301 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
302 continue;
303
304 uregs[i] = regs->regs[i - MIPS32_EF_R0];
305 }
306
307 uregs[MIPS32_EF_LO] = regs->lo;
308 uregs[MIPS32_EF_HI] = regs->hi;
309 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
310 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
311 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
312 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
313
314 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
315 sizeof(uregs));
316 }
317
318 static int gpr32_set(struct task_struct *target,
319 const struct user_regset *regset,
320 unsigned int pos, unsigned int count,
321 const void *kbuf, const void __user *ubuf)
322 {
323 struct pt_regs *regs = task_pt_regs(target);
324 u32 uregs[ELF_NGREG];
325 unsigned start, num_regs, i;
326 int err;
327
328 start = pos / sizeof(u32);
329 num_regs = count / sizeof(u32);
330
331 if (start + num_regs > ELF_NGREG)
332 return -EIO;
333
334 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
335 sizeof(uregs));
336 if (err)
337 return err;
338
339 for (i = start; i < num_regs; i++) {
340 /*
341 * Cast all values to signed here so that if this is a 64-bit
342 * kernel, the supplied 32-bit values will be sign extended.
343 */
344 switch (i) {
345 case MIPS32_EF_R1 ... MIPS32_EF_R25:
346 /* k0/k1 are ignored. */
347 case MIPS32_EF_R28 ... MIPS32_EF_R31:
348 regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i];
349 break;
350 case MIPS32_EF_LO:
351 regs->lo = (s32)uregs[i];
352 break;
353 case MIPS32_EF_HI:
354 regs->hi = (s32)uregs[i];
355 break;
356 case MIPS32_EF_CP0_EPC:
357 regs->cp0_epc = (s32)uregs[i];
358 break;
359 }
360 }
361
362 return 0;
363 }
364
365 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
366
367 #ifdef CONFIG_64BIT
368
369 static int gpr64_get(struct task_struct *target,
370 const struct user_regset *regset,
371 unsigned int pos, unsigned int count,
372 void *kbuf, void __user *ubuf)
373 {
374 struct pt_regs *regs = task_pt_regs(target);
375 u64 uregs[ELF_NGREG] = {};
376 unsigned i;
377
378 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
379 /* k0/k1 are copied as zero. */
380 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
381 continue;
382
383 uregs[i] = regs->regs[i - MIPS64_EF_R0];
384 }
385
386 uregs[MIPS64_EF_LO] = regs->lo;
387 uregs[MIPS64_EF_HI] = regs->hi;
388 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
389 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
390 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
391 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
392
393 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
394 sizeof(uregs));
395 }
396
397 static int gpr64_set(struct task_struct *target,
398 const struct user_regset *regset,
399 unsigned int pos, unsigned int count,
400 const void *kbuf, const void __user *ubuf)
401 {
402 struct pt_regs *regs = task_pt_regs(target);
403 u64 uregs[ELF_NGREG];
404 unsigned start, num_regs, i;
405 int err;
406
407 start = pos / sizeof(u64);
408 num_regs = count / sizeof(u64);
409
410 if (start + num_regs > ELF_NGREG)
411 return -EIO;
412
413 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
414 sizeof(uregs));
415 if (err)
416 return err;
417
418 for (i = start; i < num_regs; i++) {
419 switch (i) {
420 case MIPS64_EF_R1 ... MIPS64_EF_R25:
421 /* k0/k1 are ignored. */
422 case MIPS64_EF_R28 ... MIPS64_EF_R31:
423 regs->regs[i - MIPS64_EF_R0] = uregs[i];
424 break;
425 case MIPS64_EF_LO:
426 regs->lo = uregs[i];
427 break;
428 case MIPS64_EF_HI:
429 regs->hi = uregs[i];
430 break;
431 case MIPS64_EF_CP0_EPC:
432 regs->cp0_epc = uregs[i];
433 break;
434 }
435 }
436
437 return 0;
438 }
439
440 #endif /* CONFIG_64BIT */
441
442 /*
443 * Copy the floating-point context to the supplied NT_PRFPREG buffer,
444 * !CONFIG_CPU_HAS_MSA variant. FP context's general register slots
445 * correspond 1:1 to buffer slots. Only general registers are copied.
446 */
447 static int fpr_get_fpa(struct task_struct *target,
448 unsigned int *pos, unsigned int *count,
449 void **kbuf, void __user **ubuf)
450 {
451 return user_regset_copyout(pos, count, kbuf, ubuf,
452 &target->thread.fpu,
453 0, NUM_FPU_REGS * sizeof(elf_fpreg_t));
454 }
455
456 /*
457 * Copy the floating-point context to the supplied NT_PRFPREG buffer,
458 * CONFIG_CPU_HAS_MSA variant. Only lower 64 bits of FP context's
459 * general register slots are copied to buffer slots. Only general
460 * registers are copied.
461 */
462 static int fpr_get_msa(struct task_struct *target,
463 unsigned int *pos, unsigned int *count,
464 void **kbuf, void __user **ubuf)
465 {
466 unsigned int i;
467 u64 fpr_val;
468 int err;
469
470 BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));
471 for (i = 0; i < NUM_FPU_REGS; i++) {
472 fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
473 err = user_regset_copyout(pos, count, kbuf, ubuf,
474 &fpr_val, i * sizeof(elf_fpreg_t),
475 (i + 1) * sizeof(elf_fpreg_t));
476 if (err)
477 return err;
478 }
479
480 return 0;
481 }
482
483 /*
484 * Copy the floating-point context to the supplied NT_PRFPREG buffer.
485 * Choose the appropriate helper for general registers, and then copy
486 * the FCSR register separately.
487 */
488 static int fpr_get(struct task_struct *target,
489 const struct user_regset *regset,
490 unsigned int pos, unsigned int count,
491 void *kbuf, void __user *ubuf)
492 {
493 const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
494 int err;
495
496 if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
497 err = fpr_get_fpa(target, &pos, &count, &kbuf, &ubuf);
498 else
499 err = fpr_get_msa(target, &pos, &count, &kbuf, &ubuf);
500 if (err)
501 return err;
502
503 err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
504 &target->thread.fpu.fcr31,
505 fcr31_pos, fcr31_pos + sizeof(u32));
506
507 return err;
508 }
509
510 /*
511 * Copy the supplied NT_PRFPREG buffer to the floating-point context,
512 * !CONFIG_CPU_HAS_MSA variant. Buffer slots correspond 1:1 to FP
513 * context's general register slots. Only general registers are copied.
514 */
515 static int fpr_set_fpa(struct task_struct *target,
516 unsigned int *pos, unsigned int *count,
517 const void **kbuf, const void __user **ubuf)
518 {
519 return user_regset_copyin(pos, count, kbuf, ubuf,
520 &target->thread.fpu,
521 0, NUM_FPU_REGS * sizeof(elf_fpreg_t));
522 }
523
524 /*
525 * Copy the supplied NT_PRFPREG buffer to the floating-point context,
526 * CONFIG_CPU_HAS_MSA variant. Buffer slots are copied to lower 64
527 * bits only of FP context's general register slots. Only general
528 * registers are copied.
529 */
530 static int fpr_set_msa(struct task_struct *target,
531 unsigned int *pos, unsigned int *count,
532 const void **kbuf, const void __user **ubuf)
533 {
534 unsigned int i;
535 u64 fpr_val;
536 int err;
537
538 BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));
539 for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) {
540 err = user_regset_copyin(pos, count, kbuf, ubuf,
541 &fpr_val, i * sizeof(elf_fpreg_t),
542 (i + 1) * sizeof(elf_fpreg_t));
543 if (err)
544 return err;
545 set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
546 }
547
548 return 0;
549 }
550
551 /*
552 * Copy the supplied NT_PRFPREG buffer to the floating-point context.
553 * Choose the appropriate helper for general registers, and then copy
554 * the FCSR register separately.
555 *
556 * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',
557 * which is supposed to have been guaranteed by the kernel before
558 * calling us, e.g. in `ptrace_regset'. We enforce that requirement,
559 * so that we can safely avoid preinitializing temporaries for
560 * partial register writes.
561 */
562 static int fpr_set(struct task_struct *target,
563 const struct user_regset *regset,
564 unsigned int pos, unsigned int count,
565 const void *kbuf, const void __user *ubuf)
566 {
567 const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
568 u32 fcr31;
569 int err;
570
571 BUG_ON(count % sizeof(elf_fpreg_t));
572
573 init_fp_ctx(target);
574
575 if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
576 err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf);
577 else
578 err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf);
579 if (err)
580 return err;
581
582 if (count > 0) {
583 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
584 &fcr31,
585 fcr31_pos, fcr31_pos + sizeof(u32));
586 if (err)
587 return err;
588
589 ptrace_setfcr31(target, fcr31);
590 }
591
592 return err;
593 }
594
595 enum mips_regset {
596 REGSET_GPR,
597 REGSET_FPR,
598 };
599
600 struct pt_regs_offset {
601 const char *name;
602 int offset;
603 };
604
605 #define REG_OFFSET_NAME(reg, r) { \
606 .name = #reg, \
607 .offset = offsetof(struct pt_regs, r) \
608 }
609
610 #define REG_OFFSET_END { \
611 .name = NULL, \
612 .offset = 0 \
613 }
614
615 static const struct pt_regs_offset regoffset_table[] = {
616 REG_OFFSET_NAME(r0, regs[0]),
617 REG_OFFSET_NAME(r1, regs[1]),
618 REG_OFFSET_NAME(r2, regs[2]),
619 REG_OFFSET_NAME(r3, regs[3]),
620 REG_OFFSET_NAME(r4, regs[4]),
621 REG_OFFSET_NAME(r5, regs[5]),
622 REG_OFFSET_NAME(r6, regs[6]),
623 REG_OFFSET_NAME(r7, regs[7]),
624 REG_OFFSET_NAME(r8, regs[8]),
625 REG_OFFSET_NAME(r9, regs[9]),
626 REG_OFFSET_NAME(r10, regs[10]),
627 REG_OFFSET_NAME(r11, regs[11]),
628 REG_OFFSET_NAME(r12, regs[12]),
629 REG_OFFSET_NAME(r13, regs[13]),
630 REG_OFFSET_NAME(r14, regs[14]),
631 REG_OFFSET_NAME(r15, regs[15]),
632 REG_OFFSET_NAME(r16, regs[16]),
633 REG_OFFSET_NAME(r17, regs[17]),
634 REG_OFFSET_NAME(r18, regs[18]),
635 REG_OFFSET_NAME(r19, regs[19]),
636 REG_OFFSET_NAME(r20, regs[20]),
637 REG_OFFSET_NAME(r21, regs[21]),
638 REG_OFFSET_NAME(r22, regs[22]),
639 REG_OFFSET_NAME(r23, regs[23]),
640 REG_OFFSET_NAME(r24, regs[24]),
641 REG_OFFSET_NAME(r25, regs[25]),
642 REG_OFFSET_NAME(r26, regs[26]),
643 REG_OFFSET_NAME(r27, regs[27]),
644 REG_OFFSET_NAME(r28, regs[28]),
645 REG_OFFSET_NAME(r29, regs[29]),
646 REG_OFFSET_NAME(r30, regs[30]),
647 REG_OFFSET_NAME(r31, regs[31]),
648 REG_OFFSET_NAME(c0_status, cp0_status),
649 REG_OFFSET_NAME(hi, hi),
650 REG_OFFSET_NAME(lo, lo),
651 #ifdef CONFIG_CPU_HAS_SMARTMIPS
652 REG_OFFSET_NAME(acx, acx),
653 #endif
654 REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
655 REG_OFFSET_NAME(c0_cause, cp0_cause),
656 REG_OFFSET_NAME(c0_epc, cp0_epc),
657 #ifdef CONFIG_MIPS_MT_SMTC
658 REG_OFFSET_NAME(c0_tcstatus, cp0_tcstatus),
659 #endif
660 #ifdef CONFIG_CPU_CAVIUM_OCTEON
661 REG_OFFSET_NAME(mpl0, mpl[0]),
662 REG_OFFSET_NAME(mpl1, mpl[1]),
663 REG_OFFSET_NAME(mpl2, mpl[2]),
664 REG_OFFSET_NAME(mtp0, mtp[0]),
665 REG_OFFSET_NAME(mtp1, mtp[1]),
666 REG_OFFSET_NAME(mtp2, mtp[2]),
667 #endif
668 REG_OFFSET_END,
669 };
670
671 /**
672 * regs_query_register_offset() - query register offset from its name
673 * @name: the name of a register
674 *
675 * regs_query_register_offset() returns the offset of a register in struct
676 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
677 */
678 int regs_query_register_offset(const char *name)
679 {
680 const struct pt_regs_offset *roff;
681 for (roff = regoffset_table; roff->name != NULL; roff++)
682 if (!strcmp(roff->name, name))
683 return roff->offset;
684 return -EINVAL;
685 }
686
687 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
688
689 static const struct user_regset mips_regsets[] = {
690 [REGSET_GPR] = {
691 .core_note_type = NT_PRSTATUS,
692 .n = ELF_NGREG,
693 .size = sizeof(unsigned int),
694 .align = sizeof(unsigned int),
695 .get = gpr32_get,
696 .set = gpr32_set,
697 },
698 [REGSET_FPR] = {
699 .core_note_type = NT_PRFPREG,
700 .n = ELF_NFPREG,
701 .size = sizeof(elf_fpreg_t),
702 .align = sizeof(elf_fpreg_t),
703 .get = fpr_get,
704 .set = fpr_set,
705 },
706 };
707
708 static const struct user_regset_view user_mips_view = {
709 .name = "mips",
710 .e_machine = ELF_ARCH,
711 .ei_osabi = ELF_OSABI,
712 .regsets = mips_regsets,
713 .n = ARRAY_SIZE(mips_regsets),
714 };
715
716 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
717
718 #ifdef CONFIG_64BIT
719
720 static const struct user_regset mips64_regsets[] = {
721 [REGSET_GPR] = {
722 .core_note_type = NT_PRSTATUS,
723 .n = ELF_NGREG,
724 .size = sizeof(unsigned long),
725 .align = sizeof(unsigned long),
726 .get = gpr64_get,
727 .set = gpr64_set,
728 },
729 [REGSET_FPR] = {
730 .core_note_type = NT_PRFPREG,
731 .n = ELF_NFPREG,
732 .size = sizeof(elf_fpreg_t),
733 .align = sizeof(elf_fpreg_t),
734 .get = fpr_get,
735 .set = fpr_set,
736 },
737 };
738
739 static const struct user_regset_view user_mips64_view = {
740 .name = "mips64",
741 .e_machine = ELF_ARCH,
742 .ei_osabi = ELF_OSABI,
743 .regsets = mips64_regsets,
744 .n = ARRAY_SIZE(mips64_regsets),
745 };
746
747 #ifdef CONFIG_MIPS32_N32
748
749 static const struct user_regset_view user_mipsn32_view = {
750 .name = "mipsn32",
751 .e_flags = EF_MIPS_ABI2,
752 .e_machine = ELF_ARCH,
753 .ei_osabi = ELF_OSABI,
754 .regsets = mips64_regsets,
755 .n = ARRAY_SIZE(mips64_regsets),
756 };
757
758 #endif /* CONFIG_MIPS32_N32 */
759
760 #endif /* CONFIG_64BIT */
761
762 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
763 {
764 #ifdef CONFIG_32BIT
765 return &user_mips_view;
766 #else
767 #ifdef CONFIG_MIPS32_O32
768 if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
769 return &user_mips_view;
770 #endif
771 #ifdef CONFIG_MIPS32_N32
772 if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
773 return &user_mipsn32_view;
774 #endif
775 return &user_mips64_view;
776 #endif
777 }
778
779 long arch_ptrace(struct task_struct *child, long request,
780 unsigned long addr, unsigned long data)
781 {
782 int ret;
783 void __user *addrp = (void __user *) addr;
784 void __user *datavp = (void __user *) data;
785 unsigned long __user *datalp = (void __user *) data;
786
787 switch (request) {
788 /* when I and D space are separate, these will need to be fixed. */
789 case PTRACE_PEEKTEXT: /* read word at location addr. */
790 case PTRACE_PEEKDATA:
791 ret = generic_ptrace_peekdata(child, addr, data);
792 break;
793
794 /* Read the word at location addr in the USER area. */
795 case PTRACE_PEEKUSR: {
796 struct pt_regs *regs;
797 union fpureg *fregs;
798 unsigned long tmp = 0;
799
800 regs = task_pt_regs(child);
801 ret = 0; /* Default return value. */
802
803 switch (addr) {
804 case 0 ... 31:
805 tmp = regs->regs[addr];
806 break;
807 case FPR_BASE ... FPR_BASE + 31:
808 if (!tsk_used_math(child)) {
809 /* FP not yet used */
810 tmp = -1;
811 break;
812 }
813 fregs = get_fpu_regs(child);
814
815 #ifdef CONFIG_32BIT
816 if (test_thread_flag(TIF_32BIT_FPREGS)) {
817 /*
818 * The odd registers are actually the high
819 * order bits of the values stored in the even
820 * registers - unless we're using r2k_switch.S.
821 */
822 tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
823 addr & 1);
824 break;
825 }
826 #endif
827 tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
828 break;
829 case PC:
830 tmp = regs->cp0_epc;
831 break;
832 case CAUSE:
833 tmp = regs->cp0_cause;
834 break;
835 case BADVADDR:
836 tmp = regs->cp0_badvaddr;
837 break;
838 case MMHI:
839 tmp = regs->hi;
840 break;
841 case MMLO:
842 tmp = regs->lo;
843 break;
844 #ifdef CONFIG_CPU_HAS_SMARTMIPS
845 case ACX:
846 tmp = regs->acx;
847 break;
848 #endif
849 case FPC_CSR:
850 tmp = child->thread.fpu.fcr31;
851 break;
852 case FPC_EIR:
853 /* implementation / version register */
854 tmp = boot_cpu_data.fpu_id;
855 break;
856 case DSP_BASE ... DSP_BASE + 5: {
857 dspreg_t *dregs;
858
859 if (!cpu_has_dsp) {
860 tmp = 0;
861 ret = -EIO;
862 goto out;
863 }
864 dregs = __get_dsp_regs(child);
865 tmp = (unsigned long) (dregs[addr - DSP_BASE]);
866 break;
867 }
868 case DSP_CONTROL:
869 if (!cpu_has_dsp) {
870 tmp = 0;
871 ret = -EIO;
872 goto out;
873 }
874 tmp = child->thread.dsp.dspcontrol;
875 break;
876 default:
877 tmp = 0;
878 ret = -EIO;
879 goto out;
880 }
881 ret = put_user(tmp, datalp);
882 break;
883 }
884
885 /* when I and D space are separate, this will have to be fixed. */
886 case PTRACE_POKETEXT: /* write the word at location addr. */
887 case PTRACE_POKEDATA:
888 ret = generic_ptrace_pokedata(child, addr, data);
889 break;
890
891 case PTRACE_POKEUSR: {
892 struct pt_regs *regs;
893 ret = 0;
894 regs = task_pt_regs(child);
895
896 switch (addr) {
897 case 0 ... 31:
898 regs->regs[addr] = data;
899 break;
900 case FPR_BASE ... FPR_BASE + 31: {
901 union fpureg *fregs = get_fpu_regs(child);
902
903 init_fp_ctx(child);
904 #ifdef CONFIG_32BIT
905 if (test_thread_flag(TIF_32BIT_FPREGS)) {
906 /*
907 * The odd registers are actually the high
908 * order bits of the values stored in the even
909 * registers - unless we're using r2k_switch.S.
910 */
911 set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
912 addr & 1, data);
913 break;
914 }
915 #endif
916 set_fpr64(&fregs[addr - FPR_BASE], 0, data);
917 break;
918 }
919 case PC:
920 regs->cp0_epc = data;
921 break;
922 case MMHI:
923 regs->hi = data;
924 break;
925 case MMLO:
926 regs->lo = data;
927 break;
928 #ifdef CONFIG_CPU_HAS_SMARTMIPS
929 case ACX:
930 regs->acx = data;
931 break;
932 #endif
933 case FPC_CSR:
934 ptrace_setfcr31(child, data);
935 break;
936 case DSP_BASE ... DSP_BASE + 5: {
937 dspreg_t *dregs;
938
939 if (!cpu_has_dsp) {
940 ret = -EIO;
941 break;
942 }
943
944 dregs = __get_dsp_regs(child);
945 dregs[addr - DSP_BASE] = data;
946 break;
947 }
948 case DSP_CONTROL:
949 if (!cpu_has_dsp) {
950 ret = -EIO;
951 break;
952 }
953 child->thread.dsp.dspcontrol = data;
954 break;
955 default:
956 /* The rest are not allowed. */
957 ret = -EIO;
958 break;
959 }
960 break;
961 }
962
963 case PTRACE_GETREGS:
964 ret = ptrace_getregs(child, datavp);
965 break;
966
967 case PTRACE_SETREGS:
968 ret = ptrace_setregs(child, datavp);
969 break;
970
971 case PTRACE_GETFPREGS:
972 ret = ptrace_getfpregs(child, datavp);
973 break;
974
975 case PTRACE_SETFPREGS:
976 ret = ptrace_setfpregs(child, datavp);
977 break;
978
979 case PTRACE_GET_THREAD_AREA:
980 ret = put_user(task_thread_info(child)->tp_value, datalp);
981 break;
982
983 case PTRACE_GET_WATCH_REGS:
984 ret = ptrace_get_watch_regs(child, addrp);
985 break;
986
987 case PTRACE_SET_WATCH_REGS:
988 ret = ptrace_set_watch_regs(child, addrp);
989 break;
990
991 default:
992 ret = ptrace_request(child, request, addr, data);
993 break;
994 }
995 out:
996 return ret;
997 }
998
999 /*
1000 * Notification of system call entry/exit
1001 * - triggered by current->work.syscall_trace
1002 */
1003 asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
1004 {
1005 long ret = 0;
1006 user_exit();
1007
1008 current_thread_info()->syscall = syscall;
1009
1010 if (secure_computing() == -1)
1011 return -1;
1012
1013 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1014 tracehook_report_syscall_entry(regs))
1015 ret = -1;
1016
1017 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1018 trace_sys_enter(regs, regs->regs[2]);
1019
1020 audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
1021 regs->regs[6], regs->regs[7]);
1022 return syscall;
1023 }
1024
1025 /*
1026 * Notification of system call entry/exit
1027 * - triggered by current->work.syscall_trace
1028 */
1029 asmlinkage void syscall_trace_leave(struct pt_regs *regs)
1030 {
1031 /*
1032 * We may come here right after calling schedule_user()
1033 * or do_notify_resume(), in which case we can be in RCU
1034 * user mode.
1035 */
1036 user_exit();
1037
1038 audit_syscall_exit(regs);
1039
1040 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1041 trace_sys_exit(regs, regs_return_value(regs));
1042
1043 if (test_thread_flag(TIF_SYSCALL_TRACE))
1044 tracehook_report_syscall_exit(regs, 0);
1045
1046 user_enter();
1047 }
Linux with added FPC-III support