| blob | 98be7f0cd227019cbe6b6a07ad989327b8e36979 |
1 /*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
12 #include <linux/threads.h>
13 #include <asm/reg.h>
14 #include <asm/page.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/reg_a2.h>
21 #include <asm/exception-64e.h>
22 #include <asm/bug.h>
23 #include <asm/irqflags.h>
24 #include <asm/ptrace.h>
25 #include <asm/ppc-opcode.h>
26 #include <asm/mmu.h>
27 #include <asm/hw_irq.h>
29 /* XXX This will ultimately add space for a special exception save
30 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
31 * when taking special interrupts. For now we don't support that,
32 * special interrupts from within a non-standard level will probably
33 * blow you up
34 */
35 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
37 /* Exception prolog code for all exceptions */
38 #define EXCEPTION_PROLOG(n, type, addition) \
39 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
40 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
41 std r10,PACA_EX##type+EX_R10(r13); \
42 std r11,PACA_EX##type+EX_R11(r13); \
43 mfcr r10; /* save CR */ \
44 addition; /* additional code for that exc. */ \
45 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
46 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
47 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
48 type##_SET_KSTACK; /* get special stack if necessary */\
49 andi. r10,r11,MSR_PR; /* save stack pointer */ \
50 beq 1f; /* branch around if supervisor */ \
51 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
52 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
53 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
54 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
56 /* Exception type-specific macros */
57 #define GEN_SET_KSTACK \
58 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
59 #define SPRN_GEN_SRR0 SPRN_SRR0
60 #define SPRN_GEN_SRR1 SPRN_SRR1
62 #define CRIT_SET_KSTACK \
63 ld r1,PACA_CRIT_STACK(r13); \
64 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
65 #define SPRN_CRIT_SRR0 SPRN_CSRR0
66 #define SPRN_CRIT_SRR1 SPRN_CSRR1
68 #define DBG_SET_KSTACK \
69 ld r1,PACA_DBG_STACK(r13); \
70 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
71 #define SPRN_DBG_SRR0 SPRN_DSRR0
72 #define SPRN_DBG_SRR1 SPRN_DSRR1
74 #define MC_SET_KSTACK \
75 ld r1,PACA_MC_STACK(r13); \
76 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
77 #define SPRN_MC_SRR0 SPRN_MCSRR0
78 #define SPRN_MC_SRR1 SPRN_MCSRR1
80 #define NORMAL_EXCEPTION_PROLOG(n, addition) \
81 EXCEPTION_PROLOG(n, GEN, addition##_GEN(n))
83 #define CRIT_EXCEPTION_PROLOG(n, addition) \
84 EXCEPTION_PROLOG(n, CRIT, addition##_CRIT(n))
86 #define DBG_EXCEPTION_PROLOG(n, addition) \
87 EXCEPTION_PROLOG(n, DBG, addition##_DBG(n))
89 #define MC_EXCEPTION_PROLOG(n, addition) \
90 EXCEPTION_PROLOG(n, MC, addition##_MC(n))
93 /* Variants of the "addition" argument for the prolog
94 */
95 #define PROLOG_ADDITION_NONE_GEN(n)
96 #define PROLOG_ADDITION_NONE_CRIT(n)
97 #define PROLOG_ADDITION_NONE_DBG(n)
98 #define PROLOG_ADDITION_NONE_MC(n)
100 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
101 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
102 cmpwi cr0,r11,0; /* yes -> go out of line */ \
103 beq masked_interrupt_book3e_##n
105 #define PROLOG_ADDITION_2REGS_GEN(n) \
106 std r14,PACA_EXGEN+EX_R14(r13); \
107 std r15,PACA_EXGEN+EX_R15(r13)
109 #define PROLOG_ADDITION_1REG_GEN(n) \
110 std r14,PACA_EXGEN+EX_R14(r13);
112 #define PROLOG_ADDITION_2REGS_CRIT(n) \
113 std r14,PACA_EXCRIT+EX_R14(r13); \
114 std r15,PACA_EXCRIT+EX_R15(r13)
116 #define PROLOG_ADDITION_2REGS_DBG(n) \
117 std r14,PACA_EXDBG+EX_R14(r13); \
118 std r15,PACA_EXDBG+EX_R15(r13)
120 #define PROLOG_ADDITION_2REGS_MC(n) \
121 std r14,PACA_EXMC+EX_R14(r13); \
122 std r15,PACA_EXMC+EX_R15(r13)
125 /* Core exception code for all exceptions except TLB misses.
126 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
127 */
128 #define EXCEPTION_COMMON(n, excf, ints) \
129 exc_##n##_common: \
130 std r0,GPR0(r1); /* save r0 in stackframe */ \
131 std r2,GPR2(r1); /* save r2 in stackframe */ \
132 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
133 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
134 std r9,GPR9(r1); /* save r9 in stackframe */ \
135 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
136 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
137 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
138 ld r3,excf+EX_R10(r13); /* get back r10 */ \
139 ld r4,excf+EX_R11(r13); /* get back r11 */ \
140 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
141 std r12,GPR12(r1); /* save r12 in stackframe */ \
142 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
143 mflr r6; /* save LR in stackframe */ \
144 mfctr r7; /* save CTR in stackframe */ \
145 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
146 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
147 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
148 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
149 ld r12,exception_marker@toc(r2); \
150 li r0,0; \
151 std r3,GPR10(r1); /* save r10 to stackframe */ \
152 std r4,GPR11(r1); /* save r11 to stackframe */ \
153 std r5,GPR13(r1); /* save it to stackframe */ \
154 std r6,_LINK(r1); \
155 std r7,_CTR(r1); \
156 std r8,_XER(r1); \
157 li r3,(n)+1; /* indicate partial regs in trap */ \
158 std r9,0(r1); /* store stack frame back link */ \
159 std r10,_CCR(r1); /* store orig CR in stackframe */ \
160 std r9,GPR1(r1); /* store stack frame back link */ \
161 std r11,SOFTE(r1); /* and save it to stackframe */ \
162 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
163 std r3,_TRAP(r1); /* set trap number */ \
164 std r0,RESULT(r1); /* clear regs->result */ \
165 ints;
167 /* Variants for the "ints" argument. This one does nothing when we want
168 * to keep interrupts in their original state
169 */
170 #define INTS_KEEP
172 /* This second version is meant for exceptions that don't immediately
173 * hard-enable. We set a bit in paca->irq_happened to ensure that
174 * a subsequent call to arch_local_irq_restore() will properly
175 * hard-enable and avoid the fast-path
176 */
177 #define INTS_DISABLE SOFT_DISABLE_INTS(r3,r4)
179 /* This is called by exceptions that used INTS_KEEP (that did not touch
180 * irq indicators in the PACA). This will restore MSR:EE to it's previous
181 * value
182 *
183 * XXX In the long run, we may want to open-code it in order to separate the
184 * load from the wrtee, thus limiting the latency caused by the dependency
185 * but at this point, I'll favor code clarity until we have a near to final
186 * implementation
187 */
188 #define INTS_RESTORE_HARD \
189 ld r11,_MSR(r1); \
190 wrtee r11;
192 /* XXX FIXME: Restore r14/r15 when necessary */
193 #define BAD_STACK_TRAMPOLINE(n) \
194 exc_##n##_bad_stack: \
195 li r1,(n); /* get exception number */ \
196 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
197 b bad_stack_book3e; /* bad stack error */
199 /* WARNING: If you change the layout of this stub, make sure you chcek
200 * the debug exception handler which handles single stepping
201 * into exceptions from userspace, and the MM code in
202 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
203 * and would need to be updated if that branch is moved
204 */
205 #define EXCEPTION_STUB(loc, label) \
206 . = interrupt_base_book3e + loc; \
207 nop; /* To make debug interrupts happy */ \
208 b exc_##label##_book3e;
210 #define ACK_NONE(r)
211 #define ACK_DEC(r) \
212 lis r,TSR_DIS@h; \
213 mtspr SPRN_TSR,r
214 #define ACK_FIT(r) \
215 lis r,TSR_FIS@h; \
216 mtspr SPRN_TSR,r
218 /* Used by asynchronous interrupt that may happen in the idle loop.
219 *
220 * This check if the thread was in the idle loop, and if yes, returns
221 * to the caller rather than the PC. This is to avoid a race if
222 * interrupts happen before the wait instruction.
223 */
224 #define CHECK_NAPPING() \
225 CURRENT_THREAD_INFO(r11, r1); \
226 ld r10,TI_LOCAL_FLAGS(r11); \
227 andi. r9,r10,_TLF_NAPPING; \
228 beq+ 1f; \
229 ld r8,_LINK(r1); \
230 rlwinm r7,r10,0,~_TLF_NAPPING; \
231 std r8,_NIP(r1); \
232 std r7,TI_LOCAL_FLAGS(r11); \
233 1:
236 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
237 START_EXCEPTION(label); \
238 NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
239 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE) \
240 ack(r8); \
241 CHECK_NAPPING(); \
242 addi r3,r1,STACK_FRAME_OVERHEAD; \
243 bl hdlr; \
244 b .ret_from_except_lite;
246 /* This value is used to mark exception frames on the stack. */
247 .section ".toc","aw"
248 exception_marker:
249 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
252 /*
253 * And here we have the exception vectors !
254 */
256 .text
257 .balign 0x1000
258 .globl interrupt_base_book3e
259 interrupt_base_book3e: /* fake trap */
260 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
261 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
262 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
263 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
264 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
265 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
266 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
267 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
268 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
269 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
270 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
271 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
272 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
273 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
274 EXCEPTION_STUB(0x1c0, data_tlb_miss)
275 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
276 EXCEPTION_STUB(0x260, perfmon)
277 EXCEPTION_STUB(0x280, doorbell)
278 EXCEPTION_STUB(0x2a0, doorbell_crit)
279 EXCEPTION_STUB(0x2c0, guest_doorbell)
280 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
281 EXCEPTION_STUB(0x300, hypercall)
282 EXCEPTION_STUB(0x320, ehpriv)
284 .globl interrupt_end_book3e
285 interrupt_end_book3e:
287 /* Critical Input Interrupt */
288 START_EXCEPTION(critical_input);
289 CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
290 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
291 // bl special_reg_save_crit
292 // CHECK_NAPPING();
293 // addi r3,r1,STACK_FRAME_OVERHEAD
294 // bl .critical_exception
295 // b ret_from_crit_except
296 b .
298 /* Machine Check Interrupt */
299 START_EXCEPTION(machine_check);
300 CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
301 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
302 // bl special_reg_save_mc
303 // addi r3,r1,STACK_FRAME_OVERHEAD
304 // CHECK_NAPPING();
305 // bl .machine_check_exception
306 // b ret_from_mc_except
307 b .
309 /* Data Storage Interrupt */
310 START_EXCEPTION(data_storage)
311 NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
312 mfspr r14,SPRN_DEAR
313 mfspr r15,SPRN_ESR
314 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
315 b storage_fault_common
317 /* Instruction Storage Interrupt */
318 START_EXCEPTION(instruction_storage);
319 NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
320 li r15,0
321 mr r14,r10
322 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
323 b storage_fault_common
325 /* External Input Interrupt */
326 MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
328 /* Alignment */
329 START_EXCEPTION(alignment);
330 NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
331 mfspr r14,SPRN_DEAR
332 mfspr r15,SPRN_ESR
333 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
334 b alignment_more /* no room, go out of line */
336 /* Program Interrupt */
337 START_EXCEPTION(program);
338 NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
339 mfspr r14,SPRN_ESR
340 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
341 std r14,_DSISR(r1)
342 addi r3,r1,STACK_FRAME_OVERHEAD
343 ld r14,PACA_EXGEN+EX_R14(r13)
344 bl .save_nvgprs
345 bl .program_check_exception
346 b .ret_from_except
348 /* Floating Point Unavailable Interrupt */
349 START_EXCEPTION(fp_unavailable);
350 NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
351 /* we can probably do a shorter exception entry for that one... */
352 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
353 ld r12,_MSR(r1)
354 andi. r0,r12,MSR_PR;
355 beq- 1f
356 bl .load_up_fpu
357 b fast_exception_return
358 1: INTS_DISABLE
359 bl .save_nvgprs
360 addi r3,r1,STACK_FRAME_OVERHEAD
361 bl .kernel_fp_unavailable_exception
362 b .ret_from_except
364 /* Decrementer Interrupt */
365 MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
367 /* Fixed Interval Timer Interrupt */
368 MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
370 /* Watchdog Timer Interrupt */
371 START_EXCEPTION(watchdog);
372 CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
373 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
374 // bl special_reg_save_crit
375 // CHECK_NAPPING();
376 // addi r3,r1,STACK_FRAME_OVERHEAD
377 // bl .unknown_exception
378 // b ret_from_crit_except
379 b .
381 /* System Call Interrupt */
382 START_EXCEPTION(system_call)
383 mr r9,r13 /* keep a copy of userland r13 */
384 mfspr r11,SPRN_SRR0 /* get return address */
385 mfspr r12,SPRN_SRR1 /* get previous MSR */
386 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
387 b system_call_common
389 /* Auxiliary Processor Unavailable Interrupt */
390 START_EXCEPTION(ap_unavailable);
391 NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
392 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
393 bl .save_nvgprs
394 addi r3,r1,STACK_FRAME_OVERHEAD
395 bl .unknown_exception
396 b .ret_from_except
398 /* Debug exception as a critical interrupt*/
399 START_EXCEPTION(debug_crit);
400 CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
402 /*
403 * If there is a single step or branch-taken exception in an
404 * exception entry sequence, it was probably meant to apply to
405 * the code where the exception occurred (since exception entry
406 * doesn't turn off DE automatically). We simulate the effect
407 * of turning off DE on entry to an exception handler by turning
408 * off DE in the CSRR1 value and clearing the debug status.
409 */
411 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
412 andis. r15,r14,DBSR_IC@h
413 beq+ 1f
415 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
416 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
417 cmpld cr0,r10,r14
418 cmpld cr1,r10,r15
419 blt+ cr0,1f
420 bge+ cr1,1f
422 /* here it looks like we got an inappropriate debug exception. */
423 lis r14,DBSR_IC@h /* clear the IC event */
424 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
425 mtspr SPRN_DBSR,r14
426 mtspr SPRN_CSRR1,r11
427 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
428 ld r1,PACA_EXCRIT+EX_R1(r13)
429 ld r14,PACA_EXCRIT+EX_R14(r13)
430 ld r15,PACA_EXCRIT+EX_R15(r13)
431 mtcr r10
432 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
433 ld r11,PACA_EXCRIT+EX_R11(r13)
434 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
435 rfci
437 /* Normal debug exception */
438 /* XXX We only handle coming from userspace for now since we can't
439 * quite save properly an interrupted kernel state yet
440 */
441 1: andi. r14,r11,MSR_PR; /* check for userspace again */
442 beq kernel_dbg_exc; /* if from kernel mode */
444 /* Now we mash up things to make it look like we are coming on a
445 * normal exception
446 */
447 mfspr r15,SPRN_SPRG_CRIT_SCRATCH
448 mtspr SPRN_SPRG_GEN_SCRATCH,r15
449 mfspr r14,SPRN_DBSR
450 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
451 std r14,_DSISR(r1)
452 addi r3,r1,STACK_FRAME_OVERHEAD
453 mr r4,r14
454 ld r14,PACA_EXCRIT+EX_R14(r13)
455 ld r15,PACA_EXCRIT+EX_R15(r13)
456 bl .save_nvgprs
457 bl .DebugException
458 b .ret_from_except
460 kernel_dbg_exc:
461 b . /* NYI */
463 /* Debug exception as a debug interrupt*/
464 START_EXCEPTION(debug_debug);
465 DBG_EXCEPTION_PROLOG(0xd08, PROLOG_ADDITION_2REGS)
467 /*
468 * If there is a single step or branch-taken exception in an
469 * exception entry sequence, it was probably meant to apply to
470 * the code where the exception occurred (since exception entry
471 * doesn't turn off DE automatically). We simulate the effect
472 * of turning off DE on entry to an exception handler by turning
473 * off DE in the DSRR1 value and clearing the debug status.
474 */
476 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
477 andis. r15,r14,DBSR_IC@h
478 beq+ 1f
480 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
481 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
482 cmpld cr0,r10,r14
483 cmpld cr1,r10,r15
484 blt+ cr0,1f
485 bge+ cr1,1f
487 /* here it looks like we got an inappropriate debug exception. */
488 lis r14,DBSR_IC@h /* clear the IC event */
489 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
490 mtspr SPRN_DBSR,r14
491 mtspr SPRN_DSRR1,r11
492 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
493 ld r1,PACA_EXDBG+EX_R1(r13)
494 ld r14,PACA_EXDBG+EX_R14(r13)
495 ld r15,PACA_EXDBG+EX_R15(r13)
496 mtcr r10
497 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
498 ld r11,PACA_EXDBG+EX_R11(r13)
499 mfspr r13,SPRN_SPRG_DBG_SCRATCH
500 rfdi
502 /* Normal debug exception */
503 /* XXX We only handle coming from userspace for now since we can't
504 * quite save properly an interrupted kernel state yet
505 */
506 1: andi. r14,r11,MSR_PR; /* check for userspace again */
507 beq kernel_dbg_exc; /* if from kernel mode */
509 /* Now we mash up things to make it look like we are coming on a
510 * normal exception
511 */
512 mfspr r15,SPRN_SPRG_DBG_SCRATCH
513 mtspr SPRN_SPRG_GEN_SCRATCH,r15
514 mfspr r14,SPRN_DBSR
515 EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE)
516 std r14,_DSISR(r1)
517 addi r3,r1,STACK_FRAME_OVERHEAD
518 mr r4,r14
519 ld r14,PACA_EXDBG+EX_R14(r13)
520 ld r15,PACA_EXDBG+EX_R15(r13)
521 bl .save_nvgprs
522 bl .DebugException
523 b .ret_from_except
525 START_EXCEPTION(perfmon);
526 NORMAL_EXCEPTION_PROLOG(0x260, PROLOG_ADDITION_NONE)
527 EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
528 addi r3,r1,STACK_FRAME_OVERHEAD
529 bl .performance_monitor_exception
530 b .ret_from_except_lite
532 /* Doorbell interrupt */
533 MASKABLE_EXCEPTION(0x280, doorbell, .doorbell_exception, ACK_NONE)
535 /* Doorbell critical Interrupt */
536 START_EXCEPTION(doorbell_crit);
537 CRIT_EXCEPTION_PROLOG(0x2a0, PROLOG_ADDITION_NONE)
538 // EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
539 // bl special_reg_save_crit
540 // CHECK_NAPPING();
541 // addi r3,r1,STACK_FRAME_OVERHEAD
542 // bl .doorbell_critical_exception
543 // b ret_from_crit_except
544 b .
546 /* Guest Doorbell */
547 MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
549 /* Guest Doorbell critical Interrupt */
550 START_EXCEPTION(guest_doorbell_crit);
551 CRIT_EXCEPTION_PROLOG(0x2e0, PROLOG_ADDITION_NONE)
552 // EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
553 // bl special_reg_save_crit
554 // CHECK_NAPPING();
555 // addi r3,r1,STACK_FRAME_OVERHEAD
556 // bl .guest_doorbell_critical_exception
557 // b ret_from_crit_except
558 b .
560 /* Hypervisor call */
561 START_EXCEPTION(hypercall);
562 NORMAL_EXCEPTION_PROLOG(0x310, PROLOG_ADDITION_NONE)
563 EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
564 addi r3,r1,STACK_FRAME_OVERHEAD
565 bl .save_nvgprs
566 INTS_RESTORE_HARD
567 bl .unknown_exception
568 b .ret_from_except
570 /* Embedded Hypervisor priviledged */
571 START_EXCEPTION(ehpriv);
572 NORMAL_EXCEPTION_PROLOG(0x320, PROLOG_ADDITION_NONE)
573 EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
574 addi r3,r1,STACK_FRAME_OVERHEAD
575 bl .save_nvgprs
576 INTS_RESTORE_HARD
577 bl .unknown_exception
578 b .ret_from_except
580 /*
581 * An interrupt came in while soft-disabled; We mark paca->irq_happened
582 * accordingly and if the interrupt is level sensitive, we hard disable
583 */
585 masked_interrupt_book3e_0x500:
586 /* XXX When adding support for EPR, use PACA_IRQ_EE_EDGE */
587 li r11,PACA_IRQ_EE
588 b masked_interrupt_book3e_full_mask
590 masked_interrupt_book3e_0x900:
591 ACK_DEC(r11);
592 li r11,PACA_IRQ_DEC
593 b masked_interrupt_book3e_no_mask
594 masked_interrupt_book3e_0x980:
595 ACK_FIT(r11);
596 li r11,PACA_IRQ_DEC
597 b masked_interrupt_book3e_no_mask
598 masked_interrupt_book3e_0x280:
599 masked_interrupt_book3e_0x2c0:
600 li r11,PACA_IRQ_DBELL
601 b masked_interrupt_book3e_no_mask
603 masked_interrupt_book3e_no_mask:
604 mtcr r10
605 lbz r10,PACAIRQHAPPENED(r13)
606 or r10,r10,r11
607 stb r10,PACAIRQHAPPENED(r13)
608 b 1f
609 masked_interrupt_book3e_full_mask:
610 mtcr r10
611 lbz r10,PACAIRQHAPPENED(r13)
612 or r10,r10,r11
613 stb r10,PACAIRQHAPPENED(r13)
614 mfspr r10,SPRN_SRR1
615 rldicl r11,r10,48,1 /* clear MSR_EE */
616 rotldi r10,r11,16
617 mtspr SPRN_SRR1,r10
618 1: ld r10,PACA_EXGEN+EX_R10(r13);
619 ld r11,PACA_EXGEN+EX_R11(r13);
620 mfspr r13,SPRN_SPRG_GEN_SCRATCH;
621 rfi
622 b .
623 /*
624 * Called from arch_local_irq_enable when an interrupt needs
625 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
626 * to indicate the kind of interrupt. MSR:EE is already off.
627 * We generate a stackframe like if a real interrupt had happened.
628 *
629 * Note: While MSR:EE is off, we need to make sure that _MSR
630 * in the generated frame has EE set to 1 or the exception
631 * handler will not properly re-enable them.
632 */
633 _GLOBAL(__replay_interrupt)
634 /* We are going to jump to the exception common code which
635 * will retrieve various register values from the PACA which
636 * we don't give a damn about.
637 */
638 mflr r10
639 mfmsr r11
640 mfcr r4
641 mtspr SPRN_SPRG_GEN_SCRATCH,r13;
642 std r1,PACA_EXGEN+EX_R1(r13);
643 stw r4,PACA_EXGEN+EX_CR(r13);
644 ori r11,r11,MSR_EE
645 subi r1,r1,INT_FRAME_SIZE;
646 cmpwi cr0,r3,0x500
647 beq exc_0x500_common
648 cmpwi cr0,r3,0x900
649 beq exc_0x900_common
650 cmpwi cr0,r3,0x280
651 beq exc_0x280_common
652 blr
655 /*
656 * This is called from 0x300 and 0x400 handlers after the prologs with
657 * r14 and r15 containing the fault address and error code, with the
658 * original values stashed away in the PACA
659 */
660 storage_fault_common:
661 std r14,_DAR(r1)
662 std r15,_DSISR(r1)
663 addi r3,r1,STACK_FRAME_OVERHEAD
664 mr r4,r14
665 mr r5,r15
666 ld r14,PACA_EXGEN+EX_R14(r13)
667 ld r15,PACA_EXGEN+EX_R15(r13)
668 bl .do_page_fault
669 cmpdi r3,0
670 bne- 1f
671 b .ret_from_except_lite
672 1: bl .save_nvgprs
673 mr r5,r3
674 addi r3,r1,STACK_FRAME_OVERHEAD
675 ld r4,_DAR(r1)
676 bl .bad_page_fault
677 b .ret_from_except
679 /*
680 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
681 * continues here.
682 */
683 alignment_more:
684 std r14,_DAR(r1)
685 std r15,_DSISR(r1)
686 addi r3,r1,STACK_FRAME_OVERHEAD
687 ld r14,PACA_EXGEN+EX_R14(r13)
688 ld r15,PACA_EXGEN+EX_R15(r13)
689 bl .save_nvgprs
690 INTS_RESTORE_HARD
691 bl .alignment_exception
692 b .ret_from_except
694 /*
695 * We branch here from entry_64.S for the last stage of the exception
696 * return code path. MSR:EE is expected to be off at that point
697 */
698 _GLOBAL(exception_return_book3e)
699 b 1f
701 /* This is the return from load_up_fpu fast path which could do with
702 * less GPR restores in fact, but for now we have a single return path
703 */
704 .globl fast_exception_return
705 fast_exception_return:
706 wrteei 0
707 1: mr r0,r13
708 ld r10,_MSR(r1)
709 REST_4GPRS(2, r1)
710 andi. r6,r10,MSR_PR
711 REST_2GPRS(6, r1)
712 beq 1f
713 ACCOUNT_CPU_USER_EXIT(r10, r11)
714 ld r0,GPR13(r1)
716 1: stdcx. r0,0,r1 /* to clear the reservation */
718 ld r8,_CCR(r1)
719 ld r9,_LINK(r1)
720 ld r10,_CTR(r1)
721 ld r11,_XER(r1)
722 mtcr r8
723 mtlr r9
724 mtctr r10
725 mtxer r11
726 REST_2GPRS(8, r1)
727 ld r10,GPR10(r1)
728 ld r11,GPR11(r1)
729 ld r12,GPR12(r1)
730 mtspr SPRN_SPRG_GEN_SCRATCH,r0
732 std r10,PACA_EXGEN+EX_R10(r13);
733 std r11,PACA_EXGEN+EX_R11(r13);
734 ld r10,_NIP(r1)
735 ld r11,_MSR(r1)
736 ld r0,GPR0(r1)
737 ld r1,GPR1(r1)
738 mtspr SPRN_SRR0,r10
739 mtspr SPRN_SRR1,r11
740 ld r10,PACA_EXGEN+EX_R10(r13)
741 ld r11,PACA_EXGEN+EX_R11(r13)
742 mfspr r13,SPRN_SPRG_GEN_SCRATCH
743 rfi
745 /*
746 * Trampolines used when spotting a bad kernel stack pointer in
747 * the exception entry code.
748 *
749 * TODO: move some bits like SRR0 read to trampoline, pass PACA
750 * index around, etc... to handle crit & mcheck
751 */
752 BAD_STACK_TRAMPOLINE(0x000)
753 BAD_STACK_TRAMPOLINE(0x100)
754 BAD_STACK_TRAMPOLINE(0x200)
755 BAD_STACK_TRAMPOLINE(0x260)
756 BAD_STACK_TRAMPOLINE(0x280)
757 BAD_STACK_TRAMPOLINE(0x2a0)
758 BAD_STACK_TRAMPOLINE(0x2c0)
759 BAD_STACK_TRAMPOLINE(0x2e0)
760 BAD_STACK_TRAMPOLINE(0x300)
761 BAD_STACK_TRAMPOLINE(0x310)
762 BAD_STACK_TRAMPOLINE(0x320)
763 BAD_STACK_TRAMPOLINE(0x400)
764 BAD_STACK_TRAMPOLINE(0x500)
765 BAD_STACK_TRAMPOLINE(0x600)
766 BAD_STACK_TRAMPOLINE(0x700)
767 BAD_STACK_TRAMPOLINE(0x800)
768 BAD_STACK_TRAMPOLINE(0x900)
769 BAD_STACK_TRAMPOLINE(0x980)
770 BAD_STACK_TRAMPOLINE(0x9f0)
771 BAD_STACK_TRAMPOLINE(0xa00)
772 BAD_STACK_TRAMPOLINE(0xb00)
773 BAD_STACK_TRAMPOLINE(0xc00)
774 BAD_STACK_TRAMPOLINE(0xd00)
775 BAD_STACK_TRAMPOLINE(0xd08)
776 BAD_STACK_TRAMPOLINE(0xe00)
777 BAD_STACK_TRAMPOLINE(0xf00)
778 BAD_STACK_TRAMPOLINE(0xf20)
780 .globl bad_stack_book3e
781 bad_stack_book3e:
782 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
783 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
784 ld r1,PACAEMERGSP(r13)
785 subi r1,r1,64+INT_FRAME_SIZE
786 std r10,_NIP(r1)
787 std r11,_MSR(r1)
788 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
789 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
790 std r10,GPR1(r1)
791 std r11,_CCR(r1)
792 mfspr r10,SPRN_DEAR
793 mfspr r11,SPRN_ESR
794 std r10,_DAR(r1)
795 std r11,_DSISR(r1)
796 std r0,GPR0(r1); /* save r0 in stackframe */ \
797 std r2,GPR2(r1); /* save r2 in stackframe */ \
798 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
799 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
800 std r9,GPR9(r1); /* save r9 in stackframe */ \
801 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
802 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
803 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
804 std r3,GPR10(r1); /* save r10 to stackframe */ \
805 std r4,GPR11(r1); /* save r11 to stackframe */ \
806 std r12,GPR12(r1); /* save r12 in stackframe */ \
807 std r5,GPR13(r1); /* save it to stackframe */ \
808 mflr r10
809 mfctr r11
810 mfxer r12
811 std r10,_LINK(r1)
812 std r11,_CTR(r1)
813 std r12,_XER(r1)
814 SAVE_10GPRS(14,r1)
815 SAVE_8GPRS(24,r1)
816 lhz r12,PACA_TRAP_SAVE(r13)
817 std r12,_TRAP(r1)
818 addi r11,r1,INT_FRAME_SIZE
819 std r11,0(r1)
820 li r12,0
821 std r12,0(r11)
822 ld r2,PACATOC(r13)
823 1: addi r3,r1,STACK_FRAME_OVERHEAD
824 bl .kernel_bad_stack
825 b 1b
827 /*
828 * Setup the initial TLB for a core. This current implementation
829 * assume that whatever we are running off will not conflict with
830 * the new mapping at PAGE_OFFSET.
831 */
832 _GLOBAL(initial_tlb_book3e)
834 /* Look for the first TLB with IPROT set */
835 mfspr r4,SPRN_TLB0CFG
836 andi. r3,r4,TLBnCFG_IPROT
837 lis r3,MAS0_TLBSEL(0)@h
838 bne found_iprot
840 mfspr r4,SPRN_TLB1CFG
841 andi. r3,r4,TLBnCFG_IPROT
842 lis r3,MAS0_TLBSEL(1)@h
843 bne found_iprot
845 mfspr r4,SPRN_TLB2CFG
846 andi. r3,r4,TLBnCFG_IPROT
847 lis r3,MAS0_TLBSEL(2)@h
848 bne found_iprot
850 lis r3,MAS0_TLBSEL(3)@h
851 mfspr r4,SPRN_TLB3CFG
852 /* fall through */
854 found_iprot:
855 andi. r5,r4,TLBnCFG_HES
856 bne have_hes
858 mflr r8 /* save LR */
859 /* 1. Find the index of the entry we're executing in
860 *
861 * r3 = MAS0_TLBSEL (for the iprot array)
862 * r4 = SPRN_TLBnCFG
863 */
864 bl invstr /* Find our address */
865 invstr: mflr r6 /* Make it accessible */
866 mfmsr r7
867 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
868 mfspr r7,SPRN_PID
869 slwi r7,r7,16
870 or r7,r7,r5
871 mtspr SPRN_MAS6,r7
872 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
874 mfspr r3,SPRN_MAS0
875 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
877 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
878 oris r7,r7,MAS1_IPROT@h
879 mtspr SPRN_MAS1,r7
880 tlbwe
882 /* 2. Invalidate all entries except the entry we're executing in
883 *
884 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
885 * r4 = SPRN_TLBnCFG
886 * r5 = ESEL of entry we are running in
887 */
888 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
889 li r6,0 /* Set Entry counter to 0 */
890 1: mr r7,r3 /* Set MAS0(TLBSEL) */
891 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
892 mtspr SPRN_MAS0,r7
893 tlbre
894 mfspr r7,SPRN_MAS1
895 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
896 cmpw r5,r6
897 beq skpinv /* Dont update the current execution TLB */
898 mtspr SPRN_MAS1,r7
899 tlbwe
900 isync
901 skpinv: addi r6,r6,1 /* Increment */
902 cmpw r6,r4 /* Are we done? */
903 bne 1b /* If not, repeat */
905 /* Invalidate all TLBs */
906 PPC_TLBILX_ALL(0,R0)
907 sync
908 isync
910 /* 3. Setup a temp mapping and jump to it
911 *
912 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
913 * r5 = ESEL of entry we are running in
914 */
915 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
916 addi r7,r7,0x1
917 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
918 mtspr SPRN_MAS0,r4
919 tlbre
921 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
922 mtspr SPRN_MAS0,r4
924 mfspr r7,SPRN_MAS1
925 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
926 mtspr SPRN_MAS1,r6
928 tlbwe
930 mfmsr r6
931 xori r6,r6,MSR_IS
932 mtspr SPRN_SRR1,r6
933 bl 1f /* Find our address */
934 1: mflr r6
935 addi r6,r6,(2f - 1b)
936 mtspr SPRN_SRR0,r6
937 rfi
938 2:
940 /* 4. Clear out PIDs & Search info
941 *
942 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
943 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
944 * r5 = MAS3
945 */
946 li r6,0
947 mtspr SPRN_MAS6,r6
948 mtspr SPRN_PID,r6
950 /* 5. Invalidate mapping we started in
951 *
952 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
953 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
954 * r5 = MAS3
955 */
956 mtspr SPRN_MAS0,r3
957 tlbre
958 mfspr r6,SPRN_MAS1
959 rlwinm r6,r6,0,2,0 /* clear IPROT */
960 mtspr SPRN_MAS1,r6
961 tlbwe
963 /* Invalidate TLB1 */
964 PPC_TLBILX_ALL(0,R0)
965 sync
966 isync
968 /* The mapping only needs to be cache-coherent on SMP */
969 #ifdef CONFIG_SMP
970 #define M_IF_SMP MAS2_M
971 #else
972 #define M_IF_SMP 0
973 #endif
975 /* 6. Setup KERNELBASE mapping in TLB[0]
976 *
977 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
978 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
979 * r5 = MAS3
980 */
981 rlwinm r3,r3,0,16,3 /* clear ESEL */
982 mtspr SPRN_MAS0,r3
983 lis r6,(MAS1_VALID|MAS1_IPROT)@h
984 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
985 mtspr SPRN_MAS1,r6
987 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
988 mtspr SPRN_MAS2,r6
990 rlwinm r5,r5,0,0,25
991 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
992 mtspr SPRN_MAS3,r5
993 li r5,-1
994 rlwinm r5,r5,0,0,25
996 tlbwe
998 /* 7. Jump to KERNELBASE mapping
999 *
1000 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1001 */
1002 /* Now we branch the new virtual address mapped by this entry */
1003 LOAD_REG_IMMEDIATE(r6,2f)
1004 lis r7,MSR_KERNEL@h
1005 ori r7,r7,MSR_KERNEL@l
1006 mtspr SPRN_SRR0,r6
1007 mtspr SPRN_SRR1,r7
1008 rfi /* start execution out of TLB1[0] entry */
1009 2:
1011 /* 8. Clear out the temp mapping
1012 *
1013 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1014 */
1015 mtspr SPRN_MAS0,r4
1016 tlbre
1017 mfspr r5,SPRN_MAS1
1018 rlwinm r5,r5,0,2,0 /* clear IPROT */
1019 mtspr SPRN_MAS1,r5
1020 tlbwe
1022 /* Invalidate TLB1 */
1023 PPC_TLBILX_ALL(0,R0)
1024 sync
1025 isync
1027 /* We translate LR and return */
1028 tovirt(r8,r8)
1029 mtlr r8
1030 blr
1032 have_hes:
1033 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1034 * kernel linear mapping. We also set MAS8 once for all here though
1035 * that will have to be made dependent on whether we are running under
1036 * a hypervisor I suppose.
1037 */
1039 /* BEWARE, MAGIC
1040 * This code is called as an ordinary function on the boot CPU. But to
1041 * avoid duplication, this code is also used in SCOM bringup of
1042 * secondary CPUs. We read the code between the initial_tlb_code_start
1043 * and initial_tlb_code_end labels one instruction at a time and RAM it
1044 * into the new core via SCOM. That doesn't process branches, so there
1045 * must be none between those two labels. It also means if this code
1046 * ever takes any parameters, the SCOM code must also be updated to
1047 * provide them.
1048 */
1049 .globl a2_tlbinit_code_start
1050 a2_tlbinit_code_start:
1052 ori r11,r3,MAS0_WQ_ALLWAYS
1053 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1054 mtspr SPRN_MAS0,r11
1055 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1056 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1057 mtspr SPRN_MAS1,r3
1058 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1059 mtspr SPRN_MAS2,r3
1060 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1061 mtspr SPRN_MAS7_MAS3,r3
1062 li r3,0
1063 mtspr SPRN_MAS8,r3
1065 /* Write the TLB entry */
1066 tlbwe
1068 .globl a2_tlbinit_after_linear_map
1069 a2_tlbinit_after_linear_map:
1071 /* Now we branch the new virtual address mapped by this entry */
1072 LOAD_REG_IMMEDIATE(r3,1f)
1073 mtctr r3
1074 bctr
1076 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1077 * else (including IPROTed things left by firmware)
1078 * r4 = TLBnCFG
1079 * r3 = current address (more or less)
1080 */
1082 li r5,0
1083 mtspr SPRN_MAS6,r5
1084 tlbsx 0,r3
1086 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1087 rlwinm r10,r4,8,0xff
1088 addi r10,r10,-1 /* Get inner loop mask */
1090 li r3,1
1092 mfspr r5,SPRN_MAS1
1093 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1095 mfspr r6,SPRN_MAS2
1096 rldicr r6,r6,0,51 /* Extract EPN */
1098 mfspr r7,SPRN_MAS0
1099 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1101 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1103 2: add r4,r3,r8
1104 and r4,r4,r10
1106 rlwimi r7,r4,16,MAS0_ESEL_MASK
1108 mtspr SPRN_MAS0,r7
1109 mtspr SPRN_MAS1,r5
1110 mtspr SPRN_MAS2,r6
1111 tlbwe
1113 addi r3,r3,1
1114 and. r4,r3,r10
1116 bne 3f
1117 addis r6,r6,(1<<30)@h
1118 3:
1119 cmpw r3,r9
1120 blt 2b
1122 .globl a2_tlbinit_after_iprot_flush
1123 a2_tlbinit_after_iprot_flush:
1125 #ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1126 /* Now establish early debug mappings if applicable */
1127 /* Restore the MAS0 we used for linear mapping load */
1128 mtspr SPRN_MAS0,r11
1130 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1131 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1132 mtspr SPRN_MAS1,r3
1133 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1134 mtspr SPRN_MAS2,r3
1135 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1136 mtspr SPRN_MAS7_MAS3,r3
1137 /* re-use the MAS8 value from the linear mapping */
1138 tlbwe
1139 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1141 PPC_TLBILX(0,0,R0)
1142 sync
1143 isync
1145 .globl a2_tlbinit_code_end
1146 a2_tlbinit_code_end:
1148 /* We translate LR and return */
1149 mflr r3
1150 tovirt(r3,r3)
1151 mtlr r3
1152 blr
1154 /*
1155 * Main entry (boot CPU, thread 0)
1156 *
1157 * We enter here from head_64.S, possibly after the prom_init trampoline
1158 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1159 * mode. Anything else is as it was left by the bootloader
1160 *
1161 * Initial requirements of this port:
1162 *
1163 * - Kernel loaded at 0 physical
1164 * - A good lump of memory mapped 0:0 by UTLB entry 0
1165 * - MSR:IS & MSR:DS set to 0
1166 *
1167 * Note that some of the above requirements will be relaxed in the future
1168 * as the kernel becomes smarter at dealing with different initial conditions
1169 * but for now you have to be careful
1170 */
1171 _GLOBAL(start_initialization_book3e)
1172 mflr r28
1174 /* First, we need to setup some initial TLBs to map the kernel
1175 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1176 * and always use AS 0, so we just set it up to match our link
1177 * address and never use 0 based addresses.
1178 */
1179 bl .initial_tlb_book3e
1181 /* Init global core bits */
1182 bl .init_core_book3e
1184 /* Init per-thread bits */
1185 bl .init_thread_book3e
1187 /* Return to common init code */
1188 tovirt(r28,r28)
1189 mtlr r28
1190 blr
1193 /*
1194 * Secondary core/processor entry
1195 *
1196 * This is entered for thread 0 of a secondary core, all other threads
1197 * are expected to be stopped. It's similar to start_initialization_book3e
1198 * except that it's generally entered from the holding loop in head_64.S
1199 * after CPUs have been gathered by Open Firmware.
1200 *
1201 * We assume we are in 32 bits mode running with whatever TLB entry was
1202 * set for us by the firmware or POR engine.
1203 */
1204 _GLOBAL(book3e_secondary_core_init_tlb_set)
1205 li r4,1
1206 b .generic_secondary_smp_init
1208 _GLOBAL(book3e_secondary_core_init)
1209 mflr r28
1211 /* Do we need to setup initial TLB entry ? */
1212 cmplwi r4,0
1213 bne 2f
1215 /* Setup TLB for this core */
1216 bl .initial_tlb_book3e
1218 /* We can return from the above running at a different
1219 * address, so recalculate r2 (TOC)
1220 */
1221 bl .relative_toc
1223 /* Init global core bits */
1224 2: bl .init_core_book3e
1226 /* Init per-thread bits */
1227 3: bl .init_thread_book3e
1229 /* Return to common init code at proper virtual address.
1230 *
1231 * Due to various previous assumptions, we know we entered this
1232 * function at either the final PAGE_OFFSET mapping or using a
1233 * 1:1 mapping at 0, so we don't bother doing a complicated check
1234 * here, we just ensure the return address has the right top bits.
1235 *
1236 * Note that if we ever want to be smarter about where we can be
1237 * started from, we have to be careful that by the time we reach
1238 * the code below we may already be running at a different location
1239 * than the one we were called from since initial_tlb_book3e can
1240 * have moved us already.
1241 */
1242 cmpdi cr0,r28,0
1243 blt 1f
1244 lis r3,PAGE_OFFSET@highest
1245 sldi r3,r3,32
1246 or r28,r28,r3
1247 1: mtlr r28
1248 blr
1250 _GLOBAL(book3e_secondary_thread_init)
1251 mflr r28
1252 b 3b
1254 _STATIC(init_core_book3e)
1255 /* Establish the interrupt vector base */
1256 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1257 mtspr SPRN_IVPR,r3
1258 sync
1259 blr
1261 _STATIC(init_thread_book3e)
1262 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1263 mtspr SPRN_EPCR,r3
1265 /* Make sure interrupts are off */
1266 wrteei 0
1268 /* disable all timers and clear out status */
1269 li r3,0
1270 mtspr SPRN_TCR,r3
1271 mfspr r3,SPRN_TSR
1272 mtspr SPRN_TSR,r3
1274 blr
1276 _GLOBAL(__setup_base_ivors)
1277 SET_IVOR(0, 0x020) /* Critical Input */
1278 SET_IVOR(1, 0x000) /* Machine Check */
1279 SET_IVOR(2, 0x060) /* Data Storage */
1280 SET_IVOR(3, 0x080) /* Instruction Storage */
1281 SET_IVOR(4, 0x0a0) /* External Input */
1282 SET_IVOR(5, 0x0c0) /* Alignment */
1283 SET_IVOR(6, 0x0e0) /* Program */
1284 SET_IVOR(7, 0x100) /* FP Unavailable */
1285 SET_IVOR(8, 0x120) /* System Call */
1286 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1287 SET_IVOR(10, 0x160) /* Decrementer */
1288 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1289 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1290 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1291 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1292 SET_IVOR(15, 0x040) /* Debug */
1294 sync
1296 blr
1298 _GLOBAL(setup_perfmon_ivor)
1299 SET_IVOR(35, 0x260) /* Performance Monitor */
1300 blr
1302 _GLOBAL(setup_doorbell_ivors)
1303 SET_IVOR(36, 0x280) /* Processor Doorbell */
1304 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1306 /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
1307 mfspr r10,SPRN_MMUCFG
1308 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1309 beqlr
1311 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1312 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1313 blr
1315 _GLOBAL(setup_ehv_ivors)
1316 /*
1317 * We may be running as a guest and lack E.HV even on a chip
1318 * that normally has it.
1319 */
1320 mfspr r10,SPRN_MMUCFG
1321 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1322 beqlr
1324 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1325 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1326 blr