arch/blackfin/mach-bf533/include/mach/irq.h

   1 /*
   2  * Copyright 2005-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later
   5  */
   6
   7 #ifndef _BF533_IRQ_H_
   8 #define _BF533_IRQ_H_
   9
  10 #include <mach-common/irq.h>
  11
  12 #define NR_PERI_INTS            24
  13
  14 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
  15 #define IRQ_DMA_ERROR           BFIN_IRQ(1)     /* DMA Error (general) */
  16 #define IRQ_PPI_ERROR           BFIN_IRQ(2)     /* PPI Error Interrupt */
  17 #define IRQ_SPORT0_ERROR        BFIN_IRQ(3)     /* SPORT0 Error Interrupt */
  18 #define IRQ_SPORT1_ERROR        BFIN_IRQ(4)     /* SPORT1 Error Interrupt */
  19 #define IRQ_SPI_ERROR           BFIN_IRQ(5)     /* SPI Error Interrupt */
  20 #define IRQ_UART0_ERROR         BFIN_IRQ(6)     /* UART Error Interrupt */
  21 #define IRQ_RTC                 BFIN_IRQ(7)     /* RTC Interrupt */
  22 #define IRQ_PPI                 BFIN_IRQ(8)     /* DMA0 Interrupt (PPI) */
  23 #define IRQ_SPORT0_RX           BFIN_IRQ(9)     /* DMA1 Interrupt (SPORT0 RX) */
  24 #define IRQ_SPORT0_TX           BFIN_IRQ(10)    /* DMA2 Interrupt (SPORT0 TX) */
  25 #define IRQ_SPORT1_RX           BFIN_IRQ(11)    /* DMA3 Interrupt (SPORT1 RX) */
  26 #define IRQ_SPORT1_TX           BFIN_IRQ(12)    /* DMA4 Interrupt (SPORT1 TX) */
  27 #define IRQ_SPI                 BFIN_IRQ(13)    /* DMA5 Interrupt (SPI) */
  28 #define IRQ_UART0_RX            BFIN_IRQ(14)    /* DMA6 Interrupt (UART RX) */
  29 #define IRQ_UART0_TX            BFIN_IRQ(15)    /* DMA7 Interrupt (UART TX) */
  30 #define IRQ_TIMER0              BFIN_IRQ(16)    /* Timer 0 */
  31 #define IRQ_TIMER1              BFIN_IRQ(17)    /* Timer 1 */
  32 #define IRQ_TIMER2              BFIN_IRQ(18)    /* Timer 2 */
  33 #define IRQ_PROG_INTA           BFIN_IRQ(19)    /* Programmable Flags A (8) */
  34 #define IRQ_PROG_INTB           BFIN_IRQ(20)    /* Programmable Flags B (8) */
  35 #define IRQ_MEM_DMA0            BFIN_IRQ(21)    /* DMA8/9 Interrupt (Memory DMA Stream 0) */
  36 #define IRQ_MEM_DMA1            BFIN_IRQ(22)    /* DMA10/11 Interrupt (Memory DMA Stream 1) */
  37 #define IRQ_WATCH               BFIN_IRQ(23)    /* Watch Dog Timer */
  38
  39 #define SYS_IRQS                31
  40
  41 #define IRQ_PF0                 33
  42 #define IRQ_PF1                 34
  43 #define IRQ_PF2                 35
  44 #define IRQ_PF3                 36
  45 #define IRQ_PF4                 37
  46 #define IRQ_PF5                 38
  47 #define IRQ_PF6                 39
  48 #define IRQ_PF7                 40
  49 #define IRQ_PF8                 41
  50 #define IRQ_PF9                 42
  51 #define IRQ_PF10                43
  52 #define IRQ_PF11                44
  53 #define IRQ_PF12                45
  54 #define IRQ_PF13                46
  55 #define IRQ_PF14                47
  56 #define IRQ_PF15                48
  57
  58 #define GPIO_IRQ_BASE           IRQ_PF0
  59
  60 #define NR_MACH_IRQS            (IRQ_PF15 + 1)
  61
  62 /* IAR0 BIT FIELDS */
  63 #define RTC_ERROR_POS           28
  64 #define UART_ERROR_POS          24
  65 #define SPORT1_ERROR_POS        20
  66 #define SPI_ERROR_POS           16
  67 #define SPORT0_ERROR_POS        12
  68 #define PPI_ERROR_POS           8
  69 #define DMA_ERROR_POS           4
  70 #define PLLWAKE_ERROR_POS       0
  71
  72 /* IAR1 BIT FIELDS */
  73 #define DMA7_UARTTX_POS         28
  74 #define DMA6_UARTRX_POS         24
  75 #define DMA5_SPI_POS            20
  76 #define DMA4_SPORT1TX_POS       16
  77 #define DMA3_SPORT1RX_POS       12
  78 #define DMA2_SPORT0TX_POS       8
  79 #define DMA1_SPORT0RX_POS       4
  80 #define DMA0_PPI_POS            0
  81
  82 /* IAR2 BIT FIELDS */
  83 #define WDTIMER_POS             28
  84 #define MEMDMA1_POS             24
  85 #define MEMDMA0_POS             20
  86 #define PFB_POS                 16
  87 #define PFA_POS                 12
  88 #define TIMER2_POS              8
  89 #define TIMER1_POS              4
  90 #define TIMER0_POS              0
  91
  92 #endif