1 /* MN2WS0050 on-board DMA controller registers
3 * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
11 #ifndef _ASM_PROC_DMACTL_REGS_H
12 #define _ASM_PROC_DMACTL_REGS_H
14 #include <asm/cpu-regs.h>
19 #define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */
20 #define DMxCTR_BG 0x0000001f /* transfer request source */
21 #define DMxCTR_BG_SOFT 0x00000000 /* - software source */
22 #define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
23 #define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
24 #define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
25 #define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
26 #define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
27 #define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
28 #define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
29 #define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
30 #define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
31 #define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
32 #define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
33 #define DMxCTR_BG_RYBY 0x0000000d /* - NAND Flash RY/BY request source */
34 #define DMxCTR_BG_RMC 0x0000000e /* - remote controller output */
35 #define DMxCTR_BG_XIRQ12 0x00000011 /* - XIRQ12 pin interrupt source */
36 #define DMxCTR_BG_XIRQ13 0x00000012 /* - XIRQ13 pin interrupt source */
37 #define DMxCTR_BG_TCK 0x00000014 /* - tick timer underflow */
38 #define DMxCTR_BG_SC4TX 0x00000019 /* - serial port4 transmission */
39 #define DMxCTR_BG_SC4RX 0x0000001a /* - serial port4 reception */
40 #define DMxCTR_BG_SC5TX 0x0000001b /* - serial port5 transmission */
41 #define DMxCTR_BG_SC5RX 0x0000001c /* - serial port5 reception */
42 #define DMxCTR_BG_SC6TX 0x0000001d /* - serial port6 transmission */
43 #define DMxCTR_BG_SC6RX 0x0000001e /* - serial port6 reception */
44 #define DMxCTR_BG_TMSUFLOW 0x0000001f /* - timestamp timer underflow */
45 #define DMxCTR_SAM 0x00000060 /* DMA transfer src addr mode */
46 #define DMxCTR_SAM_INCR 0x00000000 /* - increment */
47 #define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
48 #define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
49 #define DMxCTR_DAM 0x00000300 /* DMA transfer dest addr mode */
50 #define DMxCTR_DAM_INCR 0x00000000 /* - increment */
51 #define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
52 #define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
53 #define DMxCTR_UT 0x00006000 /* DMA transfer unit */
54 #define DMxCTR_UT_1 0x00000000 /* - 1 byte */
55 #define DMxCTR_UT_2 0x00002000 /* - 2 byte */
56 #define DMxCTR_UT_4 0x00004000 /* - 4 byte */
57 #define DMxCTR_UT_16 0x00006000 /* - 16 byte */
58 #define DMxCTR_RRE 0x00008000 /* DMA round robin enable */
59 #define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
60 #define DMxCTR_RQM 0x00060000 /* external request input source mode */
61 #define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
62 #define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
63 #define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
64 #define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
65 #define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
66 #define DMxCTR_PERR 0x40000000 /* DMA transfer parameter error flag */
67 #define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
69 #define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */
71 #define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */
73 #define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */
74 #define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
76 #define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */
77 #define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
79 #define DM0IRQ 16 /* DMA channel 0 complete IRQ */
80 #define DM1IRQ 17 /* DMA channel 1 complete IRQ */
81 #define DM2IRQ 18 /* DMA channel 2 complete IRQ */
82 #define DM3IRQ 19 /* DMA channel 3 complete IRQ */
84 #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
85 #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
86 #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
87 #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
91 struct mn10300_dmactl_regs
{
97 } __attribute__((aligned(0x100)));
99 #endif /* __ASSEMBLY__ */
101 #endif /* __KERNEL__ */
103 #endif /* _ASM_PROC_DMACTL_REGS_H */