1 #ifndef _ASM_S390_PCI_CLP_H
2 #define _ASM_S390_PCI_CLP_H
7 * Call Logical Processor - Command Codes
9 #define CLP_LIST_PCI 0x0002
10 #define CLP_QUERY_PCI_FN 0x0003
11 #define CLP_QUERY_PCI_FNGRP 0x0004
12 #define CLP_SET_PCI_FN 0x0005
14 /* PCI function handle list entry */
15 struct clp_fh_list_entry
{
20 u32 fid
; /* PCI function id */
21 u32 fh
; /* PCI function handle */
24 #define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
25 #define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
26 #define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
27 #define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
28 #define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
29 #define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
30 #define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
31 #define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
32 #define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
33 #define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
35 /* request or response block header length */
36 #define LIST_PCI_HDR_LEN 32
38 /* Number of function handles fitting in response block */
39 #define CLP_FH_LIST_NR_ENTRIES \
40 ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
41 / sizeof(struct clp_fh_list_entry))
43 #define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
44 #define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
46 #define CLP_UTIL_STR_LEN 64
47 #define CLP_PFIP_NR_SEGMENTS 4
49 /* List PCI functions request */
50 struct clp_req_list_pci
{
51 struct clp_req_hdr hdr
;
56 /* List PCI functions response */
57 struct clp_rsp_list_pci
{
58 struct clp_rsp_hdr hdr
;
64 struct clp_fh_list_entry fh_list
[CLP_FH_LIST_NR_ENTRIES
];
67 /* Query PCI function request */
68 struct clp_req_query_pci
{
69 struct clp_req_hdr hdr
;
70 u32 fh
; /* function handle */
75 /* Query PCI function response */
76 struct clp_rsp_query_pci
{
77 struct clp_rsp_hdr hdr
;
78 u16 vfn
; /* virtual fn number */
80 u16 util_str_avail
: 1; /* utility string available? */
81 u16 pfgid
: 8; /* pci function group id */
82 u32 fid
; /* pci function id */
83 u8 bar_size
[PCI_BAR_COUNT
];
85 u32 bar
[PCI_BAR_COUNT
];
86 u8 pfip
[CLP_PFIP_NR_SEGMENTS
]; /* pci function internal path */
88 u8 pft
; /* pci function type */
89 u64 sdma
; /* start dma as */
90 u64 edma
; /* end dma as */
92 u32 uid
; /* user defined id */
93 u8 util_str
[CLP_UTIL_STR_LEN
]; /* utility string */
96 /* Query PCI function group request */
97 struct clp_req_query_pci_grp
{
98 struct clp_req_hdr hdr
;
100 u32 pfgid
: 8; /* function group id */
105 /* Query PCI function group response */
106 struct clp_rsp_query_pci_grp
{
107 struct clp_rsp_hdr hdr
;
109 u16 noi
: 12; /* number of interrupts */
113 u8 refresh
: 1; /* TLB refresh mode */
117 u64 dasm
; /* dma address space mask */
118 u64 msia
; /* MSI address */
123 /* Set PCI function request */
124 struct clp_req_set_pci
{
125 struct clp_req_hdr hdr
;
126 u32 fh
; /* function handle */
128 u8 oc
; /* operation controls */
129 u8 ndas
; /* number of dma spaces */
133 /* Set PCI function response */
134 struct clp_rsp_set_pci
{
135 struct clp_rsp_hdr hdr
;
136 u32 fh
; /* function handle */
141 /* Combined request/response block structures used by clp insn */
142 struct clp_req_rsp_list_pci
{
143 struct clp_req_list_pci request
;
144 struct clp_rsp_list_pci response
;
147 struct clp_req_rsp_set_pci
{
148 struct clp_req_set_pci request
;
149 struct clp_rsp_set_pci response
;
152 struct clp_req_rsp_query_pci
{
153 struct clp_req_query_pci request
;
154 struct clp_rsp_query_pci response
;
157 struct clp_req_rsp_query_pci_grp
{
158 struct clp_req_query_pci_grp request
;
159 struct clp_rsp_query_pci_grp response
;