2 * Copyright 2014 Cisco Systems, Inc. All rights reserved.
4 * This program is free software; you may redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
9 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
10 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
12 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
13 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
14 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
18 #include <linux/string.h>
19 #include <linux/errno.h>
20 #include <linux/pci.h>
21 #include <linux/interrupt.h>
24 #include "vnic_intr.h"
25 #include "vnic_stats.h"
31 * snic_isr_msix_wq : MSIx ISR for work queue.
35 snic_isr_msix_wq(int irq
, void *data
)
37 struct snic
*snic
= data
;
38 unsigned long wq_work_done
= 0;
40 snic
->s_stats
.misc
.last_isr_time
= jiffies
;
41 atomic64_inc(&snic
->s_stats
.misc
.isr_cnt
);
43 wq_work_done
= snic_wq_cmpl_handler(snic
, -1);
44 svnic_intr_return_credits(&snic
->intr
[SNIC_MSIX_WQ
],
47 1 /* reset intr timer */);
50 } /* end of snic_isr_msix_wq */
53 snic_isr_msix_io_cmpl(int irq
, void *data
)
55 struct snic
*snic
= data
;
56 unsigned long iocmpl_work_done
= 0;
58 snic
->s_stats
.misc
.last_isr_time
= jiffies
;
59 atomic64_inc(&snic
->s_stats
.misc
.isr_cnt
);
61 iocmpl_work_done
= snic_fwcq_cmpl_handler(snic
, -1);
62 svnic_intr_return_credits(&snic
->intr
[SNIC_MSIX_IO_CMPL
],
65 1 /* reset intr timer */);
68 } /* end of snic_isr_msix_io_cmpl */
71 snic_isr_msix_err_notify(int irq
, void *data
)
73 struct snic
*snic
= data
;
75 snic
->s_stats
.misc
.last_isr_time
= jiffies
;
76 atomic64_inc(&snic
->s_stats
.misc
.isr_cnt
);
78 svnic_intr_return_all_credits(&snic
->intr
[SNIC_MSIX_ERR_NOTIFY
]);
79 snic_log_q_error(snic
);
81 /*Handling link events */
82 snic_handle_link_event(snic
);
85 } /* end of snic_isr_msix_err_notify */
89 snic_free_intr(struct snic
*snic
)
93 /* ONLY interrupt mode MSIX is supported */
94 for (i
= 0; i
< ARRAY_SIZE(snic
->msix
); i
++) {
95 if (snic
->msix
[i
].requested
) {
96 free_irq(snic
->msix_entry
[i
].vector
,
100 } /* end of snic_free_intr */
103 snic_request_intr(struct snic
*snic
)
106 enum vnic_dev_intr_mode intr_mode
;
108 intr_mode
= svnic_dev_get_intr_mode(snic
->vdev
);
109 SNIC_BUG_ON(intr_mode
!= VNIC_DEV_INTR_MODE_MSIX
);
112 * Currently HW supports single WQ and CQ. So passing devid as snic.
113 * When hardware supports multiple WQs and CQs, one idea is
114 * to pass devid as corresponding WQ or CQ ptr and retrieve snic
116 * Except for err_notify, which is always one.
118 sprintf(snic
->msix
[SNIC_MSIX_WQ
].devname
,
121 snic
->msix
[SNIC_MSIX_WQ
].isr
= snic_isr_msix_wq
;
122 snic
->msix
[SNIC_MSIX_WQ
].devid
= snic
;
124 sprintf(snic
->msix
[SNIC_MSIX_IO_CMPL
].devname
,
127 snic
->msix
[SNIC_MSIX_IO_CMPL
].isr
= snic_isr_msix_io_cmpl
;
128 snic
->msix
[SNIC_MSIX_IO_CMPL
].devid
= snic
;
130 sprintf(snic
->msix
[SNIC_MSIX_ERR_NOTIFY
].devname
,
133 snic
->msix
[SNIC_MSIX_ERR_NOTIFY
].isr
= snic_isr_msix_err_notify
;
134 snic
->msix
[SNIC_MSIX_ERR_NOTIFY
].devid
= snic
;
136 for (i
= 0; i
< ARRAY_SIZE(snic
->msix
); i
++) {
137 ret
= request_irq(snic
->msix_entry
[i
].vector
,
140 snic
->msix
[i
].devname
,
141 snic
->msix
[i
].devid
);
143 SNIC_HOST_ERR(snic
->shost
,
144 "MSI-X: requrest_irq(%d) failed %d\n",
147 snic_free_intr(snic
);
150 snic
->msix
[i
].requested
= 1;
154 } /* end of snic_requrest_intr */
157 snic_set_intr_mode(struct snic
*snic
)
159 unsigned int n
= ARRAY_SIZE(snic
->wq
);
160 unsigned int m
= SNIC_CQ_IO_CMPL_MAX
;
164 * We need n WQs, m CQs, and n+m+1 INTRs
165 * (last INTR is used for WQ/CQ errors and notification area
168 BUILD_BUG_ON((ARRAY_SIZE(snic
->wq
) + SNIC_CQ_IO_CMPL_MAX
) >
169 ARRAY_SIZE(snic
->intr
));
170 SNIC_BUG_ON(ARRAY_SIZE(snic
->msix_entry
) < (n
+ m
+ 1));
172 for (i
= 0; i
< (n
+ m
+ 1); i
++)
173 snic
->msix_entry
[i
].entry
= i
;
175 if (snic
->wq_count
>= n
&& snic
->cq_count
>= (n
+ m
)) {
176 if (!pci_enable_msix(snic
->pdev
,
180 snic
->cq_count
= n
+ m
;
181 snic
->intr_count
= n
+ m
+ 1;
182 snic
->err_intr_offset
= SNIC_MSIX_ERR_NOTIFY
;
184 SNIC_ISR_DBG(snic
->shost
,
185 "Using MSI-X Interrupts\n");
186 svnic_dev_set_intr_mode(snic
->vdev
,
187 VNIC_DEV_INTR_MODE_MSIX
);
193 svnic_dev_set_intr_mode(snic
->vdev
, VNIC_DEV_INTR_MODE_UNKNOWN
);
196 } /* end of snic_set_intr_mode */
199 snic_clear_intr_mode(struct snic
*snic
)
201 pci_disable_msix(snic
->pdev
);
203 svnic_dev_set_intr_mode(snic
->vdev
, VNIC_DEV_INTR_MODE_INTX
);