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sfc: Remove unused constant
[linux/fpc-iii.git] / drivers / net / sfc / falcon.c
blob2c0be6ccc6241f771597a69d58fa1dfcb03062bd
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include "net_driver.h"
19 #include "bitfield.h"
20 #include "efx.h"
21 #include "mac.h"
22 #include "spi.h"
23 #include "falcon.h"
24 #include "regs.h"
25 #include "io.h"
26 #include "mdio_10g.h"
27 #include "phy.h"
28 #include "workarounds.h"
29
30 /* Hardware control for SFC4000 (aka Falcon). */
31
32 /**************************************************************************
33 *
34 * Configurable values
35 *
36 **************************************************************************
37 */
38
39 static int disable_dma_stats;
40
41 /* This is set to 16 for a good reason. In summary, if larger than
42 * 16, the descriptor cache holds more than a default socket
43 * buffer's worth of packets (for UDP we can only have at most one
44 * socket buffer's worth outstanding). This combined with the fact
45 * that we only get 1 TX event per descriptor cache means the NIC
46 * goes idle.
47 */
48 #define TX_DC_ENTRIES 16
49 #define TX_DC_ENTRIES_ORDER 1
50 #define TX_DC_BASE 0x130000
51
52 #define RX_DC_ENTRIES 64
53 #define RX_DC_ENTRIES_ORDER 3
54 #define RX_DC_BASE 0x100000
55
56 static const unsigned int
57 /* "Large" EEPROM device: Atmel AT25640 or similar
58 * 8 KB, 16-bit address, 32 B write block */
59 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
60 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
61 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
62 /* Default flash device: Atmel AT25F1024
63 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
64 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
65 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
66 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
67 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
68 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
69
70 /* RX FIFO XOFF watermark
71 *
72 * When the amount of the RX FIFO increases used increases past this
73 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
74 * This also has an effect on RX/TX arbitration
75 */
76 static int rx_xoff_thresh_bytes = -1;
77 module_param(rx_xoff_thresh_bytes, int, 0644);
78 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
79
80 /* RX FIFO XON watermark
81 *
82 * When the amount of the RX FIFO used decreases below this
83 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
84 * This also has an effect on RX/TX arbitration
85 */
86 static int rx_xon_thresh_bytes = -1;
87 module_param(rx_xon_thresh_bytes, int, 0644);
88 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
89
90 /* If FALCON_MAX_INT_ERRORS internal errors occur within
91 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
92 * disable it.
93 */
94 #define FALCON_INT_ERROR_EXPIRE 3600
95 #define FALCON_MAX_INT_ERRORS 5
96
97 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
98 */
99 #define FALCON_FLUSH_INTERVAL 10
100 #define FALCON_FLUSH_POLL_COUNT 100
101
102 /**************************************************************************
103 *
104 * Falcon constants
105 *
106 **************************************************************************
107 */
108
109 /* Size and alignment of special buffers (4KB) */
110 #define FALCON_BUF_SIZE 4096
111
112 #define FALCON_IS_DUAL_FUNC(efx) \
113 (falcon_rev(efx) < FALCON_REV_B0)
114
115 /**************************************************************************
116 *
117 * Falcon hardware access
118 *
119 **************************************************************************/
120
121 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
122 unsigned int index)
123 {
124 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
125 value, index);
126 }
127
128 /* Read the current event from the event queue */
129 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
130 unsigned int index)
131 {
132 return (((efx_qword_t *) (channel->eventq.addr)) + index);
133 }
134
135 /* See if an event is present
136 *
137 * We check both the high and low dword of the event for all ones. We
138 * wrote all ones when we cleared the event, and no valid event can
139 * have all ones in either its high or low dwords. This approach is
140 * robust against reordering.
141 *
142 * Note that using a single 64-bit comparison is incorrect; even
143 * though the CPU read will be atomic, the DMA write may not be.
144 */
145 static inline int falcon_event_present(efx_qword_t *event)
146 {
147 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
148 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
149 }
150
151 /**************************************************************************
152 *
153 * I2C bus - this is a bit-bashing interface using GPIO pins
154 * Note that it uses the output enables to tristate the outputs
155 * SDA is the data pin and SCL is the clock
156 *
157 **************************************************************************
158 */
159 static void falcon_setsda(void *data, int state)
160 {
161 struct efx_nic *efx = (struct efx_nic *)data;
162 efx_oword_t reg;
163
164 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
165 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
166 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
167 }
168
169 static void falcon_setscl(void *data, int state)
170 {
171 struct efx_nic *efx = (struct efx_nic *)data;
172 efx_oword_t reg;
173
174 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
175 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
176 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
177 }
178
179 static int falcon_getsda(void *data)
180 {
181 struct efx_nic *efx = (struct efx_nic *)data;
182 efx_oword_t reg;
183
184 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
185 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
186 }
187
188 static int falcon_getscl(void *data)
189 {
190 struct efx_nic *efx = (struct efx_nic *)data;
191 efx_oword_t reg;
192
193 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
194 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
195 }
196
197 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
198 .setsda = falcon_setsda,
199 .setscl = falcon_setscl,
200 .getsda = falcon_getsda,
201 .getscl = falcon_getscl,
202 .udelay = 5,
203 /* Wait up to 50 ms for slave to let us pull SCL high */
204 .timeout = DIV_ROUND_UP(HZ, 20),
205 };
206
207 /**************************************************************************
208 *
209 * Falcon special buffer handling
210 * Special buffers are used for event queues and the TX and RX
211 * descriptor rings.
212 *
213 *************************************************************************/
214
215 /*
216 * Initialise a Falcon special buffer
217 *
218 * This will define a buffer (previously allocated via
219 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
220 * it to be used for event queues, descriptor rings etc.
221 */
222 static void
223 falcon_init_special_buffer(struct efx_nic *efx,
224 struct efx_special_buffer *buffer)
225 {
226 efx_qword_t buf_desc;
227 int index;
228 dma_addr_t dma_addr;
229 int i;
230
231 EFX_BUG_ON_PARANOID(!buffer->addr);
232
233 /* Write buffer descriptors to NIC */
234 for (i = 0; i < buffer->entries; i++) {
235 index = buffer->index + i;
236 dma_addr = buffer->dma_addr + (i * 4096);
237 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
238 index, (unsigned long long)dma_addr);
239 EFX_POPULATE_QWORD_3(buf_desc,
240 FRF_AZ_BUF_ADR_REGION, 0,
241 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
242 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
243 falcon_write_buf_tbl(efx, &buf_desc, index);
244 }
245 }
246
247 /* Unmaps a buffer from Falcon and clears the buffer table entries */
248 static void
249 falcon_fini_special_buffer(struct efx_nic *efx,
250 struct efx_special_buffer *buffer)
251 {
252 efx_oword_t buf_tbl_upd;
253 unsigned int start = buffer->index;
254 unsigned int end = (buffer->index + buffer->entries - 1);
255
256 if (!buffer->entries)
257 return;
258
259 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
260 buffer->index, buffer->index + buffer->entries - 1);
261
262 EFX_POPULATE_OWORD_4(buf_tbl_upd,
263 FRF_AZ_BUF_UPD_CMD, 0,
264 FRF_AZ_BUF_CLR_CMD, 1,
265 FRF_AZ_BUF_CLR_END_ID, end,
266 FRF_AZ_BUF_CLR_START_ID, start);
267 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
268 }
269
270 /*
271 * Allocate a new Falcon special buffer
272 *
273 * This allocates memory for a new buffer, clears it and allocates a
274 * new buffer ID range. It does not write into Falcon's buffer table.
275 *
276 * This call will allocate 4KB buffers, since Falcon can't use 8KB
277 * buffers for event queues and descriptor rings.
278 */
279 static int falcon_alloc_special_buffer(struct efx_nic *efx,
280 struct efx_special_buffer *buffer,
281 unsigned int len)
282 {
283 len = ALIGN(len, FALCON_BUF_SIZE);
284
285 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
286 &buffer->dma_addr);
287 if (!buffer->addr)
288 return -ENOMEM;
289 buffer->len = len;
290 buffer->entries = len / FALCON_BUF_SIZE;
291 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
292
293 /* All zeros is a potentially valid event so memset to 0xff */
294 memset(buffer->addr, 0xff, len);
295
296 /* Select new buffer ID */
297 buffer->index = efx->next_buffer_table;
298 efx->next_buffer_table += buffer->entries;
299
300 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
301 "(virt %p phys %llx)\n", buffer->index,
302 buffer->index + buffer->entries - 1,
303 (u64)buffer->dma_addr, len,
304 buffer->addr, (u64)virt_to_phys(buffer->addr));
305
306 return 0;
307 }
308
309 static void falcon_free_special_buffer(struct efx_nic *efx,
310 struct efx_special_buffer *buffer)
311 {
312 if (!buffer->addr)
313 return;
314
315 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
316 "(virt %p phys %llx)\n", buffer->index,
317 buffer->index + buffer->entries - 1,
318 (u64)buffer->dma_addr, buffer->len,
319 buffer->addr, (u64)virt_to_phys(buffer->addr));
320
321 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
322 buffer->dma_addr);
323 buffer->addr = NULL;
324 buffer->entries = 0;
325 }
326
327 /**************************************************************************
328 *
329 * Falcon generic buffer handling
330 * These buffers are used for interrupt status and MAC stats
331 *
332 **************************************************************************/
333
334 static int falcon_alloc_buffer(struct efx_nic *efx,
335 struct efx_buffer *buffer, unsigned int len)
336 {
337 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
338 &buffer->dma_addr);
339 if (!buffer->addr)
340 return -ENOMEM;
341 buffer->len = len;
342 memset(buffer->addr, 0, len);
343 return 0;
344 }
345
346 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
347 {
348 if (buffer->addr) {
349 pci_free_consistent(efx->pci_dev, buffer->len,
350 buffer->addr, buffer->dma_addr);
351 buffer->addr = NULL;
352 }
353 }
354
355 /**************************************************************************
356 *
357 * Falcon TX path
358 *
359 **************************************************************************/
360
361 /* Returns a pointer to the specified transmit descriptor in the TX
362 * descriptor queue belonging to the specified channel.
363 */
364 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
365 unsigned int index)
366 {
367 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
368 }
369
370 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
371 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
372 {
373 unsigned write_ptr;
374 efx_dword_t reg;
375
376 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
377 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
378 efx_writed_page(tx_queue->efx, &reg,
379 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
380 }
381
382
383 /* For each entry inserted into the software descriptor ring, create a
384 * descriptor in the hardware TX descriptor ring (in host memory), and
385 * write a doorbell.
386 */
387 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
388 {
389
390 struct efx_tx_buffer *buffer;
391 efx_qword_t *txd;
392 unsigned write_ptr;
393
394 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
395
396 do {
397 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
398 buffer = &tx_queue->buffer[write_ptr];
399 txd = falcon_tx_desc(tx_queue, write_ptr);
400 ++tx_queue->write_count;
401
402 /* Create TX descriptor ring entry */
403 EFX_POPULATE_QWORD_4(*txd,
404 FSF_AZ_TX_KER_CONT, buffer->continuation,
405 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
406 FSF_AZ_TX_KER_BUF_REGION, 0,
407 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
408 } while (tx_queue->write_count != tx_queue->insert_count);
409
410 wmb(); /* Ensure descriptors are written before they are fetched */
411 falcon_notify_tx_desc(tx_queue);
412 }
413
414 /* Allocate hardware resources for a TX queue */
415 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
416 {
417 struct efx_nic *efx = tx_queue->efx;
418 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
419 EFX_TXQ_SIZE & EFX_TXQ_MASK);
420 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
421 EFX_TXQ_SIZE * sizeof(efx_qword_t));
422 }
423
424 void falcon_init_tx(struct efx_tx_queue *tx_queue)
425 {
426 efx_oword_t tx_desc_ptr;
427 struct efx_nic *efx = tx_queue->efx;
428
429 tx_queue->flushed = false;
430
431 /* Pin TX descriptor ring */
432 falcon_init_special_buffer(efx, &tx_queue->txd);
433
434 /* Push TX descriptor ring to card */
435 EFX_POPULATE_OWORD_10(tx_desc_ptr,
436 FRF_AZ_TX_DESCQ_EN, 1,
437 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
438 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
439 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
440 FRF_AZ_TX_DESCQ_EVQ_ID,
441 tx_queue->channel->channel,
442 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
443 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
444 FRF_AZ_TX_DESCQ_SIZE,
445 __ffs(tx_queue->txd.entries),
446 FRF_AZ_TX_DESCQ_TYPE, 0,
447 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
448
449 if (falcon_rev(efx) >= FALCON_REV_B0) {
450 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
451 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
452 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
453 !csum);
454 }
455
456 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
457 tx_queue->queue);
458
459 if (falcon_rev(efx) < FALCON_REV_B0) {
460 efx_oword_t reg;
461
462 /* Only 128 bits in this register */
463 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
464
465 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
466 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
467 clear_bit_le(tx_queue->queue, (void *)&reg);
468 else
469 set_bit_le(tx_queue->queue, (void *)&reg);
470 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
471 }
472 }
473
474 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
475 {
476 struct efx_nic *efx = tx_queue->efx;
477 efx_oword_t tx_flush_descq;
478
479 /* Post a flush command */
480 EFX_POPULATE_OWORD_2(tx_flush_descq,
481 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
482 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
483 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
484 }
485
486 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
487 {
488 struct efx_nic *efx = tx_queue->efx;
489 efx_oword_t tx_desc_ptr;
490
491 /* The queue should have been flushed */
492 WARN_ON(!tx_queue->flushed);
493
494 /* Remove TX descriptor ring from card */
495 EFX_ZERO_OWORD(tx_desc_ptr);
496 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
497 tx_queue->queue);
498
499 /* Unpin TX descriptor ring */
500 falcon_fini_special_buffer(efx, &tx_queue->txd);
501 }
502
503 /* Free buffers backing TX queue */
504 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
505 {
506 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
507 }
508
509 /**************************************************************************
510 *
511 * Falcon RX path
512 *
513 **************************************************************************/
514
515 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
516 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
517 unsigned int index)
518 {
519 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
520 }
521
522 /* This creates an entry in the RX descriptor queue */
523 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
524 unsigned index)
525 {
526 struct efx_rx_buffer *rx_buf;
527 efx_qword_t *rxd;
528
529 rxd = falcon_rx_desc(rx_queue, index);
530 rx_buf = efx_rx_buffer(rx_queue, index);
531 EFX_POPULATE_QWORD_3(*rxd,
532 FSF_AZ_RX_KER_BUF_SIZE,
533 rx_buf->len -
534 rx_queue->efx->type->rx_buffer_padding,
535 FSF_AZ_RX_KER_BUF_REGION, 0,
536 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
537 }
538
539 /* This writes to the RX_DESC_WPTR register for the specified receive
540 * descriptor ring.
541 */
542 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
543 {
544 efx_dword_t reg;
545 unsigned write_ptr;
546
547 while (rx_queue->notified_count != rx_queue->added_count) {
548 falcon_build_rx_desc(rx_queue,
549 rx_queue->notified_count &
550 EFX_RXQ_MASK);
551 ++rx_queue->notified_count;
552 }
553
554 wmb();
555 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
556 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
557 efx_writed_page(rx_queue->efx, &reg,
558 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
559 }
560
561 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
562 {
563 struct efx_nic *efx = rx_queue->efx;
564 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
565 EFX_RXQ_SIZE & EFX_RXQ_MASK);
566 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
567 EFX_RXQ_SIZE * sizeof(efx_qword_t));
568 }
569
570 void falcon_init_rx(struct efx_rx_queue *rx_queue)
571 {
572 efx_oword_t rx_desc_ptr;
573 struct efx_nic *efx = rx_queue->efx;
574 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
575 bool iscsi_digest_en = is_b0;
576
577 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
578 rx_queue->queue, rx_queue->rxd.index,
579 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
580
581 rx_queue->flushed = false;
582
583 /* Pin RX descriptor ring */
584 falcon_init_special_buffer(efx, &rx_queue->rxd);
585
586 /* Push RX descriptor ring to card */
587 EFX_POPULATE_OWORD_10(rx_desc_ptr,
588 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
589 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
590 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
591 FRF_AZ_RX_DESCQ_EVQ_ID,
592 rx_queue->channel->channel,
593 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
594 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
595 FRF_AZ_RX_DESCQ_SIZE,
596 __ffs(rx_queue->rxd.entries),
597 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
598 /* For >=B0 this is scatter so disable */
599 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
600 FRF_AZ_RX_DESCQ_EN, 1);
601 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
602 rx_queue->queue);
603 }
604
605 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
606 {
607 struct efx_nic *efx = rx_queue->efx;
608 efx_oword_t rx_flush_descq;
609
610 /* Post a flush command */
611 EFX_POPULATE_OWORD_2(rx_flush_descq,
612 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
613 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
614 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
615 }
616
617 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
618 {
619 efx_oword_t rx_desc_ptr;
620 struct efx_nic *efx = rx_queue->efx;
621
622 /* The queue should already have been flushed */
623 WARN_ON(!rx_queue->flushed);
624
625 /* Remove RX descriptor ring from card */
626 EFX_ZERO_OWORD(rx_desc_ptr);
627 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
628 rx_queue->queue);
629
630 /* Unpin RX descriptor ring */
631 falcon_fini_special_buffer(efx, &rx_queue->rxd);
632 }
633
634 /* Free buffers backing RX queue */
635 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
636 {
637 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
638 }
639
640 /**************************************************************************
641 *
642 * Falcon event queue processing
643 * Event queues are processed by per-channel tasklets.
644 *
645 **************************************************************************/
646
647 /* Update a channel's event queue's read pointer (RPTR) register
648 *
649 * This writes the EVQ_RPTR_REG register for the specified channel's
650 * event queue.
651 *
652 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
653 * whereas channel->eventq_read_ptr contains the index of the "next to
654 * read" event.
655 */
656 void falcon_eventq_read_ack(struct efx_channel *channel)
657 {
658 efx_dword_t reg;
659 struct efx_nic *efx = channel->efx;
660
661 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
662 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
663 channel->channel);
664 }
665
666 /* Use HW to insert a SW defined event */
667 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
668 {
669 efx_oword_t drv_ev_reg;
670
671 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
672 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
673 drv_ev_reg.u32[0] = event->u32[0];
674 drv_ev_reg.u32[1] = event->u32[1];
675 drv_ev_reg.u32[2] = 0;
676 drv_ev_reg.u32[3] = 0;
677 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
678 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
679 }
680
681 /* Handle a transmit completion event
682 *
683 * Falcon batches TX completion events; the message we receive is of
684 * the form "complete all TX events up to this index".
685 */
686 static void falcon_handle_tx_event(struct efx_channel *channel,
687 efx_qword_t *event)
688 {
689 unsigned int tx_ev_desc_ptr;
690 unsigned int tx_ev_q_label;
691 struct efx_tx_queue *tx_queue;
692 struct efx_nic *efx = channel->efx;
693
694 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
695 /* Transmit completion */
696 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
697 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
698 tx_queue = &efx->tx_queue[tx_ev_q_label];
699 channel->irq_mod_score +=
700 (tx_ev_desc_ptr - tx_queue->read_count) &
701 EFX_TXQ_MASK;
702 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
703 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
704 /* Rewrite the FIFO write pointer */
705 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
706 tx_queue = &efx->tx_queue[tx_ev_q_label];
707
708 if (efx_dev_registered(efx))
709 netif_tx_lock(efx->net_dev);
710 falcon_notify_tx_desc(tx_queue);
711 if (efx_dev_registered(efx))
712 netif_tx_unlock(efx->net_dev);
713 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
714 EFX_WORKAROUND_10727(efx)) {
715 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
716 } else {
717 EFX_ERR(efx, "channel %d unexpected TX event "
718 EFX_QWORD_FMT"\n", channel->channel,
719 EFX_QWORD_VAL(*event));
720 }
721 }
722
723 /* Detect errors included in the rx_evt_pkt_ok bit. */
724 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
725 const efx_qword_t *event,
726 bool *rx_ev_pkt_ok,
727 bool *discard)
728 {
729 struct efx_nic *efx = rx_queue->efx;
730 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
731 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
732 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
733 bool rx_ev_other_err, rx_ev_pause_frm;
734 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
735 unsigned rx_ev_pkt_type;
736
737 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
738 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
739 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
740 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
741 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
742 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
743 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
744 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
745 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
746 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
747 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
748 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
749 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
750 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
751 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
752 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
753
754 /* Every error apart from tobe_disc and pause_frm */
755 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
756 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
757 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
758
759 /* Count errors that are not in MAC stats. Ignore expected
760 * checksum errors during self-test. */
761 if (rx_ev_frm_trunc)
762 ++rx_queue->channel->n_rx_frm_trunc;
763 else if (rx_ev_tobe_disc)
764 ++rx_queue->channel->n_rx_tobe_disc;
765 else if (!efx->loopback_selftest) {
766 if (rx_ev_ip_hdr_chksum_err)
767 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
768 else if (rx_ev_tcp_udp_chksum_err)
769 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
770 }
771 if (rx_ev_ip_frag_err)
772 ++rx_queue->channel->n_rx_ip_frag_err;
773
774 /* The frame must be discarded if any of these are true. */
775 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
776 rx_ev_tobe_disc | rx_ev_pause_frm);
777
778 /* TOBE_DISC is expected on unicast mismatches; don't print out an
779 * error message. FRM_TRUNC indicates RXDP dropped the packet due
780 * to a FIFO overflow.
781 */
782 #ifdef EFX_ENABLE_DEBUG
783 if (rx_ev_other_err) {
784 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
785 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
786 rx_queue->queue, EFX_QWORD_VAL(*event),
787 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
788 rx_ev_ip_hdr_chksum_err ?
789 " [IP_HDR_CHKSUM_ERR]" : "",
790 rx_ev_tcp_udp_chksum_err ?
791 " [TCP_UDP_CHKSUM_ERR]" : "",
792 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
793 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
794 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
795 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
796 rx_ev_pause_frm ? " [PAUSE]" : "");
797 }
798 #endif
799 }
800
801 /* Handle receive events that are not in-order. */
802 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
803 unsigned index)
804 {
805 struct efx_nic *efx = rx_queue->efx;
806 unsigned expected, dropped;
807
808 expected = rx_queue->removed_count & EFX_RXQ_MASK;
809 dropped = (index - expected) & EFX_RXQ_MASK;
810 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
811 dropped, index, expected);
812
813 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
814 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
815 }
816
817 /* Handle a packet received event
818 *
819 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
820 * wrong destination address
821 * Also "is multicast" and "matches multicast filter" flags can be used to
822 * discard non-matching multicast packets.
823 */
824 static void falcon_handle_rx_event(struct efx_channel *channel,
825 const efx_qword_t *event)
826 {
827 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
828 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
829 unsigned expected_ptr;
830 bool rx_ev_pkt_ok, discard = false, checksummed;
831 struct efx_rx_queue *rx_queue;
832 struct efx_nic *efx = channel->efx;
833
834 /* Basic packet information */
835 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
836 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
837 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
838 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
839 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
840 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
841 channel->channel);
842
843 rx_queue = &efx->rx_queue[channel->channel];
844
845 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
846 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
847 if (unlikely(rx_ev_desc_ptr != expected_ptr))
848 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
849
850 if (likely(rx_ev_pkt_ok)) {
851 /* If packet is marked as OK and packet type is TCP/IPv4 or
852 * UDP/IPv4, then we can rely on the hardware checksum.
853 */
854 checksummed =
855 efx->rx_checksum_enabled &&
856 (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
857 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
858 } else {
859 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
860 &discard);
861 checksummed = false;
862 }
863
864 /* Detect multicast packets that didn't match the filter */
865 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
866 if (rx_ev_mcast_pkt) {
867 unsigned int rx_ev_mcast_hash_match =
868 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
869
870 if (unlikely(!rx_ev_mcast_hash_match))
871 discard = true;
872 }
873
874 channel->irq_mod_score += 2;
875
876 /* Handle received packet */
877 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
878 checksummed, discard);
879 }
880
881 /* Global events are basically PHY events */
882 static void falcon_handle_global_event(struct efx_channel *channel,
883 efx_qword_t *event)
884 {
885 struct efx_nic *efx = channel->efx;
886 bool handled = false;
887
888 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
889 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
890 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
891 efx->phy_op->clear_interrupt(efx);
892 queue_work(efx->workqueue, &efx->phy_work);
893 handled = true;
894 }
895
896 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
897 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
898 queue_work(efx->workqueue, &efx->mac_work);
899 handled = true;
900 }
901
902 if (falcon_rev(efx) <= FALCON_REV_A1 ?
903 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
904 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
905 EFX_ERR(efx, "channel %d seen global RX_RESET "
906 "event. Resetting.\n", channel->channel);
907
908 atomic_inc(&efx->rx_reset);
909 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
910 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
911 handled = true;
912 }
913
914 if (!handled)
915 EFX_ERR(efx, "channel %d unknown global event "
916 EFX_QWORD_FMT "\n", channel->channel,
917 EFX_QWORD_VAL(*event));
918 }
919
920 static void falcon_handle_driver_event(struct efx_channel *channel,
921 efx_qword_t *event)
922 {
923 struct efx_nic *efx = channel->efx;
924 unsigned int ev_sub_code;
925 unsigned int ev_sub_data;
926
927 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
928 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
929
930 switch (ev_sub_code) {
931 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
932 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
933 channel->channel, ev_sub_data);
934 break;
935 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
936 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
937 channel->channel, ev_sub_data);
938 break;
939 case FSE_AZ_EVQ_INIT_DONE_EV:
940 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
941 channel->channel, ev_sub_data);
942 break;
943 case FSE_AZ_SRM_UPD_DONE_EV:
944 EFX_TRACE(efx, "channel %d SRAM update done\n",
945 channel->channel);
946 break;
947 case FSE_AZ_WAKE_UP_EV:
948 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
949 channel->channel, ev_sub_data);
950 break;
951 case FSE_AZ_TIMER_EV:
952 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
953 channel->channel, ev_sub_data);
954 break;
955 case FSE_AA_RX_RECOVER_EV:
956 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
957 "Resetting.\n", channel->channel);
958 atomic_inc(&efx->rx_reset);
959 efx_schedule_reset(efx,
960 EFX_WORKAROUND_6555(efx) ?
961 RESET_TYPE_RX_RECOVERY :
962 RESET_TYPE_DISABLE);
963 break;
964 case FSE_BZ_RX_DSC_ERROR_EV:
965 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
966 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
967 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
968 break;
969 case FSE_BZ_TX_DSC_ERROR_EV:
970 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
971 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
972 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
973 break;
974 default:
975 EFX_TRACE(efx, "channel %d unknown driver event code %d "
976 "data %04x\n", channel->channel, ev_sub_code,
977 ev_sub_data);
978 break;
979 }
980 }
981
982 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
983 {
984 unsigned int read_ptr;
985 efx_qword_t event, *p_event;
986 int ev_code;
987 int rx_packets = 0;
988
989 read_ptr = channel->eventq_read_ptr;
990
991 do {
992 p_event = falcon_event(channel, read_ptr);
993 event = *p_event;
994
995 if (!falcon_event_present(&event))
996 /* End of events */
997 break;
998
999 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1000 channel->channel, EFX_QWORD_VAL(event));
1001
1002 /* Clear this event by marking it all ones */
1003 EFX_SET_QWORD(*p_event);
1004
1005 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1006
1007 switch (ev_code) {
1008 case FSE_AZ_EV_CODE_RX_EV:
1009 falcon_handle_rx_event(channel, &event);
1010 ++rx_packets;
1011 break;
1012 case FSE_AZ_EV_CODE_TX_EV:
1013 falcon_handle_tx_event(channel, &event);
1014 break;
1015 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1016 channel->eventq_magic = EFX_QWORD_FIELD(
1017 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1018 EFX_LOG(channel->efx, "channel %d received generated "
1019 "event "EFX_QWORD_FMT"\n", channel->channel,
1020 EFX_QWORD_VAL(event));
1021 break;
1022 case FSE_AZ_EV_CODE_GLOBAL_EV:
1023 falcon_handle_global_event(channel, &event);
1024 break;
1025 case FSE_AZ_EV_CODE_DRIVER_EV:
1026 falcon_handle_driver_event(channel, &event);
1027 break;
1028 default:
1029 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1030 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1031 ev_code, EFX_QWORD_VAL(event));
1032 }
1033
1034 /* Increment read pointer */
1035 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1036
1037 } while (rx_packets < rx_quota);
1038
1039 channel->eventq_read_ptr = read_ptr;
1040 return rx_packets;
1041 }
1042
1043 void falcon_set_int_moderation(struct efx_channel *channel)
1044 {
1045 efx_dword_t timer_cmd;
1046 struct efx_nic *efx = channel->efx;
1047
1048 /* Set timer register */
1049 if (channel->irq_moderation) {
1050 EFX_POPULATE_DWORD_2(timer_cmd,
1051 FRF_AB_TC_TIMER_MODE,
1052 FFE_BB_TIMER_MODE_INT_HLDOFF,
1053 FRF_AB_TC_TIMER_VAL,
1054 channel->irq_moderation - 1);
1055 } else {
1056 EFX_POPULATE_DWORD_2(timer_cmd,
1057 FRF_AB_TC_TIMER_MODE,
1058 FFE_BB_TIMER_MODE_DIS,
1059 FRF_AB_TC_TIMER_VAL, 0);
1060 }
1061 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1062 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1063 channel->channel);
1064
1065 }
1066
1067 /* Allocate buffer table entries for event queue */
1068 int falcon_probe_eventq(struct efx_channel *channel)
1069 {
1070 struct efx_nic *efx = channel->efx;
1071 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1072 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1073 return falcon_alloc_special_buffer(efx, &channel->eventq,
1074 EFX_EVQ_SIZE * sizeof(efx_qword_t));
1075 }
1076
1077 void falcon_init_eventq(struct efx_channel *channel)
1078 {
1079 efx_oword_t evq_ptr;
1080 struct efx_nic *efx = channel->efx;
1081
1082 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1083 channel->channel, channel->eventq.index,
1084 channel->eventq.index + channel->eventq.entries - 1);
1085
1086 /* Pin event queue buffer */
1087 falcon_init_special_buffer(efx, &channel->eventq);
1088
1089 /* Fill event queue with all ones (i.e. empty events) */
1090 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1091
1092 /* Push event queue to card */
1093 EFX_POPULATE_OWORD_3(evq_ptr,
1094 FRF_AZ_EVQ_EN, 1,
1095 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1096 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1097 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1098 channel->channel);
1099
1100 falcon_set_int_moderation(channel);
1101 }
1102
1103 void falcon_fini_eventq(struct efx_channel *channel)
1104 {
1105 efx_oword_t eventq_ptr;
1106 struct efx_nic *efx = channel->efx;
1107
1108 /* Remove event queue from card */
1109 EFX_ZERO_OWORD(eventq_ptr);
1110 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1111 channel->channel);
1112
1113 /* Unpin event queue */
1114 falcon_fini_special_buffer(efx, &channel->eventq);
1115 }
1116
1117 /* Free buffers backing event queue */
1118 void falcon_remove_eventq(struct efx_channel *channel)
1119 {
1120 falcon_free_special_buffer(channel->efx, &channel->eventq);
1121 }
1122
1123
1124 /* Generates a test event on the event queue. A subsequent call to
1125 * process_eventq() should pick up the event and place the value of
1126 * "magic" into channel->eventq_magic;
1127 */
1128 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1129 {
1130 efx_qword_t test_event;
1131
1132 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1133 FSE_AZ_EV_CODE_DRV_GEN_EV,
1134 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1135 falcon_generate_event(channel, &test_event);
1136 }
1137
1138 void falcon_sim_phy_event(struct efx_nic *efx)
1139 {
1140 efx_qword_t phy_event;
1141
1142 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1143 FSE_AZ_EV_CODE_GLOBAL_EV);
1144 if (EFX_IS10G(efx))
1145 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1146 else
1147 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1148
1149 falcon_generate_event(&efx->channel[0], &phy_event);
1150 }
1151
1152 /**************************************************************************
1153 *
1154 * Flush handling
1155 *
1156 **************************************************************************/
1157
1158
1159 static void falcon_poll_flush_events(struct efx_nic *efx)
1160 {
1161 struct efx_channel *channel = &efx->channel[0];
1162 struct efx_tx_queue *tx_queue;
1163 struct efx_rx_queue *rx_queue;
1164 unsigned int read_ptr = channel->eventq_read_ptr;
1165 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1166
1167 do {
1168 efx_qword_t *event = falcon_event(channel, read_ptr);
1169 int ev_code, ev_sub_code, ev_queue;
1170 bool ev_failed;
1171
1172 if (!falcon_event_present(event))
1173 break;
1174
1175 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1176 ev_sub_code = EFX_QWORD_FIELD(*event,
1177 FSF_AZ_DRIVER_EV_SUBCODE);
1178 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1179 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1180 ev_queue = EFX_QWORD_FIELD(*event,
1181 FSF_AZ_DRIVER_EV_SUBDATA);
1182 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1183 tx_queue = efx->tx_queue + ev_queue;
1184 tx_queue->flushed = true;
1185 }
1186 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1187 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1188 ev_queue = EFX_QWORD_FIELD(
1189 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1190 ev_failed = EFX_QWORD_FIELD(
1191 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1192 if (ev_queue < efx->n_rx_queues) {
1193 rx_queue = efx->rx_queue + ev_queue;
1194
1195 /* retry the rx flush */
1196 if (ev_failed)
1197 falcon_flush_rx_queue(rx_queue);
1198 else
1199 rx_queue->flushed = true;
1200 }
1201 }
1202
1203 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1204 } while (read_ptr != end_ptr);
1205 }
1206
1207 /* Handle tx and rx flushes at the same time, since they run in
1208 * parallel in the hardware and there's no reason for us to
1209 * serialise them */
1210 int falcon_flush_queues(struct efx_nic *efx)
1211 {
1212 struct efx_rx_queue *rx_queue;
1213 struct efx_tx_queue *tx_queue;
1214 int i;
1215 bool outstanding;
1216
1217 /* Issue flush requests */
1218 efx_for_each_tx_queue(tx_queue, efx) {
1219 tx_queue->flushed = false;
1220 falcon_flush_tx_queue(tx_queue);
1221 }
1222 efx_for_each_rx_queue(rx_queue, efx) {
1223 rx_queue->flushed = false;
1224 falcon_flush_rx_queue(rx_queue);
1225 }
1226
1227 /* Poll the evq looking for flush completions. Since we're not pushing
1228 * any more rx or tx descriptors at this point, we're in no danger of
1229 * overflowing the evq whilst we wait */
1230 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1231 msleep(FALCON_FLUSH_INTERVAL);
1232 falcon_poll_flush_events(efx);
1233
1234 /* Check if every queue has been succesfully flushed */
1235 outstanding = false;
1236 efx_for_each_tx_queue(tx_queue, efx)
1237 outstanding |= !tx_queue->flushed;
1238 efx_for_each_rx_queue(rx_queue, efx)
1239 outstanding |= !rx_queue->flushed;
1240 if (!outstanding)
1241 return 0;
1242 }
1243
1244 /* Mark the queues as all flushed. We're going to return failure
1245 * leading to a reset, or fake up success anyway. "flushed" now
1246 * indicates that we tried to flush. */
1247 efx_for_each_tx_queue(tx_queue, efx) {
1248 if (!tx_queue->flushed)
1249 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1250 tx_queue->queue);
1251 tx_queue->flushed = true;
1252 }
1253 efx_for_each_rx_queue(rx_queue, efx) {
1254 if (!rx_queue->flushed)
1255 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1256 rx_queue->queue);
1257 rx_queue->flushed = true;
1258 }
1259
1260 if (EFX_WORKAROUND_7803(efx))
1261 return 0;
1262
1263 return -ETIMEDOUT;
1264 }
1265
1266 /**************************************************************************
1267 *
1268 * Falcon hardware interrupts
1269 * The hardware interrupt handler does very little work; all the event
1270 * queue processing is carried out by per-channel tasklets.
1271 *
1272 **************************************************************************/
1273
1274 /* Enable/disable/generate Falcon interrupts */
1275 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1276 int force)
1277 {
1278 efx_oword_t int_en_reg_ker;
1279
1280 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1281 FRF_AZ_KER_INT_KER, force,
1282 FRF_AZ_DRV_INT_EN_KER, enabled);
1283 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1284 }
1285
1286 void falcon_enable_interrupts(struct efx_nic *efx)
1287 {
1288 efx_oword_t int_adr_reg_ker;
1289 struct efx_channel *channel;
1290
1291 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1292 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1293
1294 /* Program address */
1295 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1296 FRF_AZ_NORM_INT_VEC_DIS_KER,
1297 EFX_INT_MODE_USE_MSI(efx),
1298 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1299 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1300
1301 /* Enable interrupts */
1302 falcon_interrupts(efx, 1, 0);
1303
1304 /* Force processing of all the channels to get the EVQ RPTRs up to
1305 date */
1306 efx_for_each_channel(channel, efx)
1307 efx_schedule_channel(channel);
1308 }
1309
1310 void falcon_disable_interrupts(struct efx_nic *efx)
1311 {
1312 /* Disable interrupts */
1313 falcon_interrupts(efx, 0, 0);
1314 }
1315
1316 /* Generate a Falcon test interrupt
1317 * Interrupt must already have been enabled, otherwise nasty things
1318 * may happen.
1319 */
1320 void falcon_generate_interrupt(struct efx_nic *efx)
1321 {
1322 falcon_interrupts(efx, 1, 1);
1323 }
1324
1325 /* Acknowledge a legacy interrupt from Falcon
1326 *
1327 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1328 *
1329 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1330 * BIU. Interrupt acknowledge is read sensitive so must write instead
1331 * (then read to ensure the BIU collector is flushed)
1332 *
1333 * NB most hardware supports MSI interrupts
1334 */
1335 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1336 {
1337 efx_dword_t reg;
1338
1339 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1340 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1341 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1342 }
1343
1344 /* Process a fatal interrupt
1345 * Disable bus mastering ASAP and schedule a reset
1346 */
1347 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1348 {
1349 struct falcon_nic_data *nic_data = efx->nic_data;
1350 efx_oword_t *int_ker = efx->irq_status.addr;
1351 efx_oword_t fatal_intr;
1352 int error, mem_perr;
1353
1354 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1355 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1356
1357 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1358 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1359 EFX_OWORD_VAL(fatal_intr),
1360 error ? "disabling bus mastering" : "no recognised error");
1361 if (error == 0)
1362 goto out;
1363
1364 /* If this is a memory parity error dump which blocks are offending */
1365 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1366 if (mem_perr) {
1367 efx_oword_t reg;
1368 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1369 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1370 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1371 }
1372
1373 /* Disable both devices */
1374 pci_clear_master(efx->pci_dev);
1375 if (FALCON_IS_DUAL_FUNC(efx))
1376 pci_clear_master(nic_data->pci_dev2);
1377 falcon_disable_interrupts(efx);
1378
1379 /* Count errors and reset or disable the NIC accordingly */
1380 if (efx->int_error_count == 0 ||
1381 time_after(jiffies, efx->int_error_expire)) {
1382 efx->int_error_count = 0;
1383 efx->int_error_expire =
1384 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1385 }
1386 if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
1387 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1388 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1389 } else {
1390 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1391 "NIC will be disabled\n");
1392 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1393 }
1394 out:
1395 return IRQ_HANDLED;
1396 }
1397
1398 /* Handle a legacy interrupt from Falcon
1399 * Acknowledges the interrupt and schedule event queue processing.
1400 */
1401 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1402 {
1403 struct efx_nic *efx = dev_id;
1404 efx_oword_t *int_ker = efx->irq_status.addr;
1405 irqreturn_t result = IRQ_NONE;
1406 struct efx_channel *channel;
1407 efx_dword_t reg;
1408 u32 queues;
1409 int syserr;
1410
1411 /* Read the ISR which also ACKs the interrupts */
1412 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1413 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1414
1415 /* Check to see if we have a serious error condition */
1416 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1417 if (unlikely(syserr))
1418 return falcon_fatal_interrupt(efx);
1419
1420 /* Schedule processing of any interrupting queues */
1421 efx_for_each_channel(channel, efx) {
1422 if ((queues & 1) ||
1423 falcon_event_present(
1424 falcon_event(channel, channel->eventq_read_ptr))) {
1425 efx_schedule_channel(channel);
1426 result = IRQ_HANDLED;
1427 }
1428 queues >>= 1;
1429 }
1430
1431 if (result == IRQ_HANDLED) {
1432 efx->last_irq_cpu = raw_smp_processor_id();
1433 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1434 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1435 }
1436
1437 return result;
1438 }
1439
1440
1441 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1442 {
1443 struct efx_nic *efx = dev_id;
1444 efx_oword_t *int_ker = efx->irq_status.addr;
1445 struct efx_channel *channel;
1446 int syserr;
1447 int queues;
1448
1449 /* Check to see if this is our interrupt. If it isn't, we
1450 * exit without having touched the hardware.
1451 */
1452 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1453 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1454 raw_smp_processor_id());
1455 return IRQ_NONE;
1456 }
1457 efx->last_irq_cpu = raw_smp_processor_id();
1458 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1459 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1460
1461 /* Check to see if we have a serious error condition */
1462 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1463 if (unlikely(syserr))
1464 return falcon_fatal_interrupt(efx);
1465
1466 /* Determine interrupting queues, clear interrupt status
1467 * register and acknowledge the device interrupt.
1468 */
1469 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1470 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1471 EFX_ZERO_OWORD(*int_ker);
1472 wmb(); /* Ensure the vector is cleared before interrupt ack */
1473 falcon_irq_ack_a1(efx);
1474
1475 /* Schedule processing of any interrupting queues */
1476 channel = &efx->channel[0];
1477 while (queues) {
1478 if (queues & 0x01)
1479 efx_schedule_channel(channel);
1480 channel++;
1481 queues >>= 1;
1482 }
1483
1484 return IRQ_HANDLED;
1485 }
1486
1487 /* Handle an MSI interrupt from Falcon
1488 *
1489 * Handle an MSI hardware interrupt. This routine schedules event
1490 * queue processing. No interrupt acknowledgement cycle is necessary.
1491 * Also, we never need to check that the interrupt is for us, since
1492 * MSI interrupts cannot be shared.
1493 */
1494 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1495 {
1496 struct efx_channel *channel = dev_id;
1497 struct efx_nic *efx = channel->efx;
1498 efx_oword_t *int_ker = efx->irq_status.addr;
1499 int syserr;
1500
1501 efx->last_irq_cpu = raw_smp_processor_id();
1502 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1503 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1504
1505 /* Check to see if we have a serious error condition */
1506 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1507 if (unlikely(syserr))
1508 return falcon_fatal_interrupt(efx);
1509
1510 /* Schedule processing of the channel */
1511 efx_schedule_channel(channel);
1512
1513 return IRQ_HANDLED;
1514 }
1515
1516
1517 /* Setup RSS indirection table.
1518 * This maps from the hash value of the packet to RXQ
1519 */
1520 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1521 {
1522 int i = 0;
1523 unsigned long offset;
1524 efx_dword_t dword;
1525
1526 if (falcon_rev(efx) < FALCON_REV_B0)
1527 return;
1528
1529 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1530 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1531 offset += 0x10) {
1532 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1533 i % efx->n_rx_queues);
1534 efx_writed(efx, &dword, offset);
1535 i++;
1536 }
1537 }
1538
1539 /* Hook interrupt handler(s)
1540 * Try MSI and then legacy interrupts.
1541 */
1542 int falcon_init_interrupt(struct efx_nic *efx)
1543 {
1544 struct efx_channel *channel;
1545 int rc;
1546
1547 if (!EFX_INT_MODE_USE_MSI(efx)) {
1548 irq_handler_t handler;
1549 if (falcon_rev(efx) >= FALCON_REV_B0)
1550 handler = falcon_legacy_interrupt_b0;
1551 else
1552 handler = falcon_legacy_interrupt_a1;
1553
1554 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1555 efx->name, efx);
1556 if (rc) {
1557 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1558 efx->pci_dev->irq);
1559 goto fail1;
1560 }
1561 return 0;
1562 }
1563
1564 /* Hook MSI or MSI-X interrupt */
1565 efx_for_each_channel(channel, efx) {
1566 rc = request_irq(channel->irq, falcon_msi_interrupt,
1567 IRQF_PROBE_SHARED, /* Not shared */
1568 channel->name, channel);
1569 if (rc) {
1570 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1571 goto fail2;
1572 }
1573 }
1574
1575 return 0;
1576
1577 fail2:
1578 efx_for_each_channel(channel, efx)
1579 free_irq(channel->irq, channel);
1580 fail1:
1581 return rc;
1582 }
1583
1584 void falcon_fini_interrupt(struct efx_nic *efx)
1585 {
1586 struct efx_channel *channel;
1587 efx_oword_t reg;
1588
1589 /* Disable MSI/MSI-X interrupts */
1590 efx_for_each_channel(channel, efx) {
1591 if (channel->irq)
1592 free_irq(channel->irq, channel);
1593 }
1594
1595 /* ACK legacy interrupt */
1596 if (falcon_rev(efx) >= FALCON_REV_B0)
1597 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1598 else
1599 falcon_irq_ack_a1(efx);
1600
1601 /* Disable legacy interrupt */
1602 if (efx->legacy_irq)
1603 free_irq(efx->legacy_irq, efx);
1604 }
1605
1606 /**************************************************************************
1607 *
1608 * EEPROM/flash
1609 *
1610 **************************************************************************
1611 */
1612
1613 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1614
1615 static int falcon_spi_poll(struct efx_nic *efx)
1616 {
1617 efx_oword_t reg;
1618 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1619 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1620 }
1621
1622 /* Wait for SPI command completion */
1623 static int falcon_spi_wait(struct efx_nic *efx)
1624 {
1625 /* Most commands will finish quickly, so we start polling at
1626 * very short intervals. Sometimes the command may have to
1627 * wait for VPD or expansion ROM access outside of our
1628 * control, so we allow up to 100 ms. */
1629 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1630 int i;
1631
1632 for (i = 0; i < 10; i++) {
1633 if (!falcon_spi_poll(efx))
1634 return 0;
1635 udelay(10);
1636 }
1637
1638 for (;;) {
1639 if (!falcon_spi_poll(efx))
1640 return 0;
1641 if (time_after_eq(jiffies, timeout)) {
1642 EFX_ERR(efx, "timed out waiting for SPI\n");
1643 return -ETIMEDOUT;
1644 }
1645 schedule_timeout_uninterruptible(1);
1646 }
1647 }
1648
1649 int falcon_spi_cmd(const struct efx_spi_device *spi,
1650 unsigned int command, int address,
1651 const void *in, void *out, size_t len)
1652 {
1653 struct efx_nic *efx = spi->efx;
1654 bool addressed = (address >= 0);
1655 bool reading = (out != NULL);
1656 efx_oword_t reg;
1657 int rc;
1658
1659 /* Input validation */
1660 if (len > FALCON_SPI_MAX_LEN)
1661 return -EINVAL;
1662 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1663
1664 /* Check that previous command is not still running */
1665 rc = falcon_spi_poll(efx);
1666 if (rc)
1667 return rc;
1668
1669 /* Program address register, if we have an address */
1670 if (addressed) {
1671 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1672 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1673 }
1674
1675 /* Program data register, if we have data */
1676 if (in != NULL) {
1677 memcpy(&reg, in, len);
1678 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1679 }
1680
1681 /* Issue read/write command */
1682 EFX_POPULATE_OWORD_7(reg,
1683 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1684 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1685 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1686 FRF_AB_EE_SPI_HCMD_READ, reading,
1687 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1688 FRF_AB_EE_SPI_HCMD_ADBCNT,
1689 (addressed ? spi->addr_len : 0),
1690 FRF_AB_EE_SPI_HCMD_ENC, command);
1691 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1692
1693 /* Wait for read/write to complete */
1694 rc = falcon_spi_wait(efx);
1695 if (rc)
1696 return rc;
1697
1698 /* Read data */
1699 if (out != NULL) {
1700 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1701 memcpy(out, &reg, len);
1702 }
1703
1704 return 0;
1705 }
1706
1707 static size_t
1708 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1709 {
1710 return min(FALCON_SPI_MAX_LEN,
1711 (spi->block_size - (start & (spi->block_size - 1))));
1712 }
1713
1714 static inline u8
1715 efx_spi_munge_command(const struct efx_spi_device *spi,
1716 const u8 command, const unsigned int address)
1717 {
1718 return command | (((address >> 8) & spi->munge_address) << 3);
1719 }
1720
1721 /* Wait up to 10 ms for buffered write completion */
1722 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1723 {
1724 struct efx_nic *efx = spi->efx;
1725 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1726 u8 status;
1727 int rc;
1728
1729 for (;;) {
1730 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1731 &status, sizeof(status));
1732 if (rc)
1733 return rc;
1734 if (!(status & SPI_STATUS_NRDY))
1735 return 0;
1736 if (time_after_eq(jiffies, timeout)) {
1737 EFX_ERR(efx, "SPI write timeout on device %d"
1738 " last status=0x%02x\n",
1739 spi->device_id, status);
1740 return -ETIMEDOUT;
1741 }
1742 schedule_timeout_uninterruptible(1);
1743 }
1744 }
1745
1746 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1747 size_t len, size_t *retlen, u8 *buffer)
1748 {
1749 size_t block_len, pos = 0;
1750 unsigned int command;
1751 int rc = 0;
1752
1753 while (pos < len) {
1754 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1755
1756 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1757 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1758 buffer + pos, block_len);
1759 if (rc)
1760 break;
1761 pos += block_len;
1762
1763 /* Avoid locking up the system */
1764 cond_resched();
1765 if (signal_pending(current)) {
1766 rc = -EINTR;
1767 break;
1768 }
1769 }
1770
1771 if (retlen)
1772 *retlen = pos;
1773 return rc;
1774 }
1775
1776 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1777 size_t len, size_t *retlen, const u8 *buffer)
1778 {
1779 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1780 size_t block_len, pos = 0;
1781 unsigned int command;
1782 int rc = 0;
1783
1784 while (pos < len) {
1785 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1786 if (rc)
1787 break;
1788
1789 block_len = min(len - pos,
1790 falcon_spi_write_limit(spi, start + pos));
1791 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1792 rc = falcon_spi_cmd(spi, command, start + pos,
1793 buffer + pos, NULL, block_len);
1794 if (rc)
1795 break;
1796
1797 rc = falcon_spi_wait_write(spi);
1798 if (rc)
1799 break;
1800
1801 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1802 rc = falcon_spi_cmd(spi, command, start + pos,
1803 NULL, verify_buffer, block_len);
1804 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1805 rc = -EIO;
1806 break;
1807 }
1808
1809 pos += block_len;
1810
1811 /* Avoid locking up the system */
1812 cond_resched();
1813 if (signal_pending(current)) {
1814 rc = -EINTR;
1815 break;
1816 }
1817 }
1818
1819 if (retlen)
1820 *retlen = pos;
1821 return rc;
1822 }
1823
1824 /**************************************************************************
1825 *
1826 * MAC wrapper
1827 *
1828 **************************************************************************
1829 */
1830
1831 static int falcon_reset_macs(struct efx_nic *efx)
1832 {
1833 efx_oword_t reg;
1834 int count;
1835
1836 if (falcon_rev(efx) < FALCON_REV_B0) {
1837 /* It's not safe to use GLB_CTL_REG to reset the
1838 * macs, so instead use the internal MAC resets
1839 */
1840 if (!EFX_IS10G(efx)) {
1841 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1842 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1843 udelay(1000);
1844
1845 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1846 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1847 udelay(1000);
1848 return 0;
1849 } else {
1850 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1851 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1852
1853 for (count = 0; count < 10000; count++) {
1854 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1855 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1856 0)
1857 return 0;
1858 udelay(10);
1859 }
1860
1861 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1862 return -ETIMEDOUT;
1863 }
1864 }
1865
1866 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1867 * the drain sequence with the statistics fetch */
1868 efx_stats_disable(efx);
1869
1870 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1871 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1872 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1873
1874 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1875 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1876 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1877 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1878 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1879
1880 count = 0;
1881 while (1) {
1882 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1883 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1884 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1885 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1886 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1887 count);
1888 break;
1889 }
1890 if (count > 20) {
1891 EFX_ERR(efx, "MAC reset failed\n");
1892 break;
1893 }
1894 count++;
1895 udelay(10);
1896 }
1897
1898 efx_stats_enable(efx);
1899
1900 /* If we've reset the EM block and the link is up, then
1901 * we'll have to kick the XAUI link so the PHY can recover */
1902 if (efx->link_state.up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1903 falcon_reset_xaui(efx);
1904
1905 return 0;
1906 }
1907
1908 void falcon_drain_tx_fifo(struct efx_nic *efx)
1909 {
1910 efx_oword_t reg;
1911
1912 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1913 (efx->loopback_mode != LOOPBACK_NONE))
1914 return;
1915
1916 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1917 /* There is no point in draining more than once */
1918 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1919 return;
1920
1921 falcon_reset_macs(efx);
1922 }
1923
1924 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1925 {
1926 efx_oword_t reg;
1927
1928 if (falcon_rev(efx) < FALCON_REV_B0)
1929 return;
1930
1931 /* Isolate the MAC -> RX */
1932 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1933 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1934 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1935
1936 if (!efx->link_state.up)
1937 falcon_drain_tx_fifo(efx);
1938 }
1939
1940 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1941 {
1942 struct efx_link_state *link_state = &efx->link_state;
1943 efx_oword_t reg;
1944 int link_speed;
1945 bool tx_fc;
1946
1947 switch (link_state->speed) {
1948 case 10000: link_speed = 3; break;
1949 case 1000: link_speed = 2; break;
1950 case 100: link_speed = 1; break;
1951 default: link_speed = 0; break;
1952 }
1953 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1954 * as advertised. Disable to ensure packets are not
1955 * indefinitely held and TX queue can be flushed at any point
1956 * while the link is down. */
1957 EFX_POPULATE_OWORD_5(reg,
1958 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1959 FRF_AB_MAC_BCAD_ACPT, 1,
1960 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1961 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1962 FRF_AB_MAC_SPEED, link_speed);
1963 /* On B0, MAC backpressure can be disabled and packets get
1964 * discarded. */
1965 if (falcon_rev(efx) >= FALCON_REV_B0) {
1966 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1967 !link_state->up);
1968 }
1969
1970 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1971
1972 /* Restore the multicast hash registers. */
1973 falcon_set_multicast_hash(efx);
1974
1975 /* Transmission of pause frames when RX crosses the threshold is
1976 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1977 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1978 tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1979 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1980 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
1981
1982 /* Unisolate the MAC -> RX */
1983 if (falcon_rev(efx) >= FALCON_REV_B0)
1984 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1985 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1986 }
1987
1988 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1989 {
1990 efx_oword_t reg;
1991 u32 *dma_done;
1992 int i;
1993
1994 if (disable_dma_stats)
1995 return 0;
1996
1997 /* Statistics fetch will fail if the MAC is in TX drain */
1998 if (falcon_rev(efx) >= FALCON_REV_B0) {
1999 efx_oword_t temp;
2000 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2001 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2002 return 0;
2003 }
2004
2005 dma_done = (efx->stats_buffer.addr + done_offset);
2006 *dma_done = FALCON_STATS_NOT_DONE;
2007 wmb(); /* ensure done flag is clear */
2008
2009 /* Initiate DMA transfer of stats */
2010 EFX_POPULATE_OWORD_2(reg,
2011 FRF_AB_MAC_STAT_DMA_CMD, 1,
2012 FRF_AB_MAC_STAT_DMA_ADR,
2013 efx->stats_buffer.dma_addr);
2014 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2015
2016 /* Wait for transfer to complete */
2017 for (i = 0; i < 400; i++) {
2018 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2019 rmb(); /* Ensure the stats are valid. */
2020 return 0;
2021 }
2022 udelay(10);
2023 }
2024
2025 EFX_ERR(efx, "timed out waiting for statistics\n");
2026 return -ETIMEDOUT;
2027 }
2028
2029 /**************************************************************************
2030 *
2031 * PHY access via GMII
2032 *
2033 **************************************************************************
2034 */
2035
2036 /* Wait for GMII access to complete */
2037 static int falcon_gmii_wait(struct efx_nic *efx)
2038 {
2039 efx_oword_t md_stat;
2040 int count;
2041
2042 /* wait upto 50ms - taken max from datasheet */
2043 for (count = 0; count < 5000; count++) {
2044 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
2045 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2046 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2047 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2048 EFX_ERR(efx, "error from GMII access "
2049 EFX_OWORD_FMT"\n",
2050 EFX_OWORD_VAL(md_stat));
2051 return -EIO;
2052 }
2053 return 0;
2054 }
2055 udelay(10);
2056 }
2057 EFX_ERR(efx, "timed out waiting for GMII\n");
2058 return -ETIMEDOUT;
2059 }
2060
2061 /* Write an MDIO register of a PHY connected to Falcon. */
2062 static int falcon_mdio_write(struct net_device *net_dev,
2063 int prtad, int devad, u16 addr, u16 value)
2064 {
2065 struct efx_nic *efx = netdev_priv(net_dev);
2066 efx_oword_t reg;
2067 int rc;
2068
2069 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2070 prtad, devad, addr, value);
2071
2072 spin_lock_bh(&efx->phy_lock);
2073
2074 /* Check MDIO not currently being accessed */
2075 rc = falcon_gmii_wait(efx);
2076 if (rc)
2077 goto out;
2078
2079 /* Write the address/ID register */
2080 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2081 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2082
2083 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2084 FRF_AB_MD_DEV_ADR, devad);
2085 efx_writeo(efx, &reg, FR_AB_MD_ID);
2086
2087 /* Write data */
2088 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2089 efx_writeo(efx, &reg, FR_AB_MD_TXD);
2090
2091 EFX_POPULATE_OWORD_2(reg,
2092 FRF_AB_MD_WRC, 1,
2093 FRF_AB_MD_GC, 0);
2094 efx_writeo(efx, &reg, FR_AB_MD_CS);
2095
2096 /* Wait for data to be written */
2097 rc = falcon_gmii_wait(efx);
2098 if (rc) {
2099 /* Abort the write operation */
2100 EFX_POPULATE_OWORD_2(reg,
2101 FRF_AB_MD_WRC, 0,
2102 FRF_AB_MD_GC, 1);
2103 efx_writeo(efx, &reg, FR_AB_MD_CS);
2104 udelay(10);
2105 }
2106
2107 out:
2108 spin_unlock_bh(&efx->phy_lock);
2109 return rc;
2110 }
2111
2112 /* Read an MDIO register of a PHY connected to Falcon. */
2113 static int falcon_mdio_read(struct net_device *net_dev,
2114 int prtad, int devad, u16 addr)
2115 {
2116 struct efx_nic *efx = netdev_priv(net_dev);
2117 efx_oword_t reg;
2118 int rc;
2119
2120 spin_lock_bh(&efx->phy_lock);
2121
2122 /* Check MDIO not currently being accessed */
2123 rc = falcon_gmii_wait(efx);
2124 if (rc)
2125 goto out;
2126
2127 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2128 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2129
2130 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2131 FRF_AB_MD_DEV_ADR, devad);
2132 efx_writeo(efx, &reg, FR_AB_MD_ID);
2133
2134 /* Request data to be read */
2135 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2136 efx_writeo(efx, &reg, FR_AB_MD_CS);
2137
2138 /* Wait for data to become available */
2139 rc = falcon_gmii_wait(efx);
2140 if (rc == 0) {
2141 efx_reado(efx, &reg, FR_AB_MD_RXD);
2142 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2143 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2144 prtad, devad, addr, rc);
2145 } else {
2146 /* Abort the read operation */
2147 EFX_POPULATE_OWORD_2(reg,
2148 FRF_AB_MD_RIC, 0,
2149 FRF_AB_MD_GC, 1);
2150 efx_writeo(efx, &reg, FR_AB_MD_CS);
2151
2152 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2153 prtad, devad, addr, rc);
2154 }
2155
2156 out:
2157 spin_unlock_bh(&efx->phy_lock);
2158 return rc;
2159 }
2160
2161 int falcon_switch_mac(struct efx_nic *efx)
2162 {
2163 struct efx_mac_operations *old_mac_op = efx->mac_op;
2164 efx_oword_t nic_stat;
2165 unsigned strap_val;
2166 int rc = 0;
2167
2168 /* Don't try to fetch MAC stats while we're switching MACs */
2169 efx_stats_disable(efx);
2170
2171 /* Internal loopbacks override the phy speed setting */
2172 if (efx->loopback_mode == LOOPBACK_GMAC) {
2173 efx->link_state.speed = 1000;
2174 efx->link_state.fd = true;
2175 } else if (LOOPBACK_INTERNAL(efx)) {
2176 efx->link_state.speed = 10000;
2177 efx->link_state.fd = true;
2178 }
2179
2180 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2181 efx->mac_op = (EFX_IS10G(efx) ?
2182 &falcon_xmac_operations : &falcon_gmac_operations);
2183
2184 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2185 * changed, because this function is run post online reset */
2186 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2187 strap_val = EFX_IS10G(efx) ? 5 : 3;
2188 if (falcon_rev(efx) >= FALCON_REV_B0) {
2189 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2190 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2191 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2192 } else {
2193 /* Falcon A1 does not support 1G/10G speed switching
2194 * and must not be used with a PHY that does. */
2195 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2196 strap_val);
2197 }
2198
2199 if (old_mac_op == efx->mac_op)
2200 goto out;
2201
2202 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2203 /* Not all macs support a mac-level link state */
2204 efx->mac_up = true;
2205
2206 rc = falcon_reset_macs(efx);
2207 out:
2208 efx_stats_enable(efx);
2209 return rc;
2210 }
2211
2212 /* This call is responsible for hooking in the MAC and PHY operations */
2213 int falcon_probe_port(struct efx_nic *efx)
2214 {
2215 int rc;
2216
2217 switch (efx->phy_type) {
2218 case PHY_TYPE_SFX7101:
2219 efx->phy_op = &falcon_sfx7101_phy_ops;
2220 break;
2221 case PHY_TYPE_SFT9001A:
2222 case PHY_TYPE_SFT9001B:
2223 efx->phy_op = &falcon_sft9001_phy_ops;
2224 break;
2225 case PHY_TYPE_QT2022C2:
2226 case PHY_TYPE_QT2025C:
2227 efx->phy_op = &falcon_qt202x_phy_ops;
2228 break;
2229 default:
2230 EFX_ERR(efx, "Unknown PHY type %d\n",
2231 efx->phy_type);
2232 return -ENODEV;
2233 }
2234
2235 if (efx->phy_op->macs & EFX_XMAC)
2236 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2237 (1 << LOOPBACK_XGXS) |
2238 (1 << LOOPBACK_XAUI));
2239 if (efx->phy_op->macs & EFX_GMAC)
2240 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2241 efx->loopback_modes |= efx->phy_op->loopbacks;
2242
2243 /* Set up MDIO structure for PHY */
2244 efx->mdio.mmds = efx->phy_op->mmds;
2245 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2246 efx->mdio.mdio_read = falcon_mdio_read;
2247 efx->mdio.mdio_write = falcon_mdio_write;
2248
2249 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2250 if (falcon_rev(efx) >= FALCON_REV_B0)
2251 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2252 else
2253 efx->wanted_fc = EFX_FC_RX;
2254
2255 /* Allocate buffer for stats */
2256 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2257 FALCON_MAC_STATS_SIZE);
2258 if (rc)
2259 return rc;
2260 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2261 (u64)efx->stats_buffer.dma_addr,
2262 efx->stats_buffer.addr,
2263 (u64)virt_to_phys(efx->stats_buffer.addr));
2264
2265 return 0;
2266 }
2267
2268 void falcon_remove_port(struct efx_nic *efx)
2269 {
2270 falcon_free_buffer(efx, &efx->stats_buffer);
2271 }
2272
2273 /**************************************************************************
2274 *
2275 * Multicast filtering
2276 *
2277 **************************************************************************
2278 */
2279
2280 void falcon_set_multicast_hash(struct efx_nic *efx)
2281 {
2282 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2283
2284 /* Broadcast packets go through the multicast hash filter.
2285 * ether_crc_le() of the broadcast address is 0xbe2612ff
2286 * so we always add bit 0xff to the mask.
2287 */
2288 set_bit_le(0xff, mc_hash->byte);
2289
2290 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2291 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2292 }
2293
2294
2295 /**************************************************************************
2296 *
2297 * Falcon test code
2298 *
2299 **************************************************************************/
2300
2301 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2302 {
2303 struct falcon_nvconfig *nvconfig;
2304 struct efx_spi_device *spi;
2305 void *region;
2306 int rc, magic_num, struct_ver;
2307 __le16 *word, *limit;
2308 u32 csum;
2309
2310 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2311 if (!spi)
2312 return -EINVAL;
2313
2314 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2315 if (!region)
2316 return -ENOMEM;
2317 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2318
2319 mutex_lock(&efx->spi_lock);
2320 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2321 mutex_unlock(&efx->spi_lock);
2322 if (rc) {
2323 EFX_ERR(efx, "Failed to read %s\n",
2324 efx->spi_flash ? "flash" : "EEPROM");
2325 rc = -EIO;
2326 goto out;
2327 }
2328
2329 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2330 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2331
2332 rc = -EINVAL;
2333 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2334 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2335 goto out;
2336 }
2337 if (struct_ver < 2) {
2338 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2339 goto out;
2340 } else if (struct_ver < 4) {
2341 word = &nvconfig->board_magic_num;
2342 limit = (__le16 *) (nvconfig + 1);
2343 } else {
2344 word = region;
2345 limit = region + FALCON_NVCONFIG_END;
2346 }
2347 for (csum = 0; word < limit; ++word)
2348 csum += le16_to_cpu(*word);
2349
2350 if (~csum & 0xffff) {
2351 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2352 goto out;
2353 }
2354
2355 rc = 0;
2356 if (nvconfig_out)
2357 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2358
2359 out:
2360 kfree(region);
2361 return rc;
2362 }
2363
2364 /* Registers tested in the falcon register test */
2365 static struct {
2366 unsigned address;
2367 efx_oword_t mask;
2368 } efx_test_registers[] = {
2369 { FR_AZ_ADR_REGION,
2370 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2371 { FR_AZ_RX_CFG,
2372 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2373 { FR_AZ_TX_CFG,
2374 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2375 { FR_AZ_TX_RESERVED,
2376 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2377 { FR_AB_MAC_CTRL,
2378 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2379 { FR_AZ_SRM_TX_DC_CFG,
2380 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2381 { FR_AZ_RX_DC_CFG,
2382 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2383 { FR_AZ_RX_DC_PF_WM,
2384 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2385 { FR_BZ_DP_CTRL,
2386 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2387 { FR_AB_GM_CFG2,
2388 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2389 { FR_AB_GMF_CFG0,
2390 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2391 { FR_AB_XM_GLB_CFG,
2392 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2393 { FR_AB_XM_TX_CFG,
2394 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2395 { FR_AB_XM_RX_CFG,
2396 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2397 { FR_AB_XM_RX_PARAM,
2398 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2399 { FR_AB_XM_FC,
2400 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2401 { FR_AB_XM_ADR_LO,
2402 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2403 { FR_AB_XX_SD_CTL,
2404 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2405 };
2406
2407 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2408 const efx_oword_t *mask)
2409 {
2410 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2411 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2412 }
2413
2414 int falcon_test_registers(struct efx_nic *efx)
2415 {
2416 unsigned address = 0, i, j;
2417 efx_oword_t mask, imask, original, reg, buf;
2418
2419 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2420 WARN_ON(!LOOPBACK_INTERNAL(efx));
2421
2422 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2423 address = efx_test_registers[i].address;
2424 mask = imask = efx_test_registers[i].mask;
2425 EFX_INVERT_OWORD(imask);
2426
2427 efx_reado(efx, &original, address);
2428
2429 /* bit sweep on and off */
2430 for (j = 0; j < 128; j++) {
2431 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2432 continue;
2433
2434 /* Test this testable bit can be set in isolation */
2435 EFX_AND_OWORD(reg, original, mask);
2436 EFX_SET_OWORD32(reg, j, j, 1);
2437
2438 efx_writeo(efx, &reg, address);
2439 efx_reado(efx, &buf, address);
2440
2441 if (efx_masked_compare_oword(&reg, &buf, &mask))
2442 goto fail;
2443
2444 /* Test this testable bit can be cleared in isolation */
2445 EFX_OR_OWORD(reg, original, mask);
2446 EFX_SET_OWORD32(reg, j, j, 0);
2447
2448 efx_writeo(efx, &reg, address);
2449 efx_reado(efx, &buf, address);
2450
2451 if (efx_masked_compare_oword(&reg, &buf, &mask))
2452 goto fail;
2453 }
2454
2455 efx_writeo(efx, &original, address);
2456 }
2457
2458 return 0;
2459
2460 fail:
2461 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2462 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2463 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2464 return -EIO;
2465 }
2466
2467 /**************************************************************************
2468 *
2469 * Device reset
2470 *
2471 **************************************************************************
2472 */
2473
2474 /* Resets NIC to known state. This routine must be called in process
2475 * context and is allowed to sleep. */
2476 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2477 {
2478 struct falcon_nic_data *nic_data = efx->nic_data;
2479 efx_oword_t glb_ctl_reg_ker;
2480 int rc;
2481
2482 EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
2483
2484 /* Initiate device reset */
2485 if (method == RESET_TYPE_WORLD) {
2486 rc = pci_save_state(efx->pci_dev);
2487 if (rc) {
2488 EFX_ERR(efx, "failed to backup PCI state of primary "
2489 "function prior to hardware reset\n");
2490 goto fail1;
2491 }
2492 if (FALCON_IS_DUAL_FUNC(efx)) {
2493 rc = pci_save_state(nic_data->pci_dev2);
2494 if (rc) {
2495 EFX_ERR(efx, "failed to backup PCI state of "
2496 "secondary function prior to "
2497 "hardware reset\n");
2498 goto fail2;
2499 }
2500 }
2501
2502 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2503 FRF_AB_EXT_PHY_RST_DUR,
2504 FFE_AB_EXT_PHY_RST_DUR_10240US,
2505 FRF_AB_SWRST, 1);
2506 } else {
2507 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2508 /* exclude PHY from "invisible" reset */
2509 FRF_AB_EXT_PHY_RST_CTL,
2510 method == RESET_TYPE_INVISIBLE,
2511 /* exclude EEPROM/flash and PCIe */
2512 FRF_AB_PCIE_CORE_RST_CTL, 1,
2513 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2514 FRF_AB_PCIE_SD_RST_CTL, 1,
2515 FRF_AB_EE_RST_CTL, 1,
2516 FRF_AB_EXT_PHY_RST_DUR,
2517 FFE_AB_EXT_PHY_RST_DUR_10240US,
2518 FRF_AB_SWRST, 1);
2519 }
2520 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2521
2522 EFX_LOG(efx, "waiting for hardware reset\n");
2523 schedule_timeout_uninterruptible(HZ / 20);
2524
2525 /* Restore PCI configuration if needed */
2526 if (method == RESET_TYPE_WORLD) {
2527 if (FALCON_IS_DUAL_FUNC(efx)) {
2528 rc = pci_restore_state(nic_data->pci_dev2);
2529 if (rc) {
2530 EFX_ERR(efx, "failed to restore PCI config for "
2531 "the secondary function\n");
2532 goto fail3;
2533 }
2534 }
2535 rc = pci_restore_state(efx->pci_dev);
2536 if (rc) {
2537 EFX_ERR(efx, "failed to restore PCI config for the "
2538 "primary function\n");
2539 goto fail4;
2540 }
2541 EFX_LOG(efx, "successfully restored PCI config\n");
2542 }
2543
2544 /* Assert that reset complete */
2545 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2546 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2547 rc = -ETIMEDOUT;
2548 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2549 goto fail5;
2550 }
2551 EFX_LOG(efx, "hardware reset complete\n");
2552
2553 return 0;
2554
2555 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2556 fail2:
2557 fail3:
2558 pci_restore_state(efx->pci_dev);
2559 fail1:
2560 fail4:
2561 fail5:
2562 return rc;
2563 }
2564
2565 /* Zeroes out the SRAM contents. This routine must be called in
2566 * process context and is allowed to sleep.
2567 */
2568 static int falcon_reset_sram(struct efx_nic *efx)
2569 {
2570 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2571 int count;
2572
2573 /* Set the SRAM wake/sleep GPIO appropriately. */
2574 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2575 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2576 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2577 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2578
2579 /* Initiate SRAM reset */
2580 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2581 FRF_AZ_SRM_INIT_EN, 1,
2582 FRF_AZ_SRM_NB_SZ, 0);
2583 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2584
2585 /* Wait for SRAM reset to complete */
2586 count = 0;
2587 do {
2588 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2589
2590 /* SRAM reset is slow; expect around 16ms */
2591 schedule_timeout_uninterruptible(HZ / 50);
2592
2593 /* Check for reset complete */
2594 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2595 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2596 EFX_LOG(efx, "SRAM reset complete\n");
2597
2598 return 0;
2599 }
2600 } while (++count < 20); /* wait upto 0.4 sec */
2601
2602 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2603 return -ETIMEDOUT;
2604 }
2605
2606 static int falcon_spi_device_init(struct efx_nic *efx,
2607 struct efx_spi_device **spi_device_ret,
2608 unsigned int device_id, u32 device_type)
2609 {
2610 struct efx_spi_device *spi_device;
2611
2612 if (device_type != 0) {
2613 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2614 if (!spi_device)
2615 return -ENOMEM;
2616 spi_device->device_id = device_id;
2617 spi_device->size =
2618 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2619 spi_device->addr_len =
2620 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2621 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2622 spi_device->addr_len == 1);
2623 spi_device->erase_command =
2624 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2625 spi_device->erase_size =
2626 1 << SPI_DEV_TYPE_FIELD(device_type,
2627 SPI_DEV_TYPE_ERASE_SIZE);
2628 spi_device->block_size =
2629 1 << SPI_DEV_TYPE_FIELD(device_type,
2630 SPI_DEV_TYPE_BLOCK_SIZE);
2631
2632 spi_device->efx = efx;
2633 } else {
2634 spi_device = NULL;
2635 }
2636
2637 kfree(*spi_device_ret);
2638 *spi_device_ret = spi_device;
2639 return 0;
2640 }
2641
2642
2643 static void falcon_remove_spi_devices(struct efx_nic *efx)
2644 {
2645 kfree(efx->spi_eeprom);
2646 efx->spi_eeprom = NULL;
2647 kfree(efx->spi_flash);
2648 efx->spi_flash = NULL;
2649 }
2650
2651 /* Extract non-volatile configuration */
2652 static int falcon_probe_nvconfig(struct efx_nic *efx)
2653 {
2654 struct falcon_nvconfig *nvconfig;
2655 int board_rev;
2656 int rc;
2657
2658 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2659 if (!nvconfig)
2660 return -ENOMEM;
2661
2662 rc = falcon_read_nvram(efx, nvconfig);
2663 if (rc == -EINVAL) {
2664 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2665 efx->phy_type = PHY_TYPE_NONE;
2666 efx->mdio.prtad = MDIO_PRTAD_NONE;
2667 board_rev = 0;
2668 rc = 0;
2669 } else if (rc) {
2670 goto fail1;
2671 } else {
2672 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2673 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2674
2675 efx->phy_type = v2->port0_phy_type;
2676 efx->mdio.prtad = v2->port0_phy_addr;
2677 board_rev = le16_to_cpu(v2->board_revision);
2678
2679 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2680 rc = falcon_spi_device_init(
2681 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2682 le32_to_cpu(v3->spi_device_type
2683 [FFE_AB_SPI_DEVICE_FLASH]));
2684 if (rc)
2685 goto fail2;
2686 rc = falcon_spi_device_init(
2687 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2688 le32_to_cpu(v3->spi_device_type
2689 [FFE_AB_SPI_DEVICE_EEPROM]));
2690 if (rc)
2691 goto fail2;
2692 }
2693 }
2694
2695 /* Read the MAC addresses */
2696 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2697
2698 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2699
2700 falcon_probe_board(efx, board_rev);
2701
2702 kfree(nvconfig);
2703 return 0;
2704
2705 fail2:
2706 falcon_remove_spi_devices(efx);
2707 fail1:
2708 kfree(nvconfig);
2709 return rc;
2710 }
2711
2712 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2713 * count, port speed). Set workaround and feature flags accordingly.
2714 */
2715 static int falcon_probe_nic_variant(struct efx_nic *efx)
2716 {
2717 efx_oword_t altera_build;
2718 efx_oword_t nic_stat;
2719
2720 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2721 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2722 EFX_ERR(efx, "Falcon FPGA not supported\n");
2723 return -ENODEV;
2724 }
2725
2726 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2727
2728 switch (falcon_rev(efx)) {
2729 case FALCON_REV_A0:
2730 case 0xff:
2731 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2732 return -ENODEV;
2733
2734 case FALCON_REV_A1:
2735 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2736 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2737 return -ENODEV;
2738 }
2739 break;
2740
2741 case FALCON_REV_B0:
2742 break;
2743
2744 default:
2745 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2746 return -ENODEV;
2747 }
2748
2749 /* Initial assumed speed */
2750 efx->link_state.speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2751
2752 return 0;
2753 }
2754
2755 /* Probe all SPI devices on the NIC */
2756 static void falcon_probe_spi_devices(struct efx_nic *efx)
2757 {
2758 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2759 int boot_dev;
2760
2761 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2762 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2763 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2764
2765 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2766 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2767 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2768 EFX_LOG(efx, "Booted from %s\n",
2769 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2770 } else {
2771 /* Disable VPD and set clock dividers to safe
2772 * values for initial programming. */
2773 boot_dev = -1;
2774 EFX_LOG(efx, "Booted from internal ASIC settings;"
2775 " setting SPI config\n");
2776 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2777 /* 125 MHz / 7 ~= 20 MHz */
2778 FRF_AB_EE_SF_CLOCK_DIV, 7,
2779 /* 125 MHz / 63 ~= 2 MHz */
2780 FRF_AB_EE_EE_CLOCK_DIV, 63);
2781 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2782 }
2783
2784 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2785 falcon_spi_device_init(efx, &efx->spi_flash,
2786 FFE_AB_SPI_DEVICE_FLASH,
2787 default_flash_type);
2788 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2789 falcon_spi_device_init(efx, &efx->spi_eeprom,
2790 FFE_AB_SPI_DEVICE_EEPROM,
2791 large_eeprom_type);
2792 }
2793
2794 int falcon_probe_nic(struct efx_nic *efx)
2795 {
2796 struct falcon_nic_data *nic_data;
2797 struct falcon_board *board;
2798 int rc;
2799
2800 /* Allocate storage for hardware specific data */
2801 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2802 if (!nic_data)
2803 return -ENOMEM;
2804 efx->nic_data = nic_data;
2805
2806 /* Determine number of ports etc. */
2807 rc = falcon_probe_nic_variant(efx);
2808 if (rc)
2809 goto fail1;
2810
2811 /* Probe secondary function if expected */
2812 if (FALCON_IS_DUAL_FUNC(efx)) {
2813 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2814
2815 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2816 dev))) {
2817 if (dev->bus == efx->pci_dev->bus &&
2818 dev->devfn == efx->pci_dev->devfn + 1) {
2819 nic_data->pci_dev2 = dev;
2820 break;
2821 }
2822 }
2823 if (!nic_data->pci_dev2) {
2824 EFX_ERR(efx, "failed to find secondary function\n");
2825 rc = -ENODEV;
2826 goto fail2;
2827 }
2828 }
2829
2830 /* Now we can reset the NIC */
2831 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2832 if (rc) {
2833 EFX_ERR(efx, "failed to reset NIC\n");
2834 goto fail3;
2835 }
2836
2837 /* Allocate memory for INT_KER */
2838 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2839 if (rc)
2840 goto fail4;
2841 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2842
2843 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2844 (u64)efx->irq_status.dma_addr,
2845 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2846
2847 falcon_probe_spi_devices(efx);
2848
2849 /* Read in the non-volatile configuration */
2850 rc = falcon_probe_nvconfig(efx);
2851 if (rc)
2852 goto fail5;
2853
2854 /* Initialise I2C adapter */
2855 board = falcon_board(efx);
2856 board->i2c_adap.owner = THIS_MODULE;
2857 board->i2c_data = falcon_i2c_bit_operations;
2858 board->i2c_data.data = efx;
2859 board->i2c_adap.algo_data = &board->i2c_data;
2860 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2861 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2862 sizeof(board->i2c_adap.name));
2863 rc = i2c_bit_add_bus(&board->i2c_adap);
2864 if (rc)
2865 goto fail5;
2866
2867 rc = falcon_board(efx)->init(efx);
2868 if (rc) {
2869 EFX_ERR(efx, "failed to initialise board\n");
2870 goto fail6;
2871 }
2872
2873 return 0;
2874
2875 fail6:
2876 BUG_ON(i2c_del_adapter(&board->i2c_adap));
2877 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2878 fail5:
2879 falcon_remove_spi_devices(efx);
2880 falcon_free_buffer(efx, &efx->irq_status);
2881 fail4:
2882 fail3:
2883 if (nic_data->pci_dev2) {
2884 pci_dev_put(nic_data->pci_dev2);
2885 nic_data->pci_dev2 = NULL;
2886 }
2887 fail2:
2888 fail1:
2889 kfree(efx->nic_data);
2890 return rc;
2891 }
2892
2893 static void falcon_init_rx_cfg(struct efx_nic *efx)
2894 {
2895 /* Prior to Siena the RX DMA engine will split each frame at
2896 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2897 * be so large that that never happens. */
2898 const unsigned huge_buf_size = (3 * 4096) >> 5;
2899 /* RX control FIFO thresholds (32 entries) */
2900 const unsigned ctrl_xon_thr = 20;
2901 const unsigned ctrl_xoff_thr = 25;
2902 /* RX data FIFO thresholds (256-byte units; size varies) */
2903 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2904 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2905 efx_oword_t reg;
2906
2907 efx_reado(efx, &reg, FR_AZ_RX_CFG);
2908 if (falcon_rev(efx) <= FALCON_REV_A1) {
2909 /* Data FIFO size is 5.5K */
2910 if (data_xon_thr < 0)
2911 data_xon_thr = 512 >> 8;
2912 if (data_xoff_thr < 0)
2913 data_xoff_thr = 2048 >> 8;
2914 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2915 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2916 huge_buf_size);
2917 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2918 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2919 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2920 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2921 } else {
2922 /* Data FIFO size is 80K; register fields moved */
2923 if (data_xon_thr < 0)
2924 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2925 if (data_xoff_thr < 0)
2926 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2927 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2928 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2929 huge_buf_size);
2930 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2931 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2932 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2933 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2934 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2935 }
2936 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2937 }
2938
2939 /* This call performs hardware-specific global initialisation, such as
2940 * defining the descriptor cache sizes and number of RSS channels.
2941 * It does not set up any buffers, descriptor rings or event queues.
2942 */
2943 int falcon_init_nic(struct efx_nic *efx)
2944 {
2945 efx_oword_t temp;
2946 int rc;
2947
2948 /* Use on-chip SRAM */
2949 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2950 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2951 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2952
2953 /* Set the source of the GMAC clock */
2954 if (falcon_rev(efx) == FALCON_REV_B0) {
2955 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2956 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2957 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2958 }
2959
2960 rc = falcon_reset_sram(efx);
2961 if (rc)
2962 return rc;
2963
2964 /* Set positions of descriptor caches in SRAM. */
2965 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2966 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
2967 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2968 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
2969
2970 /* Set TX descriptor cache size. */
2971 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
2972 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2973 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
2974
2975 /* Set RX descriptor cache size. Set low watermark to size-8, as
2976 * this allows most efficient prefetching.
2977 */
2978 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
2979 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2980 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
2981 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2982 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
2983
2984 /* Clear the parity enables on the TX data fifos as
2985 * they produce false parity errors because of timing issues
2986 */
2987 if (EFX_WORKAROUND_5129(efx)) {
2988 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2989 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2990 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2991 }
2992
2993 /* Enable all the genuinely fatal interrupts. (They are still
2994 * masked by the overall interrupt mask, controlled by
2995 * falcon_interrupts()).
2996 *
2997 * Note: All other fatal interrupts are enabled
2998 */
2999 EFX_POPULATE_OWORD_3(temp,
3000 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3001 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3002 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3003 EFX_INVERT_OWORD(temp);
3004 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3005
3006 if (EFX_WORKAROUND_7244(efx)) {
3007 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3008 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3009 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3010 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3011 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3012 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3013 }
3014
3015 falcon_setup_rss_indir_table(efx);
3016
3017 /* XXX This is documented only for Falcon A0/A1 */
3018 /* Setup RX. Wait for descriptor is broken and must
3019 * be disabled. RXDP recovery shouldn't be needed, but is.
3020 */
3021 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3022 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3023 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3024 if (EFX_WORKAROUND_5583(efx))
3025 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3026 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3027
3028 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3029 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3030 */
3031 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3032 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3033 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3034 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3035 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3036 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3037 /* Enable SW_EV to inherit in char driver - assume harmless here */
3038 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3039 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3040 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3041 /* Squash TX of packets of 16 bytes or less */
3042 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3043 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3044 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3045
3046 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3047 * descriptors (which is bad).
3048 */
3049 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3050 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3051 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3052
3053 falcon_init_rx_cfg(efx);
3054
3055 /* Set destination of both TX and RX Flush events */
3056 if (falcon_rev(efx) >= FALCON_REV_B0) {
3057 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3058 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3059 }
3060
3061 return 0;
3062 }
3063
3064 void falcon_remove_nic(struct efx_nic *efx)
3065 {
3066 struct falcon_nic_data *nic_data = efx->nic_data;
3067 struct falcon_board *board = falcon_board(efx);
3068 int rc;
3069
3070 falcon_board(efx)->fini(efx);
3071
3072 /* Remove I2C adapter and clear it in preparation for a retry */
3073 rc = i2c_del_adapter(&board->i2c_adap);
3074 BUG_ON(rc);
3075 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
3076
3077 falcon_remove_spi_devices(efx);
3078 falcon_free_buffer(efx, &efx->irq_status);
3079
3080 falcon_reset_hw(efx, RESET_TYPE_ALL);
3081
3082 /* Release the second function after the reset */
3083 if (nic_data->pci_dev2) {
3084 pci_dev_put(nic_data->pci_dev2);
3085 nic_data->pci_dev2 = NULL;
3086 }
3087
3088 /* Tear down the private nic state */
3089 kfree(efx->nic_data);
3090 efx->nic_data = NULL;
3091 }
3092
3093 void falcon_update_nic_stats(struct efx_nic *efx)
3094 {
3095 efx_oword_t cnt;
3096
3097 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3098 efx->n_rx_nodesc_drop_cnt +=
3099 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3100 }
3101
3102 /**************************************************************************
3103 *
3104 * Revision-dependent attributes used by efx.c
3105 *
3106 **************************************************************************
3107 */
3108
3109 struct efx_nic_type falcon_a_nic_type = {
3110 .mem_map_size = 0x20000,
3111 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3112 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3113 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3114 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3115 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3116 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3117 .rx_buffer_padding = 0x24,
3118 .max_interrupt_mode = EFX_INT_MODE_MSI,
3119 .phys_addr_channels = 4,
3120 };
3121
3122 struct efx_nic_type falcon_b_nic_type = {
3123 /* Map everything up to and including the RSS indirection
3124 * table. Don't map MSI-X table, MSI-X PBA since Linux
3125 * requires that they not be mapped. */
3126 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3127 FR_BZ_RX_INDIRECTION_TBL_STEP *
3128 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3129 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3130 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3131 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3132 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3133 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3134 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3135 .rx_buffer_padding = 0,
3136 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3137 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3138 * interrupt handler only supports 32
3139 * channels */
3140 };
3141
Linux with added FPC-III support