arch/x86/include/asm/gart.h

   1 #ifndef _ASM_X86_GART_H
   2 #define _ASM_X86_GART_H
   3
   4 #include <asm/e820/api.h>
   5
   6 extern void set_up_gart_resume(u32, u32);
   7
   8 extern int fallback_aper_order;
   9 extern int fallback_aper_force;
  10 extern int fix_aperture;
  11
  12 /* PTE bits. */
  13 #define GPTE_VALID      1
  14 #define GPTE_COHERENT   2
  15
  16 /* Aperture control register bits. */
  17 #define GARTEN          (1<<0)
  18 #define DISGARTCPU      (1<<4)
  19 #define DISGARTIO       (1<<5)
  20 #define DISTLBWALKPRB   (1<<6)
  21
  22 /* GART cache control register bits. */
  23 #define INVGART         (1<<0)
  24 #define GARTPTEERR      (1<<1)
  25
  26 /* K8 On-cpu GART registers */
  27 #define AMD64_GARTAPERTURECTL   0x90
  28 #define AMD64_GARTAPERTUREBASE  0x94
  29 #define AMD64_GARTTABLEBASE     0x98
  30 #define AMD64_GARTCACHECTL      0x9c
  31
  32 #ifdef CONFIG_GART_IOMMU
  33 extern int gart_iommu_aperture;
  34 extern int gart_iommu_aperture_allowed;
  35 extern int gart_iommu_aperture_disabled;
  36
  37 extern void early_gart_iommu_check(void);
  38 extern int gart_iommu_init(void);
  39 extern void __init gart_parse_options(char *);
  40 extern int gart_iommu_hole_init(void);
  41
  42 #else
  43 #define gart_iommu_aperture            0
  44 #define gart_iommu_aperture_allowed    0
  45 #define gart_iommu_aperture_disabled   1
  46
  47 static inline void early_gart_iommu_check(void)
  48 {
  49 }
  50 static inline void gart_parse_options(char *options)
  51 {
  52 }
  53 static inline int gart_iommu_hole_init(void)
  54 {
  55         return -ENODEV;
  56 }
  57 #endif
  58
  59 extern int agp_amd64_init(void);
  60
  61 static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
  62 {
  63         u32 ctl;
  64
  65         /*
  66          * Don't enable translation but enable GART IO and CPU accesses.
  67          * Also, set DISTLBWALKPRB since GART tables memory is UC.
  68          */
  69         ctl = order << 1;
  70
  71         pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
  72 }
  73
  74 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
  75 {
  76         u32 tmp, ctl;
  77
  78         /* address of the mappings table */
  79         addr >>= 12;
  80         tmp = (u32) addr<<4;
  81         tmp &= ~0xf;
  82         pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
  83
  84         /* Enable GART translation for this hammer. */
  85         pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
  86         ctl |= GARTEN | DISTLBWALKPRB;
  87         ctl &= ~(DISGARTCPU | DISGARTIO);
  88         pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
  89 }
  90
  91 static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
  92 {
  93         if (!aper_base)
  94                 return 0;
  95
  96         if (aper_base + aper_size > 0x100000000ULL) {
  97                 printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
  98                 return 0;
  99         }
 100         if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) {
 101                 printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
 102                 return 0;
 103         }
 104         if (aper_size < min_size) {
 105                 printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
 106                                  aper_size>>20, min_size>>20);
 107                 return 0;
 108         }
 109
 110         return 1;
 111 }
 112
 113 #endif /* _ASM_X86_GART_H */