arch/x86/include/asm/intel_pmc_ipc.h

   1 #ifndef _ASM_X86_INTEL_PMC_IPC_H_
   2 #define  _ASM_X86_INTEL_PMC_IPC_H_
   3
   4 /* Commands */
   5 #define PMC_IPC_PMIC_ACCESS             0xFF
   6 #define         PMC_IPC_PMIC_ACCESS_READ        0x0
   7 #define         PMC_IPC_PMIC_ACCESS_WRITE       0x1
   8 #define PMC_IPC_USB_PWR_CTRL            0xF0
   9 #define PMC_IPC_PMIC_BLACKLIST_SEL      0xEF
  10 #define PMC_IPC_PHY_CONFIG              0xEE
  11 #define PMC_IPC_NORTHPEAK_CTRL          0xED
  12 #define PMC_IPC_PM_DEBUG                0xEC
  13 #define PMC_IPC_PMC_TELEMTRY            0xEB
  14 #define PMC_IPC_PMC_FW_MSG_CTRL         0xEA
  15
  16 /* IPC return code */
  17 #define IPC_ERR_NONE                    0
  18 #define IPC_ERR_CMD_NOT_SUPPORTED       1
  19 #define IPC_ERR_CMD_NOT_SERVICED        2
  20 #define IPC_ERR_UNABLE_TO_SERVICE       3
  21 #define IPC_ERR_CMD_INVALID             4
  22 #define IPC_ERR_CMD_FAILED              5
  23 #define IPC_ERR_EMSECURITY              6
  24 #define IPC_ERR_UNSIGNEDKERNEL          7
  25
  26 /* GCR reg offsets from gcr base*/
  27 #define PMC_GCR_PMC_CFG_REG             0x08
  28 #define PMC_GCR_TELEM_DEEP_S0IX_REG     0x78
  29 #define PMC_GCR_TELEM_SHLW_S0IX_REG     0x80
  30
  31 #if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
  32
  33 int intel_pmc_ipc_simple_command(int cmd, int sub);
  34 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
  35                 u32 *out, u32 outlen, u32 dptr, u32 sptr);
  36 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  37                 u32 *out, u32 outlen);
  38 int intel_pmc_s0ix_counter_read(u64 *data);
  39 int intel_pmc_gcr_read(u32 offset, u32 *data);
  40 int intel_pmc_gcr_write(u32 offset, u32 data);
  41 int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val);
  42
  43 #else
  44
  45 static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
  46 {
  47         return -EINVAL;
  48 }
  49
  50 static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
  51                 u32 *out, u32 outlen, u32 dptr, u32 sptr)
  52 {
  53         return -EINVAL;
  54 }
  55
  56 static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  57                 u32 *out, u32 outlen)
  58 {
  59         return -EINVAL;
  60 }
  61
  62 static inline int intel_pmc_s0ix_counter_read(u64 *data)
  63 {
  64         return -EINVAL;
  65 }
  66
  67 static inline int intel_pmc_gcr_read(u32 offset, u32 *data)
  68 {
  69         return -EINVAL;
  70 }
  71
  72 static inline int intel_pmc_gcr_write(u32 offset, u32 data)
  73 {
  74         return -EINVAL;
  75 }
  76
  77 static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
  78 {
  79         return -EINVAL;
  80 }
  81
  82 #endif /*CONFIG_INTEL_PMC_IPC*/
  83
  84 #endif