arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9 struct vm86;
  10
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <uapi/asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeatures.h>
  17 #include <asm/page.h>
  18 #include <asm/pgtable_types.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23 #include <asm/special_insns.h>
  24 #include <asm/fpu/types.h>
  25
  26 #include <linux/personality.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/err.h>
  31 #include <linux/irqflags.h>
  32
  33 /*
  34  * We handle most unaligned accesses in hardware.  On the other hand
  35  * unaligned DMA can be quite expensive on some Nehalem processors.
  36  *
  37  * Based on this we disable the IP header alignment in network drivers.
  38  */
  39 #define NET_IP_ALIGN    0
  40
  41 #define HBP_NUM 4
  42 /*
  43  * Default implementation of macro that returns current
  44  * instruction pointer ("program counter").
  45  */
  46 static inline void *current_text_addr(void)
  47 {
  48         void *pc;
  49
  50         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  51
  52         return pc;
  53 }
  54
  55 /*
  56  * These alignment constraints are for performance in the vSMP case,
  57  * but in the task_struct case we must also meet hardware imposed
  58  * alignment requirements of the FPU state:
  59  */
  60 #ifdef CONFIG_X86_VSMP
  61 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  62 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  63 #else
  64 # define ARCH_MIN_TASKALIGN             __alignof__(union fpregs_state)
  65 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  66 #endif
  67
  68 enum tlb_infos {
  69         ENTRIES,
  70         NR_INFO
  71 };
  72
  73 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  74 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  75 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  76 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  77 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  78 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  79 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  80
  81 /*
  82  *  CPU type and hardware bug flags. Kept separately for each CPU.
  83  *  Members of this structure are referenced in head_32.S, so think twice
  84  *  before touching them. [mj]
  85  */
  86
  87 struct cpuinfo_x86 {
  88         __u8                    x86;            /* CPU family */
  89         __u8                    x86_vendor;     /* CPU vendor */
  90         __u8                    x86_model;
  91         __u8                    x86_mask;
  92 #ifdef CONFIG_X86_64
  93         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  94         int                     x86_tlbsize;
  95 #endif
  96         __u8                    x86_virt_bits;
  97         __u8                    x86_phys_bits;
  98         /* CPUID returned core id bits: */
  99         __u8                    x86_coreid_bits;
 100         __u8                    cu_id;
 101         /* Max extended CPUID function supported: */
 102         __u32                   extended_cpuid_level;
 103         /* Maximum supported CPUID level, -1=no CPUID: */
 104         int                     cpuid_level;
 105         __u32                   x86_capability[NCAPINTS + NBUGINTS];
 106         char                    x86_vendor_id[16];
 107         char                    x86_model_id[64];
 108         /* in KB - valid for CPUS which support this call: */
 109         int                     x86_cache_size;
 110         int                     x86_cache_alignment;    /* In bytes */
 111         /* Cache QoS architectural values: */
 112         int                     x86_cache_max_rmid;     /* max index */
 113         int                     x86_cache_occ_scale;    /* scale to bytes */
 114         int                     x86_power;
 115         unsigned long           loops_per_jiffy;
 116         /* cpuid returned max cores value: */
 117         u16                      x86_max_cores;
 118         u16                     apicid;
 119         u16                     initial_apicid;
 120         u16                     x86_clflush_size;
 121         /* number of cores as seen by the OS: */
 122         u16                     booted_cores;
 123         /* Physical processor id: */
 124         u16                     phys_proc_id;
 125         /* Logical processor id: */
 126         u16                     logical_proc_id;
 127         /* Core id: */
 128         u16                     cpu_core_id;
 129         /* Index into per_cpu list: */
 130         u16                     cpu_index;
 131         u32                     microcode;
 132 } __randomize_layout;
 133
 134 struct cpuid_regs {
 135         u32 eax, ebx, ecx, edx;
 136 };
 137
 138 enum cpuid_regs_idx {
 139         CPUID_EAX = 0,
 140         CPUID_EBX,
 141         CPUID_ECX,
 142         CPUID_EDX,
 143 };
 144
 145 #define X86_VENDOR_INTEL        0
 146 #define X86_VENDOR_CYRIX        1
 147 #define X86_VENDOR_AMD          2
 148 #define X86_VENDOR_UMC          3
 149 #define X86_VENDOR_CENTAUR      5
 150 #define X86_VENDOR_TRANSMETA    7
 151 #define X86_VENDOR_NSC          8
 152 #define X86_VENDOR_NUM          9
 153
 154 #define X86_VENDOR_UNKNOWN      0xff
 155
 156 /*
 157  * capabilities of CPUs
 158  */
 159 extern struct cpuinfo_x86       boot_cpu_data;
 160 extern struct cpuinfo_x86       new_cpu_data;
 161
 162 extern struct tss_struct        doublefault_tss;
 163 extern __u32                    cpu_caps_cleared[NCAPINTS];
 164 extern __u32                    cpu_caps_set[NCAPINTS];
 165
 166 #ifdef CONFIG_SMP
 167 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 168 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 169 #else
 170 #define cpu_info                boot_cpu_data
 171 #define cpu_data(cpu)           boot_cpu_data
 172 #endif
 173
 174 extern const struct seq_operations cpuinfo_op;
 175
 176 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 177
 178 extern void cpu_detect(struct cpuinfo_x86 *c);
 179
 180 extern void early_cpu_init(void);
 181 extern void identify_boot_cpu(void);
 182 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 183 extern void print_cpu_info(struct cpuinfo_x86 *);
 184 void print_cpu_msr(struct cpuinfo_x86 *);
 185 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 186 extern u32 get_scattered_cpuid_leaf(unsigned int level,
 187                                     unsigned int sub_leaf,
 188                                     enum cpuid_regs_idx reg);
 189 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 190 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 191
 192 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 193 extern void detect_ht(struct cpuinfo_x86 *c);
 194
 195 #ifdef CONFIG_X86_32
 196 extern int have_cpuid_p(void);
 197 #else
 198 static inline int have_cpuid_p(void)
 199 {
 200         return 1;
 201 }
 202 #endif
 203 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 204                                 unsigned int *ecx, unsigned int *edx)
 205 {
 206         /* ecx is often an input as well as an output. */
 207         asm volatile("cpuid"
 208             : "=a" (*eax),
 209               "=b" (*ebx),
 210               "=c" (*ecx),
 211               "=d" (*edx)
 212             : "0" (*eax), "2" (*ecx)
 213             : "memory");
 214 }
 215
 216 #define native_cpuid_reg(reg)                                   \
 217 static inline unsigned int native_cpuid_##reg(unsigned int op)  \
 218 {                                                               \
 219         unsigned int eax = op, ebx, ecx = 0, edx;               \
 220                                                                 \
 221         native_cpuid(&eax, &ebx, &ecx, &edx);                   \
 222                                                                 \
 223         return reg;                                             \
 224 }
 225
 226 /*
 227  * Native CPUID functions returning a single datum.
 228  */
 229 native_cpuid_reg(eax)
 230 native_cpuid_reg(ebx)
 231 native_cpuid_reg(ecx)
 232 native_cpuid_reg(edx)
 233
 234 /*
 235  * Friendlier CR3 helpers.
 236  */
 237 static inline unsigned long read_cr3_pa(void)
 238 {
 239         return __read_cr3() & CR3_ADDR_MASK;
 240 }
 241
 242 static inline void load_cr3(pgd_t *pgdir)
 243 {
 244         write_cr3(__pa(pgdir));
 245 }
 246
 247 #ifdef CONFIG_X86_32
 248 /* This is the TSS defined by the hardware. */
 249 struct x86_hw_tss {
 250         unsigned short          back_link, __blh;
 251         unsigned long           sp0;
 252         unsigned short          ss0, __ss0h;
 253         unsigned long           sp1;
 254
 255         /*
 256          * We don't use ring 1, so ss1 is a convenient scratch space in
 257          * the same cacheline as sp0.  We use ss1 to cache the value in
 258          * MSR_IA32_SYSENTER_CS.  When we context switch
 259          * MSR_IA32_SYSENTER_CS, we first check if the new value being
 260          * written matches ss1, and, if it's not, then we wrmsr the new
 261          * value and update ss1.
 262          *
 263          * The only reason we context switch MSR_IA32_SYSENTER_CS is
 264          * that we set it to zero in vm86 tasks to avoid corrupting the
 265          * stack if we were to go through the sysenter path from vm86
 266          * mode.
 267          */
 268         unsigned short          ss1;    /* MSR_IA32_SYSENTER_CS */
 269
 270         unsigned short          __ss1h;
 271         unsigned long           sp2;
 272         unsigned short          ss2, __ss2h;
 273         unsigned long           __cr3;
 274         unsigned long           ip;
 275         unsigned long           flags;
 276         unsigned long           ax;
 277         unsigned long           cx;
 278         unsigned long           dx;
 279         unsigned long           bx;
 280         unsigned long           sp;
 281         unsigned long           bp;
 282         unsigned long           si;
 283         unsigned long           di;
 284         unsigned short          es, __esh;
 285         unsigned short          cs, __csh;
 286         unsigned short          ss, __ssh;
 287         unsigned short          ds, __dsh;
 288         unsigned short          fs, __fsh;
 289         unsigned short          gs, __gsh;
 290         unsigned short          ldt, __ldth;
 291         unsigned short          trace;
 292         unsigned short          io_bitmap_base;
 293
 294 } __attribute__((packed));
 295 #else
 296 struct x86_hw_tss {
 297         u32                     reserved1;
 298         u64                     sp0;
 299         u64                     sp1;
 300         u64                     sp2;
 301         u64                     reserved2;
 302         u64                     ist[7];
 303         u32                     reserved3;
 304         u32                     reserved4;
 305         u16                     reserved5;
 306         u16                     io_bitmap_base;
 307
 308 } __attribute__((packed));
 309 #endif
 310
 311 /*
 312  * IO-bitmap sizes:
 313  */
 314 #define IO_BITMAP_BITS                  65536
 315 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 316 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 317 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 318 #define INVALID_IO_BITMAP_OFFSET        0x8000
 319
 320 struct tss_struct {
 321         /*
 322          * The hardware state:
 323          */
 324         struct x86_hw_tss       x86_tss;
 325
 326         /*
 327          * The extra 1 is there because the CPU will access an
 328          * additional byte beyond the end of the IO permission
 329          * bitmap. The extra byte must be all 1 bits, and must
 330          * be within the limit.
 331          */
 332         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 333
 334 #ifdef CONFIG_X86_32
 335         /*
 336          * Space for the temporary SYSENTER stack.
 337          */
 338         unsigned long           SYSENTER_stack_canary;
 339         unsigned long           SYSENTER_stack[64];
 340 #endif
 341
 342 } ____cacheline_aligned;
 343
 344 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
 345
 346 /*
 347  * sizeof(unsigned long) coming from an extra "long" at the end
 348  * of the iobitmap.
 349  *
 350  * -1? seg base+limit should be pointing to the address of the
 351  * last valid byte
 352  */
 353 #define __KERNEL_TSS_LIMIT      \
 354         (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
 355
 356 #ifdef CONFIG_X86_32
 357 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
 358 #endif
 359
 360 /*
 361  * Save the original ist values for checking stack pointers during debugging
 362  */
 363 struct orig_ist {
 364         unsigned long           ist[7];
 365 };
 366
 367 #ifdef CONFIG_X86_64
 368 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 369
 370 union irq_stack_union {
 371         char irq_stack[IRQ_STACK_SIZE];
 372         /*
 373          * GCC hardcodes the stack canary as %gs:40.  Since the
 374          * irq_stack is the object at %gs:0, we reserve the bottom
 375          * 48 bytes of the irq stack for the canary.
 376          */
 377         struct {
 378                 char gs_base[40];
 379                 unsigned long stack_canary;
 380         };
 381 };
 382
 383 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
 384 DECLARE_INIT_PER_CPU(irq_stack_union);
 385
 386 DECLARE_PER_CPU(char *, irq_stack_ptr);
 387 DECLARE_PER_CPU(unsigned int, irq_count);
 388 extern asmlinkage void ignore_sysret(void);
 389 #else   /* X86_64 */
 390 #ifdef CONFIG_CC_STACKPROTECTOR
 391 /*
 392  * Make sure stack canary segment base is cached-aligned:
 393  *   "For Intel Atom processors, avoid non zero segment base address
 394  *    that is not aligned to cache line boundary at all cost."
 395  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 396  */
 397 struct stack_canary {
 398         char __pad[20];         /* canary at %gs:20 */
 399         unsigned long canary;
 400 };
 401 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 402 #endif
 403 /*
 404  * per-CPU IRQ handling stacks
 405  */
 406 struct irq_stack {
 407         u32                     stack[THREAD_SIZE/sizeof(u32)];
 408 } __aligned(THREAD_SIZE);
 409
 410 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
 411 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
 412 #endif  /* X86_64 */
 413
 414 extern unsigned int fpu_kernel_xstate_size;
 415 extern unsigned int fpu_user_xstate_size;
 416
 417 struct perf_event;
 418
 419 typedef struct {
 420         unsigned long           seg;
 421 } mm_segment_t;
 422
 423 struct thread_struct {
 424         /* Cached TLS descriptors: */
 425         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 426         unsigned long           sp0;
 427         unsigned long           sp;
 428 #ifdef CONFIG_X86_32
 429         unsigned long           sysenter_cs;
 430 #else
 431         unsigned short          es;
 432         unsigned short          ds;
 433         unsigned short          fsindex;
 434         unsigned short          gsindex;
 435 #endif
 436
 437         u32                     status;         /* thread synchronous flags */
 438
 439 #ifdef CONFIG_X86_64
 440         unsigned long           fsbase;
 441         unsigned long           gsbase;
 442 #else
 443         /*
 444          * XXX: this could presumably be unsigned short.  Alternatively,
 445          * 32-bit kernels could be taught to use fsindex instead.
 446          */
 447         unsigned long fs;
 448         unsigned long gs;
 449 #endif
 450
 451         /* Save middle states of ptrace breakpoints */
 452         struct perf_event       *ptrace_bps[HBP_NUM];
 453         /* Debug status used for traps, single steps, etc... */
 454         unsigned long           debugreg6;
 455         /* Keep track of the exact dr7 value set by the user */
 456         unsigned long           ptrace_dr7;
 457         /* Fault info: */
 458         unsigned long           cr2;
 459         unsigned long           trap_nr;
 460         unsigned long           error_code;
 461 #ifdef CONFIG_VM86
 462         /* Virtual 86 mode info */
 463         struct vm86             *vm86;
 464 #endif
 465         /* IO permissions: */
 466         unsigned long           *io_bitmap_ptr;
 467         unsigned long           iopl;
 468         /* Max allowed port in the bitmap, in bytes: */
 469         unsigned                io_bitmap_max;
 470
 471         mm_segment_t            addr_limit;
 472
 473         unsigned int            sig_on_uaccess_err:1;
 474         unsigned int            uaccess_err:1;  /* uaccess failed */
 475
 476         /* Floating point and extended processor state */
 477         struct fpu              fpu;
 478         /*
 479          * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
 480          * the end.
 481          */
 482 };
 483
 484 /*
 485  * Thread-synchronous status.
 486  *
 487  * This is different from the flags in that nobody else
 488  * ever touches our thread-synchronous status, so we don't
 489  * have to worry about atomic accesses.
 490  */
 491 #define TS_COMPAT               0x0002  /* 32bit syscall active (64BIT)*/
 492
 493 /*
 494  * Set IOPL bits in EFLAGS from given mask
 495  */
 496 static inline void native_set_iopl_mask(unsigned mask)
 497 {
 498 #ifdef CONFIG_X86_32
 499         unsigned int reg;
 500
 501         asm volatile ("pushfl;"
 502                       "popl %0;"
 503                       "andl %1, %0;"
 504                       "orl %2, %0;"
 505                       "pushl %0;"
 506                       "popfl"
 507                       : "=&r" (reg)
 508                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 509 #endif
 510 }
 511
 512 static inline void
 513 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 514 {
 515         tss->x86_tss.sp0 = thread->sp0;
 516 #ifdef CONFIG_X86_32
 517         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 518         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 519                 tss->x86_tss.ss1 = thread->sysenter_cs;
 520                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 521         }
 522 #endif
 523 }
 524
 525 static inline void native_swapgs(void)
 526 {
 527 #ifdef CONFIG_X86_64
 528         asm volatile("swapgs" ::: "memory");
 529 #endif
 530 }
 531
 532 static inline unsigned long current_top_of_stack(void)
 533 {
 534 #ifdef CONFIG_X86_64
 535         return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
 536 #else
 537         /* sp0 on x86_32 is special in and around vm86 mode. */
 538         return this_cpu_read_stable(cpu_current_top_of_stack);
 539 #endif
 540 }
 541
 542 #ifdef CONFIG_PARAVIRT
 543 #include <asm/paravirt.h>
 544 #else
 545 #define __cpuid                 native_cpuid
 546
 547 static inline void load_sp0(struct tss_struct *tss,
 548                             struct thread_struct *thread)
 549 {
 550         native_load_sp0(tss, thread);
 551 }
 552
 553 #define set_iopl_mask native_set_iopl_mask
 554 #endif /* CONFIG_PARAVIRT */
 555
 556 /* Free all resources held by a thread. */
 557 extern void release_thread(struct task_struct *);
 558
 559 unsigned long get_wchan(struct task_struct *p);
 560
 561 /*
 562  * Generic CPUID function
 563  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 564  * resulting in stale register contents being returned.
 565  */
 566 static inline void cpuid(unsigned int op,
 567                          unsigned int *eax, unsigned int *ebx,
 568                          unsigned int *ecx, unsigned int *edx)
 569 {
 570         *eax = op;
 571         *ecx = 0;
 572         __cpuid(eax, ebx, ecx, edx);
 573 }
 574
 575 /* Some CPUID calls want 'count' to be placed in ecx */
 576 static inline void cpuid_count(unsigned int op, int count,
 577                                unsigned int *eax, unsigned int *ebx,
 578                                unsigned int *ecx, unsigned int *edx)
 579 {
 580         *eax = op;
 581         *ecx = count;
 582         __cpuid(eax, ebx, ecx, edx);
 583 }
 584
 585 /*
 586  * CPUID functions returning a single datum
 587  */
 588 static inline unsigned int cpuid_eax(unsigned int op)
 589 {
 590         unsigned int eax, ebx, ecx, edx;
 591
 592         cpuid(op, &eax, &ebx, &ecx, &edx);
 593
 594         return eax;
 595 }
 596
 597 static inline unsigned int cpuid_ebx(unsigned int op)
 598 {
 599         unsigned int eax, ebx, ecx, edx;
 600
 601         cpuid(op, &eax, &ebx, &ecx, &edx);
 602
 603         return ebx;
 604 }
 605
 606 static inline unsigned int cpuid_ecx(unsigned int op)
 607 {
 608         unsigned int eax, ebx, ecx, edx;
 609
 610         cpuid(op, &eax, &ebx, &ecx, &edx);
 611
 612         return ecx;
 613 }
 614
 615 static inline unsigned int cpuid_edx(unsigned int op)
 616 {
 617         unsigned int eax, ebx, ecx, edx;
 618
 619         cpuid(op, &eax, &ebx, &ecx, &edx);
 620
 621         return edx;
 622 }
 623
 624 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 625 static __always_inline void rep_nop(void)
 626 {
 627         asm volatile("rep; nop" ::: "memory");
 628 }
 629
 630 static __always_inline void cpu_relax(void)
 631 {
 632         rep_nop();
 633 }
 634
 635 /*
 636  * This function forces the icache and prefetched instruction stream to
 637  * catch up with reality in two very specific cases:
 638  *
 639  *  a) Text was modified using one virtual address and is about to be executed
 640  *     from the same physical page at a different virtual address.
 641  *
 642  *  b) Text was modified on a different CPU, may subsequently be
 643  *     executed on this CPU, and you want to make sure the new version
 644  *     gets executed.  This generally means you're calling this in a IPI.
 645  *
 646  * If you're calling this for a different reason, you're probably doing
 647  * it wrong.
 648  */
 649 static inline void sync_core(void)
 650 {
 651         /*
 652          * There are quite a few ways to do this.  IRET-to-self is nice
 653          * because it works on every CPU, at any CPL (so it's compatible
 654          * with paravirtualization), and it never exits to a hypervisor.
 655          * The only down sides are that it's a bit slow (it seems to be
 656          * a bit more than 2x slower than the fastest options) and that
 657          * it unmasks NMIs.  The "push %cs" is needed because, in
 658          * paravirtual environments, __KERNEL_CS may not be a valid CS
 659          * value when we do IRET directly.
 660          *
 661          * In case NMI unmasking or performance ever becomes a problem,
 662          * the next best option appears to be MOV-to-CR2 and an
 663          * unconditional jump.  That sequence also works on all CPUs,
 664          * but it will fault at CPL3 (i.e. Xen PV and lguest).
 665          *
 666          * CPUID is the conventional way, but it's nasty: it doesn't
 667          * exist on some 486-like CPUs, and it usually exits to a
 668          * hypervisor.
 669          *
 670          * Like all of Linux's memory ordering operations, this is a
 671          * compiler barrier as well.
 672          */
 673         register void *__sp asm(_ASM_SP);
 674
 675 #ifdef CONFIG_X86_32
 676         asm volatile (
 677                 "pushfl\n\t"
 678                 "pushl %%cs\n\t"
 679                 "pushl $1f\n\t"
 680                 "iret\n\t"
 681                 "1:"
 682                 : "+r" (__sp) : : "memory");
 683 #else
 684         unsigned int tmp;
 685
 686         asm volatile (
 687                 "mov %%ss, %0\n\t"
 688                 "pushq %q0\n\t"
 689                 "pushq %%rsp\n\t"
 690                 "addq $8, (%%rsp)\n\t"
 691                 "pushfq\n\t"
 692                 "mov %%cs, %0\n\t"
 693                 "pushq %q0\n\t"
 694                 "pushq $1f\n\t"
 695                 "iretq\n\t"
 696                 "1:"
 697                 : "=&r" (tmp), "+r" (__sp) : : "cc", "memory");
 698 #endif
 699 }
 700
 701 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 702 extern void amd_e400_c1e_apic_setup(void);
 703
 704 extern unsigned long            boot_option_idle_override;
 705
 706 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 707                          IDLE_POLL};
 708
 709 extern void enable_sep_cpu(void);
 710 extern int sysenter_setup(void);
 711
 712 extern void early_trap_init(void);
 713 void early_trap_pf_init(void);
 714
 715 /* Defined in head.S */
 716 extern struct desc_ptr          early_gdt_descr;
 717
 718 extern void cpu_set_gdt(int);
 719 extern void switch_to_new_gdt(int);
 720 extern void load_direct_gdt(int);
 721 extern void load_fixmap_gdt(int);
 722 extern void load_percpu_segment(int);
 723 extern void cpu_init(void);
 724
 725 static inline unsigned long get_debugctlmsr(void)
 726 {
 727         unsigned long debugctlmsr = 0;
 728
 729 #ifndef CONFIG_X86_DEBUGCTLMSR
 730         if (boot_cpu_data.x86 < 6)
 731                 return 0;
 732 #endif
 733         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 734
 735         return debugctlmsr;
 736 }
 737
 738 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 739 {
 740 #ifndef CONFIG_X86_DEBUGCTLMSR
 741         if (boot_cpu_data.x86 < 6)
 742                 return;
 743 #endif
 744         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 745 }
 746
 747 extern void set_task_blockstep(struct task_struct *task, bool on);
 748
 749 /* Boot loader type from the setup header: */
 750 extern int                      bootloader_type;
 751 extern int                      bootloader_version;
 752
 753 extern char                     ignore_fpu_irq;
 754
 755 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 756 #define ARCH_HAS_PREFETCHW
 757 #define ARCH_HAS_SPINLOCK_PREFETCH
 758
 759 #ifdef CONFIG_X86_32
 760 # define BASE_PREFETCH          ""
 761 # define ARCH_HAS_PREFETCH
 762 #else
 763 # define BASE_PREFETCH          "prefetcht0 %P1"
 764 #endif
 765
 766 /*
 767  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 768  *
 769  * It's not worth to care about 3dnow prefetches for the K6
 770  * because they are microcoded there and very slow.
 771  */
 772 static inline void prefetch(const void *x)
 773 {
 774         alternative_input(BASE_PREFETCH, "prefetchnta %P1",
 775                           X86_FEATURE_XMM,
 776                           "m" (*(const char *)x));
 777 }
 778
 779 /*
 780  * 3dnow prefetch to get an exclusive cache line.
 781  * Useful for spinlocks to avoid one state transition in the
 782  * cache coherency protocol:
 783  */
 784 static inline void prefetchw(const void *x)
 785 {
 786         alternative_input(BASE_PREFETCH, "prefetchw %P1",
 787                           X86_FEATURE_3DNOWPREFETCH,
 788                           "m" (*(const char *)x));
 789 }
 790
 791 static inline void spin_lock_prefetch(const void *x)
 792 {
 793         prefetchw(x);
 794 }
 795
 796 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
 797                            TOP_OF_KERNEL_STACK_PADDING)
 798
 799 #ifdef CONFIG_X86_32
 800 /*
 801  * User space process size: 3GB (default).
 802  */
 803 #define IA32_PAGE_OFFSET        PAGE_OFFSET
 804 #define TASK_SIZE               PAGE_OFFSET
 805 #define TASK_SIZE_MAX           TASK_SIZE
 806 #define STACK_TOP               TASK_SIZE
 807 #define STACK_TOP_MAX           STACK_TOP
 808
 809 #define INIT_THREAD  {                                                    \
 810         .sp0                    = TOP_OF_INIT_STACK,                      \
 811         .sysenter_cs            = __KERNEL_CS,                            \
 812         .io_bitmap_ptr          = NULL,                                   \
 813         .addr_limit             = KERNEL_DS,                              \
 814 }
 815
 816 /*
 817  * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
 818  * This is necessary to guarantee that the entire "struct pt_regs"
 819  * is accessible even if the CPU haven't stored the SS/ESP registers
 820  * on the stack (interrupt gate does not save these registers
 821  * when switching to the same priv ring).
 822  * Therefore beware: accessing the ss/esp fields of the
 823  * "struct pt_regs" is possible, but they may contain the
 824  * completely wrong values.
 825  */
 826 #define task_pt_regs(task) \
 827 ({                                                                      \
 828         unsigned long __ptr = (unsigned long)task_stack_page(task);     \
 829         __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;             \
 830         ((struct pt_regs *)__ptr) - 1;                                  \
 831 })
 832
 833 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 834
 835 #else
 836 /*
 837  * User space process size. 47bits minus one guard page.  The guard
 838  * page is necessary on Intel CPUs: if a SYSCALL instruction is at
 839  * the highest possible canonical userspace address, then that
 840  * syscall will enter the kernel with a non-canonical return
 841  * address, and SYSRET will explode dangerously.  We avoid this
 842  * particular problem by preventing anything from being mapped
 843  * at the maximum canonical address.
 844  */
 845 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 846
 847 /* This decides where the kernel will search for a free chunk of vm
 848  * space during mmap's.
 849  */
 850 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 851                                         0xc0000000 : 0xFFFFe000)
 852
 853 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
 854                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 855 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
 856                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 857
 858 #define STACK_TOP               TASK_SIZE
 859 #define STACK_TOP_MAX           TASK_SIZE_MAX
 860
 861 #define INIT_THREAD  {                                          \
 862         .sp0                    = TOP_OF_INIT_STACK,            \
 863         .addr_limit             = KERNEL_DS,                    \
 864 }
 865
 866 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 867 extern unsigned long KSTK_ESP(struct task_struct *task);
 868
 869 #endif /* CONFIG_X86_64 */
 870
 871 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 872                                                unsigned long new_sp);
 873
 874 /*
 875  * This decides where the kernel will search for a free chunk of vm
 876  * space during mmap's.
 877  */
 878 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
 879 #define TASK_UNMAPPED_BASE              __TASK_UNMAPPED_BASE(TASK_SIZE)
 880
 881 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 882
 883 /* Get/set a process' ability to use the timestamp counter instruction */
 884 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 885 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 886
 887 extern int get_tsc_mode(unsigned long adr);
 888 extern int set_tsc_mode(unsigned int val);
 889
 890 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
 891
 892 /* Register/unregister a process' MPX related resource */
 893 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
 894 #define MPX_DISABLE_MANAGEMENT()        mpx_disable_management()
 895
 896 #ifdef CONFIG_X86_INTEL_MPX
 897 extern int mpx_enable_management(void);
 898 extern int mpx_disable_management(void);
 899 #else
 900 static inline int mpx_enable_management(void)
 901 {
 902         return -EINVAL;
 903 }
 904 static inline int mpx_disable_management(void)
 905 {
 906         return -EINVAL;
 907 }
 908 #endif /* CONFIG_X86_INTEL_MPX */
 909
 910 #ifdef CONFIG_CPU_SUP_AMD
 911 extern u16 amd_get_nb_id(int cpu);
 912 extern u32 amd_get_nodes_per_socket(void);
 913 #else
 914 static inline u16 amd_get_nb_id(int cpu)                { return 0; }
 915 static inline u32 amd_get_nodes_per_socket(void)        { return 0; }
 916 #endif
 917
 918 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 919 {
 920         uint32_t base, eax, signature[3];
 921
 922         for (base = 0x40000000; base < 0x40010000; base += 0x100) {
 923                 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 924
 925                 if (!memcmp(sig, signature, 12) &&
 926                     (leaves == 0 || ((eax - base) >= leaves)))
 927                         return base;
 928         }
 929
 930         return 0;
 931 }
 932
 933 extern unsigned long arch_align_stack(unsigned long sp);
 934 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 935
 936 void default_idle(void);
 937 #ifdef  CONFIG_XEN
 938 bool xen_set_default_idle(void);
 939 #else
 940 #define xen_set_default_idle 0
 941 #endif
 942
 943 void stop_this_cpu(void *dummy);
 944 void df_debug(struct pt_regs *regs, long error_code);
 945 #endif /* _ASM_X86_PROCESSOR_H */