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Merge tag 'pm-4.13-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[linux/fpc-iii.git] / arch / x86 / include / asm / uv / uv_bau.h
blob7cac79802ad2d7067522cfa4f483fd5210a6af36
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
16
17 /*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use one set for sending BAU messages from each of the
30 * cpu's on the uvhub.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36 #define MAX_CPUS_PER_UVHUB 128
37 #define MAX_CPUS_PER_SOCKET 64
38 #define ADP_SZ 64 /* hardware-provided max. */
39 #define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40 #define ITEMS_PER_DESC 8
41 /* the 'throttle' to prevent the hardware stay-busy bug */
42 #define MAX_BAU_CONCURRENT 3
43 #define UV_ACT_STATUS_MASK 0x3
44 #define UV_ACT_STATUS_SIZE 2
45 #define UV_DISTRIBUTION_SIZE 256
46 #define UV_SW_ACK_NPENDING 8
47 #define UV1_NET_ENDPOINT_INTD 0x38
48 #define UV2_NET_ENDPOINT_INTD 0x28
49 #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_DESC_PSHIFT 49
52 #define UV_PAYLOADQ_GNODE_SHIFT 49
53 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54 #define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55 #define UV_BAU_TUNABLES_DIR "sgi_uv"
56 #define UV_BAU_TUNABLES_FILE "bau_tunables"
57 #define WHITESPACE " \t\n"
58 #define cpubit_isset(cpu, bau_local_cpumask) \
59 test_bit((cpu), (bau_local_cpumask).bits)
60
61 /* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
62 /*
63 * UV2: Bit 19 selects between
64 * (0): 10 microsecond timebase and
65 * (1): 80 microseconds
66 * we're using 560us, similar to UV1: 65 units of 10us
67 */
68 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
69 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
70
71 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
72 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
73 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
74 /* assuming UV3 is the same */
75
76 #define BAU_MISC_CONTROL_MULT_MASK 3
77
78 #define UVH_AGING_PRESCALE_SEL 0x000000b000UL
79 /* [30:28] URGENCY_7 an index into a table of times */
80 #define BAU_URGENCY_7_SHIFT 28
81 #define BAU_URGENCY_7_MASK 7
82
83 #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
84 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
85 #define BAU_TRANS_SHIFT 40
86 #define BAU_TRANS_MASK 0x3f
87
88 /*
89 * shorten some awkward names
90 */
91 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
92 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
93 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
94 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
95 #define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
96 #define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
97 #define write_gmmr uv_write_global_mmr64
98 #define write_lmmr uv_write_local_mmr
99 #define read_lmmr uv_read_local_mmr
100 #define read_gmmr uv_read_global_mmr64
101
102 /*
103 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
104 */
105 #define DS_IDLE 0
106 #define DS_ACTIVE 1
107 #define DS_DESTINATION_TIMEOUT 2
108 #define DS_SOURCE_TIMEOUT 3
109 /*
110 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
111 * values 1 and 3 will not occur
112 * Decoded meaning ERROR BUSY AUX ERR
113 * ------------------------------- ---- ----- -------
114 * IDLE 0 0 0
115 * BUSY (active) 0 1 0
116 * SW Ack Timeout (destination) 1 0 0
117 * SW Ack INTD rejected (strong NACK) 1 0 1
118 * Source Side Time Out Detected 1 1 0
119 * Destination Side PUT Failed 1 1 1
120 */
121 #define UV2H_DESC_IDLE 0
122 #define UV2H_DESC_BUSY 2
123 #define UV2H_DESC_DEST_TIMEOUT 4
124 #define UV2H_DESC_DEST_STRONG_NACK 5
125 #define UV2H_DESC_SOURCE_TIMEOUT 6
126 #define UV2H_DESC_DEST_PUT_ERR 7
127
128 /*
129 * delay for 'plugged' timeout retries, in microseconds
130 */
131 #define PLUGGED_DELAY 10
132
133 /*
134 * threshholds at which to use IPI to free resources
135 */
136 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
137 #define PLUGSB4RESET 100
138 /* after this many consecutive timeouts, use IPI to release resources */
139 #define TIMEOUTSB4RESET 1
140 /* at this number uses of IPI to release resources, giveup the request */
141 #define IPI_RESET_LIMIT 1
142 /* after this # consecutive successes, bump up the throttle if it was lowered */
143 #define COMPLETE_THRESHOLD 5
144 /* after this # of giveups (fall back to kernel IPI's) disable the use of
145 the BAU for a period of time */
146 #define GIVEUP_LIMIT 100
147
148 #define UV_LB_SUBNODEID 0x10
149
150 /* these two are the same for UV1 and UV2: */
151 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
152 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
153 /* 4 bits of software ack period */
154 #define UV2_ACK_MASK 0x7UL
155 #define UV2_ACK_UNITS_SHFT 3
156 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
157
158 /*
159 * number of entries in the destination side payload queue
160 */
161 #define DEST_Q_SIZE 20
162 /*
163 * number of destination side software ack resources
164 */
165 #define DEST_NUM_RESOURCES 8
166 /*
167 * completion statuses for sending a TLB flush message
168 */
169 #define FLUSH_RETRY_PLUGGED 1
170 #define FLUSH_RETRY_TIMEOUT 2
171 #define FLUSH_GIVEUP 3
172 #define FLUSH_COMPLETE 4
173
174 /*
175 * tuning the action when the numalink network is extremely delayed
176 */
177 #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
178 microseconds */
179 #define CONGESTED_REPS 10 /* long delays averaged over
180 this many broadcasts */
181 #define DISABLED_PERIOD 10 /* time for the bau to be
182 disabled, in seconds */
183 /* see msg_type: */
184 #define MSG_NOOP 0
185 #define MSG_REGULAR 1
186 #define MSG_RETRY 2
187
188 #define BAU_DESC_QUALIFIER 0x534749
189
190 enum uv_bau_version {
191 UV_BAU_V1 = 1,
192 UV_BAU_V2,
193 UV_BAU_V3,
194 UV_BAU_V4,
195 };
196
197 /*
198 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
199 * If the 'multilevel' flag in the header portion of the descriptor
200 * has been set to 0, then endpoint multi-unicast mode is selected.
201 * The distribution specification (32 bytes) is interpreted as a 256-bit
202 * distribution vector. Adjacent bits correspond to consecutive even numbered
203 * nodeIDs. The result of adding the index of a given bit to the 15-bit
204 * 'base_dest_nasid' field of the header corresponds to the
205 * destination nodeID associated with that specified bit.
206 */
207 struct pnmask {
208 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
209 };
210
211 /*
212 * mask of cpu's on a uvhub
213 * (during initialization we need to check that unsigned long has
214 * enough bits for max. cpu's per uvhub)
215 */
216 struct bau_local_cpumask {
217 unsigned long bits;
218 };
219
220 /*
221 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
222 * only 12 bytes (96 bits) of the payload area are usable.
223 * An additional 3 bytes (bits 27:4) of the header address are carried
224 * to the next bytes of the destination payload queue.
225 * And an additional 2 bytes of the header Suppl_A field are also
226 * carried to the destination payload queue.
227 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
228 * of the destination payload queue, which is written by the hardware
229 * with the s/w ack resource bit vector.
230 * [ effective message contents (16 bytes (128 bits) maximum), not counting
231 * the s/w ack bit vector ]
232 */
233
234 /**
235 * struct uv1_2_3_bau_msg_payload - defines payload for INTD transactions
236 * @address: Signifies a page or all TLB's of the cpu
237 * @sending_cpu: CPU from which the message originates
238 * @acknowledge_count: CPUs on the destination Hub that received the interrupt
239 */
240 struct uv1_2_3_bau_msg_payload {
241 u64 address;
242 u16 sending_cpu;
243 u16 acknowledge_count;
244 };
245
246 /**
247 * struct uv4_bau_msg_payload - defines payload for INTD transactions
248 * @address: Signifies a page or all TLB's of the cpu
249 * @sending_cpu: CPU from which the message originates
250 * @acknowledge_count: CPUs on the destination Hub that received the interrupt
251 * @qualifier: Set by source to verify origin of INTD broadcast
252 */
253 struct uv4_bau_msg_payload {
254 u64 address;
255 u16 sending_cpu;
256 u16 acknowledge_count;
257 u32 reserved:8;
258 u32 qualifier:24;
259 };
260
261 /*
262 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
263 * see table 4.2.3.0.1 in broacast_assist spec.
264 */
265 struct uv1_bau_msg_header {
266 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
267 /* bits 5:0 */
268 unsigned int base_dest_nasid:15; /* nasid of the first bit */
269 /* bits 20:6 */ /* in uvhub map */
270 unsigned int command:8; /* message type */
271 /* bits 28:21 */
272 /* 0x38: SN3net EndPoint Message */
273 unsigned int rsvd_1:3; /* must be zero */
274 /* bits 31:29 */
275 /* int will align on 32 bits */
276 unsigned int rsvd_2:9; /* must be zero */
277 /* bits 40:32 */
278 /* Suppl_A is 56-41 */
279 unsigned int sequence:16; /* message sequence number */
280 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
281 /* Address field (96:57) is
282 never used as an address
283 (these are address bits
284 42:3) */
285
286 unsigned int rsvd_3:1; /* must be zero */
287 /* bit 57 */
288 /* address bits 27:4 are payload */
289 /* these next 24 (58-81) bits become bytes 12-14 of msg */
290 /* bits 65:58 land in byte 12 */
291 unsigned int replied_to:1; /* sent as 0 by the source to
292 byte 12 */
293 /* bit 58 */
294 unsigned int msg_type:3; /* software type of the
295 message */
296 /* bits 61:59 */
297 unsigned int canceled:1; /* message canceled, resource
298 is to be freed*/
299 /* bit 62 */
300 unsigned int payload_1a:1; /* not currently used */
301 /* bit 63 */
302 unsigned int payload_1b:2; /* not currently used */
303 /* bits 65:64 */
304
305 /* bits 73:66 land in byte 13 */
306 unsigned int payload_1ca:6; /* not currently used */
307 /* bits 71:66 */
308 unsigned int payload_1c:2; /* not currently used */
309 /* bits 73:72 */
310
311 /* bits 81:74 land in byte 14 */
312 unsigned int payload_1d:6; /* not currently used */
313 /* bits 79:74 */
314 unsigned int payload_1e:2; /* not currently used */
315 /* bits 81:80 */
316
317 unsigned int rsvd_4:7; /* must be zero */
318 /* bits 88:82 */
319 unsigned int swack_flag:1; /* software acknowledge flag */
320 /* bit 89 */
321 /* INTD trasactions at
322 destination are to wait for
323 software acknowledge */
324 unsigned int rsvd_5:6; /* must be zero */
325 /* bits 95:90 */
326 unsigned int rsvd_6:5; /* must be zero */
327 /* bits 100:96 */
328 unsigned int int_both:1; /* if 1, interrupt both sockets
329 on the uvhub */
330 /* bit 101*/
331 unsigned int fairness:3; /* usually zero */
332 /* bits 104:102 */
333 unsigned int multilevel:1; /* multi-level multicast
334 format */
335 /* bit 105 */
336 /* 0 for TLB: endpoint multi-unicast messages */
337 unsigned int chaining:1; /* next descriptor is part of
338 this activation*/
339 /* bit 106 */
340 unsigned int rsvd_7:21; /* must be zero */
341 /* bits 127:107 */
342 };
343
344 /*
345 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
346 * see figure 9-2 of harp_sys.pdf
347 * assuming UV3 is the same
348 */
349 struct uv2_3_bau_msg_header {
350 unsigned int base_dest_nasid:15; /* nasid of the first bit */
351 /* bits 14:0 */ /* in uvhub map */
352 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */
353 /* bits 19:15 */
354 unsigned int rsvd_1:1; /* must be zero */
355 /* bit 20 */
356 /* Address bits 59:21 */
357 /* bits 25:2 of address (44:21) are payload */
358 /* these next 24 bits become bytes 12-14 of msg */
359 /* bits 28:21 land in byte 12 */
360 unsigned int replied_to:1; /* sent as 0 by the source to
361 byte 12 */
362 /* bit 21 */
363 unsigned int msg_type:3; /* software type of the
364 message */
365 /* bits 24:22 */
366 unsigned int canceled:1; /* message canceled, resource
367 is to be freed*/
368 /* bit 25 */
369 unsigned int payload_1:3; /* not currently used */
370 /* bits 28:26 */
371
372 /* bits 36:29 land in byte 13 */
373 unsigned int payload_2a:3; /* not currently used */
374 unsigned int payload_2b:5; /* not currently used */
375 /* bits 36:29 */
376
377 /* bits 44:37 land in byte 14 */
378 unsigned int payload_3:8; /* not currently used */
379 /* bits 44:37 */
380
381 unsigned int rsvd_2:7; /* reserved */
382 /* bits 51:45 */
383 unsigned int swack_flag:1; /* software acknowledge flag */
384 /* bit 52 */
385 unsigned int rsvd_3a:3; /* must be zero */
386 unsigned int rsvd_3b:8; /* must be zero */
387 unsigned int rsvd_3c:8; /* must be zero */
388 unsigned int rsvd_3d:3; /* must be zero */
389 /* bits 74:53 */
390 unsigned int fairness:3; /* usually zero */
391 /* bits 77:75 */
392
393 unsigned int sequence:16; /* message sequence number */
394 /* bits 93:78 Suppl_A */
395 unsigned int chaining:1; /* next descriptor is part of
396 this activation*/
397 /* bit 94 */
398 unsigned int multilevel:1; /* multi-level multicast
399 format */
400 /* bit 95 */
401 unsigned int rsvd_4:24; /* ordered / source node /
402 source subnode / aging
403 must be zero */
404 /* bits 119:96 */
405 unsigned int command:8; /* message type */
406 /* bits 127:120 */
407 };
408
409 /*
410 * The activation descriptor:
411 * The format of the message to send, plus all accompanying control
412 * Should be 64 bytes
413 */
414 struct bau_desc {
415 struct pnmask distribution;
416 /*
417 * message template, consisting of header and payload:
418 */
419 union bau_msg_header {
420 struct uv1_bau_msg_header uv1_hdr;
421 struct uv2_3_bau_msg_header uv2_3_hdr;
422 } header;
423
424 union bau_payload_header {
425 struct uv1_2_3_bau_msg_payload uv1_2_3;
426 struct uv4_bau_msg_payload uv4;
427 } payload;
428 };
429 /* UV1:
430 * -payload-- ---------header------
431 * bytes 0-11 bits 41-56 bits 58-81
432 * A B (2) C (3)
433 *
434 * A/B/C are moved to:
435 * A C B
436 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
437 * ------------payload queue-----------
438 */
439 /* UV2:
440 * -payload-- ---------header------
441 * bytes 0-11 bits 70-78 bits 21-44
442 * A B (2) C (3)
443 *
444 * A/B/C are moved to:
445 * A C B
446 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
447 * ------------payload queue-----------
448 */
449
450 /*
451 * The payload queue on the destination side is an array of these.
452 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
453 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
454 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
455 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
456 * swack_vec and payload_2)
457 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
458 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
459 * operation."
460 */
461 struct bau_pq_entry {
462 unsigned long address; /* signifies a page or all TLB's
463 of the cpu */
464 /* 64 bits, bytes 0-7 */
465 unsigned short sending_cpu; /* cpu that sent the message */
466 /* 16 bits, bytes 8-9 */
467 unsigned short acknowledge_count; /* filled in by destination */
468 /* 16 bits, bytes 10-11 */
469 /* these next 3 bytes come from bits 58-81 of the message header */
470 unsigned short replied_to:1; /* sent as 0 by the source */
471 unsigned short msg_type:3; /* software message type */
472 unsigned short canceled:1; /* sent as 0 by the source */
473 unsigned short unused1:3; /* not currently using */
474 /* byte 12 */
475 unsigned char unused2a; /* not currently using */
476 /* byte 13 */
477 unsigned char unused2; /* not currently using */
478 /* byte 14 */
479 unsigned char swack_vec; /* filled in by the hardware */
480 /* byte 15 (bits 127:120) */
481 unsigned short sequence; /* message sequence number */
482 /* bytes 16-17 */
483 unsigned char unused4[2]; /* not currently using bytes 18-19 */
484 /* bytes 18-19 */
485 int number_of_cpus; /* filled in at destination */
486 /* 32 bits, bytes 20-23 (aligned) */
487 unsigned char unused5[8]; /* not using */
488 /* bytes 24-31 */
489 };
490
491 struct msg_desc {
492 struct bau_pq_entry *msg;
493 int msg_slot;
494 struct bau_pq_entry *queue_first;
495 struct bau_pq_entry *queue_last;
496 };
497
498 struct reset_args {
499 int sender;
500 };
501
502 /*
503 * This structure is allocated per_cpu for UV TLB shootdown statistics.
504 */
505 struct ptc_stats {
506 /* sender statistics */
507 unsigned long s_giveup; /* number of fall backs to
508 IPI-style flushes */
509 unsigned long s_requestor; /* number of shootdown
510 requests */
511 unsigned long s_stimeout; /* source side timeouts */
512 unsigned long s_dtimeout; /* destination side timeouts */
513 unsigned long s_strongnacks; /* number of strong nack's */
514 unsigned long s_time; /* time spent in sending side */
515 unsigned long s_retriesok; /* successful retries */
516 unsigned long s_ntargcpu; /* total number of cpu's
517 targeted */
518 unsigned long s_ntargself; /* times the sending cpu was
519 targeted */
520 unsigned long s_ntarglocals; /* targets of cpus on the local
521 blade */
522 unsigned long s_ntargremotes; /* targets of cpus on remote
523 blades */
524 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
525 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
526 unsigned long s_ntarguvhub; /* total number of uvhubs
527 targeted */
528 unsigned long s_ntarguvhub16; /* number of times target
529 hubs >= 16*/
530 unsigned long s_ntarguvhub8; /* number of times target
531 hubs >= 8 */
532 unsigned long s_ntarguvhub4; /* number of times target
533 hubs >= 4 */
534 unsigned long s_ntarguvhub2; /* number of times target
535 hubs >= 2 */
536 unsigned long s_ntarguvhub1; /* number of times target
537 hubs == 1 */
538 unsigned long s_resets_plug; /* ipi-style resets from plug
539 state */
540 unsigned long s_resets_timeout; /* ipi-style resets from
541 timeouts */
542 unsigned long s_busy; /* status stayed busy past
543 s/w timer */
544 unsigned long s_throttles; /* waits in throttle */
545 unsigned long s_retry_messages; /* retry broadcasts */
546 unsigned long s_bau_reenabled; /* for bau enable/disable */
547 unsigned long s_bau_disabled; /* for bau enable/disable */
548 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */
549 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */
550 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */
551 unsigned long s_overipilimit; /* over the ipi reset limit */
552 unsigned long s_giveuplimit; /* disables, over giveup limit*/
553 unsigned long s_enters; /* entries to the driver */
554 unsigned long s_ipifordisabled; /* fall back to IPI; disabled */
555 unsigned long s_plugged; /* plugged by h/w bug*/
556 unsigned long s_congested; /* giveup on long wait */
557 /* destination statistics */
558 unsigned long d_alltlb; /* times all tlb's on this
559 cpu were flushed */
560 unsigned long d_onetlb; /* times just one tlb on this
561 cpu was flushed */
562 unsigned long d_multmsg; /* interrupts with multiple
563 messages */
564 unsigned long d_nomsg; /* interrupts with no message */
565 unsigned long d_time; /* time spent on destination
566 side */
567 unsigned long d_requestee; /* number of messages
568 processed */
569 unsigned long d_retries; /* number of retry messages
570 processed */
571 unsigned long d_canceled; /* number of messages canceled
572 by retries */
573 unsigned long d_nocanceled; /* retries that found nothing
574 to cancel */
575 unsigned long d_resets; /* number of ipi-style requests
576 processed */
577 unsigned long d_rcanceled; /* number of messages canceled
578 by resets */
579 };
580
581 struct tunables {
582 int *tunp;
583 int deflt;
584 };
585
586 struct hub_and_pnode {
587 short uvhub;
588 short pnode;
589 };
590
591 struct socket_desc {
592 short num_cpus;
593 short cpu_number[MAX_CPUS_PER_SOCKET];
594 };
595
596 struct uvhub_desc {
597 unsigned short socket_mask;
598 short num_cpus;
599 short uvhub;
600 short pnode;
601 struct socket_desc socket[2];
602 };
603
604 /**
605 * struct bau_control
606 * @status_mmr: location of status mmr, determined by uvhub_cpu
607 * @status_index: index of ERR|BUSY bits in status mmr, determined by uvhub_cpu
608 *
609 * Per-cpu control struct containing CPU topology information and BAU tuneables.
610 */
611 struct bau_control {
612 struct bau_desc *descriptor_base;
613 struct bau_pq_entry *queue_first;
614 struct bau_pq_entry *queue_last;
615 struct bau_pq_entry *bau_msg_head;
616 struct bau_control *uvhub_master;
617 struct bau_control *socket_master;
618 struct ptc_stats *statp;
619 cpumask_t *cpumask;
620 unsigned long timeout_interval;
621 unsigned long set_bau_on_time;
622 atomic_t active_descriptor_count;
623 int plugged_tries;
624 int timeout_tries;
625 int ipi_attempts;
626 int conseccompletes;
627 u64 status_mmr;
628 int status_index;
629 bool nobau;
630 short baudisabled;
631 short cpu;
632 short osnode;
633 short uvhub_cpu;
634 short uvhub;
635 short uvhub_version;
636 short cpus_in_socket;
637 short cpus_in_uvhub;
638 short partition_base_pnode;
639 short busy; /* all were busy (war) */
640 unsigned short message_number;
641 unsigned short uvhub_quiesce;
642 short socket_acknowledge_count[DEST_Q_SIZE];
643 cycles_t send_message;
644 cycles_t period_end;
645 cycles_t period_time;
646 spinlock_t uvhub_lock;
647 spinlock_t queue_lock;
648 spinlock_t disable_lock;
649 /* tunables */
650 int max_concurr;
651 int max_concurr_const;
652 int plugged_delay;
653 int plugsb4reset;
654 int timeoutsb4reset;
655 int ipi_reset_limit;
656 int complete_threshold;
657 int cong_response_us;
658 int cong_reps;
659 cycles_t disabled_period;
660 int period_giveups;
661 int giveup_limit;
662 long period_requests;
663 struct hub_and_pnode *thp;
664 };
665
666 /* Abstracted BAU functions */
667 struct bau_operations {
668 unsigned long (*read_l_sw_ack)(void);
669 unsigned long (*read_g_sw_ack)(int pnode);
670 unsigned long (*bau_gpa_to_offset)(unsigned long vaddr);
671 void (*write_l_sw_ack)(unsigned long mmr);
672 void (*write_g_sw_ack)(int pnode, unsigned long mmr);
673 void (*write_payload_first)(int pnode, unsigned long mmr);
674 void (*write_payload_last)(int pnode, unsigned long mmr);
675 int (*wait_completion)(struct bau_desc*,
676 struct bau_control*, long try);
677 };
678
679 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
680 {
681 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
682 }
683
684 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
685 {
686 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
687 }
688
689 static inline void write_mmr_activation(unsigned long index)
690 {
691 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
692 }
693
694 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
695 {
696 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
697 }
698
699 static inline void write_mmr_proc_payload_first(int pnode, unsigned long mmr_image)
700 {
701 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_FIRST, mmr_image);
702 }
703
704 static inline void write_mmr_proc_payload_last(int pnode, unsigned long mmr_image)
705 {
706 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_LAST, mmr_image);
707 }
708
709 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
710 {
711 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
712 }
713
714 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
715 {
716 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
717 }
718
719 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
720 {
721 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
722 }
723
724 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
725 {
726 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
727 }
728
729 static inline unsigned long read_mmr_misc_control(int pnode)
730 {
731 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
732 }
733
734 static inline void write_mmr_sw_ack(unsigned long mr)
735 {
736 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
737 }
738
739 static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
740 {
741 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
742 }
743
744 static inline unsigned long read_mmr_sw_ack(void)
745 {
746 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
747 }
748
749 static inline unsigned long read_gmmr_sw_ack(int pnode)
750 {
751 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
752 }
753
754 static inline void write_mmr_proc_sw_ack(unsigned long mr)
755 {
756 uv_write_local_mmr(UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
757 }
758
759 static inline void write_gmmr_proc_sw_ack(int pnode, unsigned long mr)
760 {
761 write_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
762 }
763
764 static inline unsigned long read_mmr_proc_sw_ack(void)
765 {
766 return read_lmmr(UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
767 }
768
769 static inline unsigned long read_gmmr_proc_sw_ack(int pnode)
770 {
771 return read_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
772 }
773
774 static inline void write_mmr_data_config(int pnode, unsigned long mr)
775 {
776 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
777 }
778
779 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
780 {
781 return constant_test_bit(uvhub, &dstp->bits[0]);
782 }
783 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
784 {
785 __set_bit(pnode, &dstp->bits[0]);
786 }
787 static inline void bau_uvhubs_clear(struct pnmask *dstp,
788 int nbits)
789 {
790 bitmap_zero(&dstp->bits[0], nbits);
791 }
792 static inline int bau_uvhub_weight(struct pnmask *dstp)
793 {
794 return bitmap_weight((unsigned long *)&dstp->bits[0],
795 UV_DISTRIBUTION_SIZE);
796 }
797
798 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
799 {
800 bitmap_zero(&dstp->bits, nbits);
801 }
802
803 extern void uv_bau_message_intr1(void);
804 #ifdef CONFIG_TRACING
805 #define trace_uv_bau_message_intr1 uv_bau_message_intr1
806 #endif
807 extern void uv_bau_timeout_intr1(void);
808
809 struct atomic_short {
810 short counter;
811 };
812
813 /*
814 * atomic_read_short - read a short atomic variable
815 * @v: pointer of type atomic_short
816 *
817 * Atomically reads the value of @v.
818 */
819 static inline int atomic_read_short(const struct atomic_short *v)
820 {
821 return v->counter;
822 }
823
824 /*
825 * atom_asr - add and return a short int
826 * @i: short value to add
827 * @v: pointer of type atomic_short
828 *
829 * Atomically adds @i to @v and returns @i + @v
830 */
831 static inline int atom_asr(short i, struct atomic_short *v)
832 {
833 short __i = i;
834 asm volatile(LOCK_PREFIX "xaddw %0, %1"
835 : "+r" (i), "+m" (v->counter)
836 : : "memory");
837 return i + __i;
838 }
839
840 /*
841 * conditionally add 1 to *v, unless *v is >= u
842 * return 0 if we cannot add 1 to *v because it is >= u
843 * return 1 if we can add 1 to *v because it is < u
844 * the add is atomic
845 *
846 * This is close to atomic_add_unless(), but this allows the 'u' value
847 * to be lowered below the current 'v'. atomic_add_unless can only stop
848 * on equal.
849 */
850 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
851 {
852 spin_lock(lock);
853 if (atomic_read(v) >= u) {
854 spin_unlock(lock);
855 return 0;
856 }
857 atomic_inc(v);
858 spin_unlock(lock);
859 return 1;
860 }
861
862 #endif /* _ASM_X86_UV_UV_BAU_H */
Linux with added FPC-III support