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cpu/hotplug: Cleanup state names
[linux/fpc-iii.git] / drivers / gpio / gpio-mxs.c
blob1e8fde8cb803d7406dd98d51673b63eb69fdfd23
1 /*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23 #include <linux/err.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/driver.h>
35 /* FIXME: for gpio_get_value(), replace this by direct register read */
36 #include <linux/gpio.h>
37 #include <linux/module.h>
38
39 #define MXS_SET 0x4
40 #define MXS_CLR 0x8
41
42 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
43 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
44 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
45 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
46 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
47 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
48 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
49 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
50
51 #define GPIO_INT_FALL_EDGE 0x0
52 #define GPIO_INT_LOW_LEV 0x1
53 #define GPIO_INT_RISE_EDGE 0x2
54 #define GPIO_INT_HIGH_LEV 0x3
55 #define GPIO_INT_LEV_MASK (1 << 0)
56 #define GPIO_INT_POL_MASK (1 << 1)
57
58 enum mxs_gpio_id {
59 IMX23_GPIO,
60 IMX28_GPIO,
61 };
62
63 struct mxs_gpio_port {
64 void __iomem *base;
65 int id;
66 int irq;
67 struct irq_domain *domain;
68 struct gpio_chip gc;
69 enum mxs_gpio_id devid;
70 u32 both_edges;
71 };
72
73 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
74 {
75 return port->devid == IMX23_GPIO;
76 }
77
78 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
79 {
80 return port->devid == IMX28_GPIO;
81 }
82
83 /* Note: This driver assumes 32 GPIOs are handled in one register */
84
85 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
86 {
87 u32 val;
88 u32 pin_mask = 1 << d->hwirq;
89 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
90 struct irq_chip_type *ct = irq_data_get_chip_type(d);
91 struct mxs_gpio_port *port = gc->private;
92 void __iomem *pin_addr;
93 int edge;
94
95 if (!(ct->type & type))
96 if (irq_setup_alt_chip(d, type))
97 return -EINVAL;
98
99 port->both_edges &= ~pin_mask;
100 switch (type) {
101 case IRQ_TYPE_EDGE_BOTH:
102 val = gpio_get_value(port->gc.base + d->hwirq);
103 if (val)
104 edge = GPIO_INT_FALL_EDGE;
105 else
106 edge = GPIO_INT_RISE_EDGE;
107 port->both_edges |= pin_mask;
108 break;
109 case IRQ_TYPE_EDGE_RISING:
110 edge = GPIO_INT_RISE_EDGE;
111 break;
112 case IRQ_TYPE_EDGE_FALLING:
113 edge = GPIO_INT_FALL_EDGE;
114 break;
115 case IRQ_TYPE_LEVEL_LOW:
116 edge = GPIO_INT_LOW_LEV;
117 break;
118 case IRQ_TYPE_LEVEL_HIGH:
119 edge = GPIO_INT_HIGH_LEV;
120 break;
121 default:
122 return -EINVAL;
123 }
124
125 /* set level or edge */
126 pin_addr = port->base + PINCTRL_IRQLEV(port);
127 if (edge & GPIO_INT_LEV_MASK) {
128 writel(pin_mask, pin_addr + MXS_SET);
129 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
130 } else {
131 writel(pin_mask, pin_addr + MXS_CLR);
132 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
133 }
134
135 /* set polarity */
136 pin_addr = port->base + PINCTRL_IRQPOL(port);
137 if (edge & GPIO_INT_POL_MASK)
138 writel(pin_mask, pin_addr + MXS_SET);
139 else
140 writel(pin_mask, pin_addr + MXS_CLR);
141
142 writel(pin_mask,
143 port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
144
145 return 0;
146 }
147
148 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
149 {
150 u32 bit, val, edge;
151 void __iomem *pin_addr;
152
153 bit = 1 << gpio;
154
155 pin_addr = port->base + PINCTRL_IRQPOL(port);
156 val = readl(pin_addr);
157 edge = val & bit;
158
159 if (edge)
160 writel(bit, pin_addr + MXS_CLR);
161 else
162 writel(bit, pin_addr + MXS_SET);
163 }
164
165 /* MXS has one interrupt *per* gpio port */
166 static void mxs_gpio_irq_handler(struct irq_desc *desc)
167 {
168 u32 irq_stat;
169 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
170
171 desc->irq_data.chip->irq_ack(&desc->irq_data);
172
173 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
174 readl(port->base + PINCTRL_IRQEN(port));
175
176 while (irq_stat != 0) {
177 int irqoffset = fls(irq_stat) - 1;
178 if (port->both_edges & (1 << irqoffset))
179 mxs_flip_edge(port, irqoffset);
180
181 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
182 irq_stat &= ~(1 << irqoffset);
183 }
184 }
185
186 /*
187 * Set interrupt number "irq" in the GPIO as a wake-up source.
188 * While system is running, all registered GPIO interrupts need to have
189 * wake-up enabled. When system is suspended, only selected GPIO interrupts
190 * need to have wake-up enabled.
191 * @param irq interrupt source number
192 * @param enable enable as wake-up if equal to non-zero
193 * @return This function returns 0 on success.
194 */
195 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
196 {
197 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
198 struct mxs_gpio_port *port = gc->private;
199
200 if (enable)
201 enable_irq_wake(port->irq);
202 else
203 disable_irq_wake(port->irq);
204
205 return 0;
206 }
207
208 static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
209 {
210 struct irq_chip_generic *gc;
211 struct irq_chip_type *ct;
212
213 gc = irq_alloc_generic_chip("gpio-mxs", 2, irq_base,
214 port->base, handle_level_irq);
215 if (!gc)
216 return -ENOMEM;
217
218 gc->private = port;
219
220 ct = &gc->chip_types[0];
221 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
222 ct->chip.irq_ack = irq_gc_ack_set_bit;
223 ct->chip.irq_mask = irq_gc_mask_disable_reg;
224 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
225 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
226 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
227 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
228 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
229 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
230 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
231
232 ct = &gc->chip_types[1];
233 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
234 ct->chip.irq_ack = irq_gc_ack_set_bit;
235 ct->chip.irq_mask = irq_gc_mask_disable_reg;
236 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
237 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
238 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
239 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
240 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
241 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
242 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
243 ct->handler = handle_level_irq;
244
245 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
246 IRQ_NOREQUEST, 0);
247
248 return 0;
249 }
250
251 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
252 {
253 struct mxs_gpio_port *port = gpiochip_get_data(gc);
254
255 return irq_find_mapping(port->domain, offset);
256 }
257
258 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
259 {
260 struct mxs_gpio_port *port = gpiochip_get_data(gc);
261 u32 mask = 1 << offset;
262 u32 dir;
263
264 dir = readl(port->base + PINCTRL_DOE(port));
265 return !(dir & mask);
266 }
267
268 static const struct platform_device_id mxs_gpio_ids[] = {
269 {
270 .name = "imx23-gpio",
271 .driver_data = IMX23_GPIO,
272 }, {
273 .name = "imx28-gpio",
274 .driver_data = IMX28_GPIO,
275 }, {
276 /* sentinel */
277 }
278 };
279 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
280
281 static const struct of_device_id mxs_gpio_dt_ids[] = {
282 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
283 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
284 { /* sentinel */ }
285 };
286 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
287
288 static int mxs_gpio_probe(struct platform_device *pdev)
289 {
290 const struct of_device_id *of_id =
291 of_match_device(mxs_gpio_dt_ids, &pdev->dev);
292 struct device_node *np = pdev->dev.of_node;
293 struct device_node *parent;
294 static void __iomem *base;
295 struct mxs_gpio_port *port;
296 int irq_base;
297 int err;
298
299 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
300 if (!port)
301 return -ENOMEM;
302
303 port->id = of_alias_get_id(np, "gpio");
304 if (port->id < 0)
305 return port->id;
306 port->devid = (enum mxs_gpio_id) of_id->data;
307 port->irq = platform_get_irq(pdev, 0);
308 if (port->irq < 0)
309 return port->irq;
310
311 /*
312 * map memory region only once, as all the gpio ports
313 * share the same one
314 */
315 if (!base) {
316 parent = of_get_parent(np);
317 base = of_iomap(parent, 0);
318 of_node_put(parent);
319 if (!base)
320 return -EADDRNOTAVAIL;
321 }
322 port->base = base;
323
324 /* initially disable the interrupts */
325 writel(0, port->base + PINCTRL_PIN2IRQ(port));
326 writel(0, port->base + PINCTRL_IRQEN(port));
327
328 /* clear address has to be used to clear IRQSTAT bits */
329 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
330
331 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
332 if (irq_base < 0) {
333 err = irq_base;
334 goto out_iounmap;
335 }
336
337 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
338 &irq_domain_simple_ops, NULL);
339 if (!port->domain) {
340 err = -ENODEV;
341 goto out_irqdesc_free;
342 }
343
344 /* gpio-mxs can be a generic irq chip */
345 err = mxs_gpio_init_gc(port, irq_base);
346 if (err < 0)
347 goto out_irqdomain_remove;
348
349 /* setup one handler for each entry */
350 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
351 port);
352
353 err = bgpio_init(&port->gc, &pdev->dev, 4,
354 port->base + PINCTRL_DIN(port),
355 port->base + PINCTRL_DOUT(port) + MXS_SET,
356 port->base + PINCTRL_DOUT(port) + MXS_CLR,
357 port->base + PINCTRL_DOE(port), NULL, 0);
358 if (err)
359 goto out_irqdomain_remove;
360
361 port->gc.to_irq = mxs_gpio_to_irq;
362 port->gc.get_direction = mxs_gpio_get_direction;
363 port->gc.base = port->id * 32;
364
365 err = gpiochip_add_data(&port->gc, port);
366 if (err)
367 goto out_irqdomain_remove;
368
369 return 0;
370
371 out_irqdomain_remove:
372 irq_domain_remove(port->domain);
373 out_irqdesc_free:
374 irq_free_descs(irq_base, 32);
375 out_iounmap:
376 iounmap(port->base);
377 return err;
378 }
379
380 static struct platform_driver mxs_gpio_driver = {
381 .driver = {
382 .name = "gpio-mxs",
383 .of_match_table = mxs_gpio_dt_ids,
384 },
385 .probe = mxs_gpio_probe,
386 .id_table = mxs_gpio_ids,
387 };
388
389 static int __init mxs_gpio_init(void)
390 {
391 return platform_driver_register(&mxs_gpio_driver);
392 }
393 postcore_initcall(mxs_gpio_init);
394
395 MODULE_AUTHOR("Freescale Semiconductor, "
396 "Daniel Mack <danielncaiaq.de>, "
397 "Juergen Beisert <kernel@pengutronix.de>");
398 MODULE_DESCRIPTION("Freescale MXS GPIO");
399 MODULE_LICENSE("GPL");
Linux with added FPC-III support