2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/export.h>
14 #include <linux/delay.h>
15 #include <linux/ssb/ssb_embedded.h>
17 #include "ssb_private.h"
19 static u32
ssb_pcie_read(struct ssb_pcicore
*pc
, u32 address
);
20 static void ssb_pcie_write(struct ssb_pcicore
*pc
, u32 address
, u32 data
);
21 static u16
ssb_pcie_mdio_read(struct ssb_pcicore
*pc
, u8 device
, u8 address
);
22 static void ssb_pcie_mdio_write(struct ssb_pcicore
*pc
, u8 device
,
23 u8 address
, u16 data
);
26 u32
pcicore_read32(struct ssb_pcicore
*pc
, u16 offset
)
28 return ssb_read32(pc
->dev
, offset
);
32 void pcicore_write32(struct ssb_pcicore
*pc
, u16 offset
, u32 value
)
34 ssb_write32(pc
->dev
, offset
, value
);
38 u16
pcicore_read16(struct ssb_pcicore
*pc
, u16 offset
)
40 return ssb_read16(pc
->dev
, offset
);
44 void pcicore_write16(struct ssb_pcicore
*pc
, u16 offset
, u16 value
)
46 ssb_write16(pc
->dev
, offset
, value
);
49 /**************************************************
50 * Code for hostmode operation.
51 **************************************************/
53 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
55 #include <asm/paccess.h>
56 /* Probe a 32bit value on the bus and catch bus exceptions.
57 * Returns nonzero on a bus exception.
58 * This is MIPS specific */
59 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
61 /* Assume one-hot slot wiring */
62 #define SSB_PCI_SLOT_MAX 16
64 /* Global lock is OK, as we won't have more than one extpci anyway. */
65 static DEFINE_SPINLOCK(cfgspace_lock
);
66 /* Core to access the external PCI config space. Can only have one. */
67 static struct ssb_pcicore
*extpci_core
;
70 static u32
get_cfgspace_addr(struct ssb_pcicore
*pc
,
71 unsigned int bus
, unsigned int dev
,
72 unsigned int func
, unsigned int off
)
77 /* We do only have one cardbus device behind the bridge. */
78 if (pc
->cardbusmode
&& (dev
> 1))
82 /* Type 0 transaction */
83 if (unlikely(dev
>= SSB_PCI_SLOT_MAX
))
85 /* Slide the window */
86 tmp
= SSB_PCICORE_SBTOPCI_CFG0
;
87 tmp
|= ((1 << (dev
+ 16)) & SSB_PCICORE_SBTOPCI1_MASK
);
88 pcicore_write32(pc
, SSB_PCICORE_SBTOPCI1
, tmp
);
89 /* Calculate the address */
91 addr
|= ((1 << (dev
+ 16)) & ~SSB_PCICORE_SBTOPCI1_MASK
);
95 /* Type 1 transaction */
96 pcicore_write32(pc
, SSB_PCICORE_SBTOPCI1
,
97 SSB_PCICORE_SBTOPCI_CFG1
);
98 /* Calculate the address */
109 static int ssb_extpci_read_config(struct ssb_pcicore
*pc
,
110 unsigned int bus
, unsigned int dev
,
111 unsigned int func
, unsigned int off
,
118 SSB_WARN_ON(!pc
->hostmode
);
119 if (unlikely(len
!= 1 && len
!= 2 && len
!= 4))
121 addr
= get_cfgspace_addr(pc
, bus
, dev
, func
, off
);
125 mmio
= ioremap_nocache(addr
, len
);
129 if (mips_busprobe32(val
, mmio
)) {
135 val
>>= (8 * (off
& 3));
139 *((u8
*)buf
) = (u8
)val
;
142 *((u16
*)buf
) = (u16
)val
;
145 *((u32
*)buf
) = (u32
)val
;
155 static int ssb_extpci_write_config(struct ssb_pcicore
*pc
,
156 unsigned int bus
, unsigned int dev
,
157 unsigned int func
, unsigned int off
,
158 const void *buf
, int len
)
164 SSB_WARN_ON(!pc
->hostmode
);
165 if (unlikely(len
!= 1 && len
!= 2 && len
!= 4))
167 addr
= get_cfgspace_addr(pc
, bus
, dev
, func
, off
);
171 mmio
= ioremap_nocache(addr
, len
);
175 if (mips_busprobe32(val
, mmio
)) {
183 val
&= ~(0xFF << (8 * (off
& 3)));
184 val
|= *((const u8
*)buf
) << (8 * (off
& 3));
188 val
&= ~(0xFFFF << (8 * (off
& 3)));
189 val
|= *((const u16
*)buf
) << (8 * (off
& 3));
192 val
= *((const u32
*)buf
);
204 static int ssb_pcicore_read_config(struct pci_bus
*bus
, unsigned int devfn
,
205 int reg
, int size
, u32
*val
)
210 spin_lock_irqsave(&cfgspace_lock
, flags
);
211 err
= ssb_extpci_read_config(extpci_core
, bus
->number
, PCI_SLOT(devfn
),
212 PCI_FUNC(devfn
), reg
, val
, size
);
213 spin_unlock_irqrestore(&cfgspace_lock
, flags
);
215 return err
? PCIBIOS_DEVICE_NOT_FOUND
: PCIBIOS_SUCCESSFUL
;
218 static int ssb_pcicore_write_config(struct pci_bus
*bus
, unsigned int devfn
,
219 int reg
, int size
, u32 val
)
224 spin_lock_irqsave(&cfgspace_lock
, flags
);
225 err
= ssb_extpci_write_config(extpci_core
, bus
->number
, PCI_SLOT(devfn
),
226 PCI_FUNC(devfn
), reg
, &val
, size
);
227 spin_unlock_irqrestore(&cfgspace_lock
, flags
);
229 return err
? PCIBIOS_DEVICE_NOT_FOUND
: PCIBIOS_SUCCESSFUL
;
232 static struct pci_ops ssb_pcicore_pciops
= {
233 .read
= ssb_pcicore_read_config
,
234 .write
= ssb_pcicore_write_config
,
237 static struct resource ssb_pcicore_mem_resource
= {
238 .name
= "SSB PCIcore external memory",
239 .start
= SSB_PCI_DMA
,
240 .end
= SSB_PCI_DMA
+ SSB_PCI_DMA_SZ
- 1,
241 .flags
= IORESOURCE_MEM
| IORESOURCE_PCI_FIXED
,
244 static struct resource ssb_pcicore_io_resource
= {
245 .name
= "SSB PCIcore external I/O",
248 .flags
= IORESOURCE_IO
| IORESOURCE_PCI_FIXED
,
251 static struct pci_controller ssb_pcicore_controller
= {
252 .pci_ops
= &ssb_pcicore_pciops
,
253 .io_resource
= &ssb_pcicore_io_resource
,
254 .mem_resource
= &ssb_pcicore_mem_resource
,
257 /* This function is called when doing a pci_enable_device().
258 * We must first check if the device is a device on the PCI-core bridge. */
259 int ssb_pcicore_plat_dev_init(struct pci_dev
*d
)
261 if (d
->bus
->ops
!= &ssb_pcicore_pciops
) {
262 /* This is not a device on the PCI-core bridge. */
266 ssb_info("PCI: Fixing up device %s\n", pci_name(d
));
268 /* Fix up interrupt lines */
269 d
->irq
= ssb_mips_irq(extpci_core
->dev
) + 2;
270 pci_write_config_byte(d
, PCI_INTERRUPT_LINE
, d
->irq
);
275 /* Early PCI fixup for a device on the PCI-core bridge. */
276 static void ssb_pcicore_fixup_pcibridge(struct pci_dev
*dev
)
280 if (dev
->bus
->ops
!= &ssb_pcicore_pciops
) {
281 /* This is not a device on the PCI-core bridge. */
284 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) != 0)
287 ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev
));
289 /* Enable PCI bridge bus mastering and memory space */
291 if (pcibios_enable_device(dev
, ~0) < 0) {
292 ssb_err("PCI: SSB bridge enable failed\n");
296 /* Enable PCI bridge BAR1 prefetch and burst */
297 pci_write_config_dword(dev
, SSB_BAR1_CONTROL
, 3);
299 /* Make sure our latency is high enough to handle the devices behind us */
301 ssb_info("PCI: Fixing latency timer of device %s to %u\n",
303 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
305 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, ssb_pcicore_fixup_pcibridge
);
307 /* PCI device IRQ mapping. */
308 int ssb_pcicore_pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
310 if (dev
->bus
->ops
!= &ssb_pcicore_pciops
) {
311 /* This is not a device on the PCI-core bridge. */
314 return ssb_mips_irq(extpci_core
->dev
) + 2;
317 static void ssb_pcicore_init_hostmode(struct ssb_pcicore
*pc
)
321 if (WARN_ON(extpci_core
))
325 ssb_dbg("PCIcore in host mode found\n");
326 /* Reset devices on the external PCI bus */
327 val
= SSB_PCICORE_CTL_RST_OE
;
328 val
|= SSB_PCICORE_CTL_CLK_OE
;
329 pcicore_write32(pc
, SSB_PCICORE_CTL
, val
);
330 val
|= SSB_PCICORE_CTL_CLK
; /* Clock on */
331 pcicore_write32(pc
, SSB_PCICORE_CTL
, val
);
332 udelay(150); /* Assertion time demanded by the PCI standard */
333 val
|= SSB_PCICORE_CTL_RST
; /* Deassert RST# */
334 pcicore_write32(pc
, SSB_PCICORE_CTL
, val
);
335 val
= SSB_PCICORE_ARBCTL_INTERN
;
336 pcicore_write32(pc
, SSB_PCICORE_ARBCTL
, val
);
337 udelay(1); /* Assertion time demanded by the PCI standard */
339 if (pc
->dev
->bus
->has_cardbus_slot
) {
340 ssb_dbg("CardBus slot detected\n");
342 /* GPIO 1 resets the bridge */
343 ssb_gpio_out(pc
->dev
->bus
, 1, 1);
344 ssb_gpio_outen(pc
->dev
->bus
, 1, 1);
345 pcicore_write16(pc
, SSB_PCICORE_SPROM(0),
346 pcicore_read16(pc
, SSB_PCICORE_SPROM(0))
350 /* 64MB I/O window */
351 pcicore_write32(pc
, SSB_PCICORE_SBTOPCI0
,
352 SSB_PCICORE_SBTOPCI_IO
);
353 /* 64MB config space */
354 pcicore_write32(pc
, SSB_PCICORE_SBTOPCI1
,
355 SSB_PCICORE_SBTOPCI_CFG0
);
356 /* 1GB memory window */
357 pcicore_write32(pc
, SSB_PCICORE_SBTOPCI2
,
358 SSB_PCICORE_SBTOPCI_MEM
| SSB_PCI_DMA
);
360 /* Enable PCI bridge BAR0 prefetch and burst */
361 val
= PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
362 ssb_extpci_write_config(pc
, 0, 0, 0, PCI_COMMAND
, &val
, 2);
363 /* Clear error conditions */
365 ssb_extpci_write_config(pc
, 0, 0, 0, PCI_STATUS
, &val
, 2);
367 /* Enable PCI interrupts */
368 pcicore_write32(pc
, SSB_PCICORE_IMASK
,
369 SSB_PCICORE_IMASK_INTA
);
371 /* Ok, ready to run, register it to the system.
372 * The following needs change, if we want to port hostmode
373 * to non-MIPS platform. */
374 ssb_pcicore_controller
.io_map_base
= (unsigned long)ioremap_nocache(SSB_PCI_MEM
, 0x04000000);
375 set_io_port_base(ssb_pcicore_controller
.io_map_base
);
376 /* Give some time to the PCI controller to configure itself with the new
377 * values. Not waiting at this point causes crashes of the machine. */
379 register_pci_controller(&ssb_pcicore_controller
);
382 static int pcicore_is_in_hostmode(struct ssb_pcicore
*pc
)
384 struct ssb_bus
*bus
= pc
->dev
->bus
;
388 chipid_top
= (bus
->chip_id
& 0xFF00);
389 if (chipid_top
!= 0x4700 &&
390 chipid_top
!= 0x5300)
393 if (bus
->sprom
.boardflags_lo
& SSB_PCICORE_BFL_NOPCI
)
396 /* The 200-pin BCM4712 package does not bond out PCI. Even when
397 * PCI is bonded out, some boards may leave the pins floating. */
398 if (bus
->chip_id
== 0x4712) {
399 if (bus
->chip_package
== SSB_CHIPPACK_BCM4712S
)
401 if (bus
->chip_package
== SSB_CHIPPACK_BCM4712M
)
404 if (bus
->chip_id
== 0x5350)
407 return !mips_busprobe32(tmp
, (bus
->mmio
+ (pc
->dev
->core_index
* SSB_CORE_SIZE
)));
409 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
411 /**************************************************
413 **************************************************/
415 static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore
*pc
)
417 u16 tmp
= pcicore_read16(pc
, SSB_PCICORE_SPROM(0));
418 if (((tmp
& 0xF000) >> 12) != pc
->dev
->core_index
) {
420 tmp
|= (pc
->dev
->core_index
<< 12);
421 pcicore_write16(pc
, SSB_PCICORE_SPROM(0), tmp
);
425 static u8
ssb_pcicore_polarity_workaround(struct ssb_pcicore
*pc
)
427 return (ssb_pcie_read(pc
, 0x204) & 0x10) ? 0xC0 : 0x80;
430 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore
*pc
)
432 const u8 serdes_pll_device
= 0x1D;
433 const u8 serdes_rx_device
= 0x1F;
436 ssb_pcie_mdio_write(pc
, serdes_rx_device
, 1 /* Control */,
437 ssb_pcicore_polarity_workaround(pc
));
438 tmp
= ssb_pcie_mdio_read(pc
, serdes_pll_device
, 1 /* Control */);
440 ssb_pcie_mdio_write(pc
, serdes_pll_device
, 1, tmp
& ~0x4000);
443 static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore
*pc
)
445 struct ssb_device
*pdev
= pc
->dev
;
446 struct ssb_bus
*bus
= pdev
->bus
;
449 tmp
= pcicore_read32(pc
, SSB_PCICORE_SBTOPCI2
);
450 tmp
|= SSB_PCICORE_SBTOPCI_PREF
;
451 tmp
|= SSB_PCICORE_SBTOPCI_BURST
;
452 pcicore_write32(pc
, SSB_PCICORE_SBTOPCI2
, tmp
);
454 if (pdev
->id
.revision
< 5) {
455 tmp
= ssb_read32(pdev
, SSB_IMCFGLO
);
456 tmp
&= ~SSB_IMCFGLO_SERTO
;
458 tmp
&= ~SSB_IMCFGLO_REQTO
;
459 tmp
|= 3 << SSB_IMCFGLO_REQTO_SHIFT
;
460 ssb_write32(pdev
, SSB_IMCFGLO
, tmp
);
461 ssb_commit_settings(bus
);
462 } else if (pdev
->id
.revision
>= 11) {
463 tmp
= pcicore_read32(pc
, SSB_PCICORE_SBTOPCI2
);
464 tmp
|= SSB_PCICORE_SBTOPCI_MRM
;
465 pcicore_write32(pc
, SSB_PCICORE_SBTOPCI2
, tmp
);
469 static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore
*pc
)
472 u8 rev
= pc
->dev
->id
.revision
;
474 if (rev
== 0 || rev
== 1) {
475 /* TLP Workaround register. */
476 tmp
= ssb_pcie_read(pc
, 0x4);
478 ssb_pcie_write(pc
, 0x4, tmp
);
481 /* DLLP Link Control register. */
482 tmp
= ssb_pcie_read(pc
, 0x100);
484 ssb_pcie_write(pc
, 0x100, tmp
);
488 const u8 serdes_rx_device
= 0x1F;
490 ssb_pcie_mdio_write(pc
, serdes_rx_device
,
491 2 /* Timer */, 0x8128);
492 ssb_pcie_mdio_write(pc
, serdes_rx_device
,
493 6 /* CDR */, 0x0100);
494 ssb_pcie_mdio_write(pc
, serdes_rx_device
,
495 7 /* CDR BW */, 0x1466);
496 } else if (rev
== 3 || rev
== 4 || rev
== 5) {
497 /* TODO: DLLP Power Management Threshold */
498 ssb_pcicore_serdes_workaround(pc
);
500 } else if (rev
== 7) {
501 /* TODO: No PLL down */
505 /* Miscellaneous Configuration Fixup */
506 tmp
= pcicore_read16(pc
, SSB_PCICORE_SPROM(5));
508 pcicore_write16(pc
, SSB_PCICORE_SPROM(5),
513 /**************************************************
514 * Generic and Clientmode operation code.
515 **************************************************/
517 static void ssb_pcicore_init_clientmode(struct ssb_pcicore
*pc
)
519 struct ssb_device
*pdev
= pc
->dev
;
520 struct ssb_bus
*bus
= pdev
->bus
;
522 if (bus
->bustype
== SSB_BUSTYPE_PCI
)
523 ssb_pcicore_fix_sprom_core_index(pc
);
525 /* Disable PCI interrupts. */
526 ssb_write32(pdev
, SSB_INTVEC
, 0);
528 /* Additional PCIe always once-executed workarounds */
529 if (pc
->dev
->id
.coreid
== SSB_DEV_PCIE
) {
530 ssb_pcicore_serdes_workaround(pc
);
532 /* TODO: Clock Request Update */
536 void ssb_pcicore_init(struct ssb_pcicore
*pc
)
538 struct ssb_device
*dev
= pc
->dev
;
542 if (!ssb_device_is_enabled(dev
))
543 ssb_device_enable(dev
, 0);
545 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
546 pc
->hostmode
= pcicore_is_in_hostmode(pc
);
548 ssb_pcicore_init_hostmode(pc
);
549 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
551 ssb_pcicore_init_clientmode(pc
);
554 static u32
ssb_pcie_read(struct ssb_pcicore
*pc
, u32 address
)
556 pcicore_write32(pc
, 0x130, address
);
557 return pcicore_read32(pc
, 0x134);
560 static void ssb_pcie_write(struct ssb_pcicore
*pc
, u32 address
, u32 data
)
562 pcicore_write32(pc
, 0x130, address
);
563 pcicore_write32(pc
, 0x134, data
);
566 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore
*pc
, u8 phy
)
568 const u16 mdio_control
= 0x128;
569 const u16 mdio_data
= 0x12C;
573 v
= (1 << 30); /* Start of Transaction */
574 v
|= (1 << 28); /* Write Transaction */
575 v
|= (1 << 17); /* Turnaround */
578 pcicore_write32(pc
, mdio_data
, v
);
581 for (i
= 0; i
< 200; i
++) {
582 v
= pcicore_read32(pc
, mdio_control
);
583 if (v
& 0x100 /* Trans complete */)
589 static u16
ssb_pcie_mdio_read(struct ssb_pcicore
*pc
, u8 device
, u8 address
)
591 const u16 mdio_control
= 0x128;
592 const u16 mdio_data
= 0x12C;
593 int max_retries
= 10;
598 v
= 0x80; /* Enable Preamble Sequence */
599 v
|= 0x2; /* MDIO Clock Divisor */
600 pcicore_write32(pc
, mdio_control
, v
);
602 if (pc
->dev
->id
.revision
>= 10) {
604 ssb_pcie_mdio_set_phy(pc
, device
);
607 v
= (1 << 30); /* Start of Transaction */
608 v
|= (1 << 29); /* Read Transaction */
609 v
|= (1 << 17); /* Turnaround */
610 if (pc
->dev
->id
.revision
< 10)
611 v
|= (u32
)device
<< 22;
612 v
|= (u32
)address
<< 18;
613 pcicore_write32(pc
, mdio_data
, v
);
614 /* Wait for the device to complete the transaction */
616 for (i
= 0; i
< max_retries
; i
++) {
617 v
= pcicore_read32(pc
, mdio_control
);
618 if (v
& 0x100 /* Trans complete */) {
620 ret
= pcicore_read32(pc
, mdio_data
);
625 pcicore_write32(pc
, mdio_control
, 0);
629 static void ssb_pcie_mdio_write(struct ssb_pcicore
*pc
, u8 device
,
630 u8 address
, u16 data
)
632 const u16 mdio_control
= 0x128;
633 const u16 mdio_data
= 0x12C;
634 int max_retries
= 10;
638 v
= 0x80; /* Enable Preamble Sequence */
639 v
|= 0x2; /* MDIO Clock Divisor */
640 pcicore_write32(pc
, mdio_control
, v
);
642 if (pc
->dev
->id
.revision
>= 10) {
644 ssb_pcie_mdio_set_phy(pc
, device
);
647 v
= (1 << 30); /* Start of Transaction */
648 v
|= (1 << 28); /* Write Transaction */
649 v
|= (1 << 17); /* Turnaround */
650 if (pc
->dev
->id
.revision
< 10)
651 v
|= (u32
)device
<< 22;
652 v
|= (u32
)address
<< 18;
654 pcicore_write32(pc
, mdio_data
, v
);
655 /* Wait for the device to complete the transaction */
657 for (i
= 0; i
< max_retries
; i
++) {
658 v
= pcicore_read32(pc
, mdio_control
);
659 if (v
& 0x100 /* Trans complete */)
663 pcicore_write32(pc
, mdio_control
, 0);
666 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore
*pc
,
667 struct ssb_device
*dev
)
669 struct ssb_device
*pdev
= pc
->dev
;
674 if (dev
->bus
->bustype
!= SSB_BUSTYPE_PCI
) {
675 /* This SSB device is not on a PCI host-bus. So the IRQs are
676 * not routed through the PCI core.
677 * So we must not enable routing through the PCI core. */
685 might_sleep_if(pdev
->id
.coreid
!= SSB_DEV_PCI
);
687 /* Enable interrupts for this device. */
688 if ((pdev
->id
.revision
>= 6) || (pdev
->id
.coreid
== SSB_DEV_PCIE
)) {
691 /* Calculate the "coremask" for the device. */
692 coremask
= (1 << dev
->core_index
);
694 SSB_WARN_ON(bus
->bustype
!= SSB_BUSTYPE_PCI
);
695 err
= pci_read_config_dword(bus
->host_pci
, SSB_PCI_IRQMASK
, &tmp
);
698 tmp
|= coremask
<< 8;
699 err
= pci_write_config_dword(bus
->host_pci
, SSB_PCI_IRQMASK
, tmp
);
705 intvec
= ssb_read32(pdev
, SSB_INTVEC
);
706 tmp
= ssb_read32(dev
, SSB_TPSFLAG
);
707 tmp
&= SSB_TPSFLAG_BPFLAG
;
708 intvec
|= (1 << tmp
);
709 ssb_write32(pdev
, SSB_INTVEC
, intvec
);
712 /* Setup PCIcore operation. */
715 if (pdev
->id
.coreid
== SSB_DEV_PCI
) {
716 ssb_pcicore_pci_setup_workarounds(pc
);
718 WARN_ON(pdev
->id
.coreid
!= SSB_DEV_PCIE
);
719 ssb_pcicore_pcie_setup_workarounds(pc
);
725 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable
);