drivers/watchdog/iTCO_wdt.c

   1 /*
   2  *      intel TCO Watchdog Driver
   3  *
   4  *      (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  12  *      provide warranty for any of this software. This material is
  13  *      provided "AS-IS" and at no charge.
  14  *
  15  *      The TCO watchdog is implemented in the following I/O controller hubs:
  16  *      (See the intel documentation on http://developer.intel.com.)
  17  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  18  *      document number 290687-002, 298242-027: 82801BA (ICH2)
  19  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
  20  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  21  *      document number 290744-001, 290745-025: 82801DB (ICH4)
  22  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  23  *      document number 273599-001, 273645-002: 82801E (C-ICH)
  24  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  25  *      document number 300641-004, 300884-013: 6300ESB
  26  *      document number 301473-002, 301474-026: 82801F (ICH6)
  27  *      document number 313082-001, 313075-006: 631xESB, 632xESB
  28  *      document number 307013-003, 307014-024: 82801G (ICH7)
  29  *      document number 322896-001, 322897-001: NM10
  30  *      document number 313056-003, 313057-017: 82801H (ICH8)
  31  *      document number 316972-004, 316973-012: 82801I (ICH9)
  32  *      document number 319973-002, 319974-002: 82801J (ICH10)
  33  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  34  *      document number 320066-003, 320257-008: EP80597 (IICH)
  35  *      document number 324645-001, 324646-001: Cougar Point (CPT)
  36  *      document number TBD                   : Patsburg (PBG)
  37  *      document number TBD                   : DH89xxCC
  38  *      document number TBD                   : Panther Point
  39  *      document number TBD                   : Lynx Point
  40  *      document number TBD                   : Lynx Point-LP
  41  */
  42
  43 /*
  44  *      Includes, defines, variables, module parameters, ...
  45  */
  46
  47 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  48
  49 /* Module and version information */
  50 #define DRV_NAME        "iTCO_wdt"
  51 #define DRV_VERSION     "1.10"
  52
  53 /* Includes */
  54 #include <linux/module.h>               /* For module specific items */
  55 #include <linux/moduleparam.h>          /* For new moduleparam's */
  56 #include <linux/types.h>                /* For standard types (like size_t) */
  57 #include <linux/errno.h>                /* For the -ENODEV/... values */
  58 #include <linux/kernel.h>               /* For printk/panic/... */
  59 #include <linux/watchdog.h>             /* For the watchdog specific items */
  60 #include <linux/init.h>                 /* For __init/__exit/... */
  61 #include <linux/fs.h>                   /* For file operations */
  62 #include <linux/platform_device.h>      /* For platform_driver framework */
  63 #include <linux/pci.h>                  /* For pci functions */
  64 #include <linux/ioport.h>               /* For io-port access */
  65 #include <linux/spinlock.h>             /* For spin_lock/spin_unlock/... */
  66 #include <linux/uaccess.h>              /* For copy_to_user/put_user/... */
  67 #include <linux/io.h>                   /* For inb/outb/... */
  68 #include <linux/mfd/core.h>
  69 #include <linux/mfd/lpc_ich.h>
  70
  71 #include "iTCO_vendor.h"
  72
  73 /* Address definitions for the TCO */
  74 /* TCO base address */
  75 #define TCOBASE         (iTCO_wdt_private.tco_res->start)
  76 /* SMI Control and Enable Register */
  77 #define SMI_EN          (iTCO_wdt_private.smi_res->start)
  78
  79 #define TCO_RLD         (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
  80 #define TCOv1_TMR       (TCOBASE + 0x01) /* TCOv1 Timer Initial Value   */
  81 #define TCO_DAT_IN      (TCOBASE + 0x02) /* TCO Data In Register        */
  82 #define TCO_DAT_OUT     (TCOBASE + 0x03) /* TCO Data Out Register       */
  83 #define TCO1_STS        (TCOBASE + 0x04) /* TCO1 Status Register        */
  84 #define TCO2_STS        (TCOBASE + 0x06) /* TCO2 Status Register        */
  85 #define TCO1_CNT        (TCOBASE + 0x08) /* TCO1 Control Register       */
  86 #define TCO2_CNT        (TCOBASE + 0x0a) /* TCO2 Control Register       */
  87 #define TCOv2_TMR       (TCOBASE + 0x12) /* TCOv2 Timer Initial Value   */
  88
  89 /* internal variables */
  90 static struct {         /* this is private data for the iTCO_wdt device */
  91         /* TCO version/generation */
  92         unsigned int iTCO_version;
  93         struct resource *tco_res;
  94         struct resource *smi_res;
  95         struct resource *gcs_res;
  96         /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
  97         unsigned long __iomem *gcs;
  98         /* the lock for io operations */
  99         spinlock_t io_lock;
 100         struct platform_device *dev;
 101         /* the PCI-device */
 102         struct pci_dev *pdev;
 103 } iTCO_wdt_private;
 104
 105 /* module parameters */
 106 #define WATCHDOG_TIMEOUT 30     /* 30 sec default heartbeat */
 107 static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
 108 module_param(heartbeat, int, 0);
 109 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
 110         "5..76 (TCO v1) or 3..614 (TCO v2), default="
 111                                 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
 112
 113 static bool nowayout = WATCHDOG_NOWAYOUT;
 114 module_param(nowayout, bool, 0);
 115 MODULE_PARM_DESC(nowayout,
 116         "Watchdog cannot be stopped once started (default="
 117                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 118
 119 static int turn_SMI_watchdog_clear_off = 1;
 120 module_param(turn_SMI_watchdog_clear_off, int, 0);
 121 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
 122         "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
 123
 124 /*
 125  * Some TCO specific functions
 126  */
 127
 128 static inline unsigned int seconds_to_ticks(int seconds)
 129 {
 130         /* the internal timer is stored as ticks which decrement
 131          * every 0.6 seconds */
 132         return (seconds * 10) / 6;
 133 }
 134
 135 static void iTCO_wdt_set_NO_REBOOT_bit(void)
 136 {
 137         u32 val32;
 138
 139         /* Set the NO_REBOOT bit: this disables reboots */
 140         if (iTCO_wdt_private.iTCO_version == 2) {
 141                 val32 = readl(iTCO_wdt_private.gcs);
 142                 val32 |= 0x00000020;
 143                 writel(val32, iTCO_wdt_private.gcs);
 144         } else if (iTCO_wdt_private.iTCO_version == 1) {
 145                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 146                 val32 |= 0x00000002;
 147                 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
 148         }
 149 }
 150
 151 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
 152 {
 153         int ret = 0;
 154         u32 val32;
 155
 156         /* Unset the NO_REBOOT bit: this enables reboots */
 157         if (iTCO_wdt_private.iTCO_version == 2) {
 158                 val32 = readl(iTCO_wdt_private.gcs);
 159                 val32 &= 0xffffffdf;
 160                 writel(val32, iTCO_wdt_private.gcs);
 161
 162                 val32 = readl(iTCO_wdt_private.gcs);
 163                 if (val32 & 0x00000020)
 164                         ret = -EIO;
 165         } else if (iTCO_wdt_private.iTCO_version == 1) {
 166                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 167                 val32 &= 0xfffffffd;
 168                 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
 169
 170                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 171                 if (val32 & 0x00000002)
 172                         ret = -EIO;
 173         }
 174
 175         return ret; /* returns: 0 = OK, -EIO = Error */
 176 }
 177
 178 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
 179 {
 180         unsigned int val;
 181
 182         spin_lock(&iTCO_wdt_private.io_lock);
 183
 184         iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
 185
 186         /* disable chipset's NO_REBOOT bit */
 187         if (iTCO_wdt_unset_NO_REBOOT_bit()) {
 188                 spin_unlock(&iTCO_wdt_private.io_lock);
 189                 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
 190                 return -EIO;
 191         }
 192
 193         /* Force the timer to its reload value by writing to the TCO_RLD
 194            register */
 195         if (iTCO_wdt_private.iTCO_version == 2)
 196                 outw(0x01, TCO_RLD);
 197         else if (iTCO_wdt_private.iTCO_version == 1)
 198                 outb(0x01, TCO_RLD);
 199
 200         /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
 201         val = inw(TCO1_CNT);
 202         val &= 0xf7ff;
 203         outw(val, TCO1_CNT);
 204         val = inw(TCO1_CNT);
 205         spin_unlock(&iTCO_wdt_private.io_lock);
 206
 207         if (val & 0x0800)
 208                 return -1;
 209         return 0;
 210 }
 211
 212 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
 213 {
 214         unsigned int val;
 215
 216         spin_lock(&iTCO_wdt_private.io_lock);
 217
 218         iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
 219
 220         /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
 221         val = inw(TCO1_CNT);
 222         val |= 0x0800;
 223         outw(val, TCO1_CNT);
 224         val = inw(TCO1_CNT);
 225
 226         /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
 227         iTCO_wdt_set_NO_REBOOT_bit();
 228
 229         spin_unlock(&iTCO_wdt_private.io_lock);
 230
 231         if ((val & 0x0800) == 0)
 232                 return -1;
 233         return 0;
 234 }
 235
 236 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
 237 {
 238         spin_lock(&iTCO_wdt_private.io_lock);
 239
 240         iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
 241
 242         /* Reload the timer by writing to the TCO Timer Counter register */
 243         if (iTCO_wdt_private.iTCO_version == 2)
 244                 outw(0x01, TCO_RLD);
 245         else if (iTCO_wdt_private.iTCO_version == 1) {
 246                 /* Reset the timeout status bit so that the timer
 247                  * needs to count down twice again before rebooting */
 248                 outw(0x0008, TCO1_STS); /* write 1 to clear bit */
 249
 250                 outb(0x01, TCO_RLD);
 251         }
 252
 253         spin_unlock(&iTCO_wdt_private.io_lock);
 254         return 0;
 255 }
 256
 257 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
 258 {
 259         unsigned int val16;
 260         unsigned char val8;
 261         unsigned int tmrval;
 262
 263         tmrval = seconds_to_ticks(t);
 264
 265         /* For TCO v1 the timer counts down twice before rebooting */
 266         if (iTCO_wdt_private.iTCO_version == 1)
 267                 tmrval /= 2;
 268
 269         /* from the specs: */
 270         /* "Values of 0h-3h are ignored and should not be attempted" */
 271         if (tmrval < 0x04)
 272                 return -EINVAL;
 273         if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
 274             ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
 275                 return -EINVAL;
 276
 277         iTCO_vendor_pre_set_heartbeat(tmrval);
 278
 279         /* Write new heartbeat to watchdog */
 280         if (iTCO_wdt_private.iTCO_version == 2) {
 281                 spin_lock(&iTCO_wdt_private.io_lock);
 282                 val16 = inw(TCOv2_TMR);
 283                 val16 &= 0xfc00;
 284                 val16 |= tmrval;
 285                 outw(val16, TCOv2_TMR);
 286                 val16 = inw(TCOv2_TMR);
 287                 spin_unlock(&iTCO_wdt_private.io_lock);
 288
 289                 if ((val16 & 0x3ff) != tmrval)
 290                         return -EINVAL;
 291         } else if (iTCO_wdt_private.iTCO_version == 1) {
 292                 spin_lock(&iTCO_wdt_private.io_lock);
 293                 val8 = inb(TCOv1_TMR);
 294                 val8 &= 0xc0;
 295                 val8 |= (tmrval & 0xff);
 296                 outb(val8, TCOv1_TMR);
 297                 val8 = inb(TCOv1_TMR);
 298                 spin_unlock(&iTCO_wdt_private.io_lock);
 299
 300                 if ((val8 & 0x3f) != tmrval)
 301                         return -EINVAL;
 302         }
 303
 304         wd_dev->timeout = t;
 305         return 0;
 306 }
 307
 308 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
 309 {
 310         unsigned int val16;
 311         unsigned char val8;
 312         unsigned int time_left = 0;
 313
 314         /* read the TCO Timer */
 315         if (iTCO_wdt_private.iTCO_version == 2) {
 316                 spin_lock(&iTCO_wdt_private.io_lock);
 317                 val16 = inw(TCO_RLD);
 318                 val16 &= 0x3ff;
 319                 spin_unlock(&iTCO_wdt_private.io_lock);
 320
 321                 time_left = (val16 * 6) / 10;
 322         } else if (iTCO_wdt_private.iTCO_version == 1) {
 323                 spin_lock(&iTCO_wdt_private.io_lock);
 324                 val8 = inb(TCO_RLD);
 325                 val8 &= 0x3f;
 326                 if (!(inw(TCO1_STS) & 0x0008))
 327                         val8 += (inb(TCOv1_TMR) & 0x3f);
 328                 spin_unlock(&iTCO_wdt_private.io_lock);
 329
 330                 time_left = (val8 * 6) / 10;
 331         }
 332         return time_left;
 333 }
 334
 335 /*
 336  *      Kernel Interfaces
 337  */
 338
 339 static const struct watchdog_info ident = {
 340         .options =              WDIOF_SETTIMEOUT |
 341                                 WDIOF_KEEPALIVEPING |
 342                                 WDIOF_MAGICCLOSE,
 343         .firmware_version =     0,
 344         .identity =             DRV_NAME,
 345 };
 346
 347 static const struct watchdog_ops iTCO_wdt_ops = {
 348         .owner =                THIS_MODULE,
 349         .start =                iTCO_wdt_start,
 350         .stop =                 iTCO_wdt_stop,
 351         .ping =                 iTCO_wdt_ping,
 352         .set_timeout =          iTCO_wdt_set_timeout,
 353         .get_timeleft =         iTCO_wdt_get_timeleft,
 354 };
 355
 356 static struct watchdog_device iTCO_wdt_watchdog_dev = {
 357         .info =         &ident,
 358         .ops =          &iTCO_wdt_ops,
 359 };
 360
 361 /*
 362  *      Init & exit routines
 363  */
 364
 365 static void iTCO_wdt_cleanup(void)
 366 {
 367         /* Stop the timer before we leave */
 368         if (!nowayout)
 369                 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
 370
 371         /* Deregister */
 372         watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
 373
 374         /* release resources */
 375         release_region(iTCO_wdt_private.tco_res->start,
 376                         resource_size(iTCO_wdt_private.tco_res));
 377         release_region(iTCO_wdt_private.smi_res->start,
 378                         resource_size(iTCO_wdt_private.smi_res));
 379         if (iTCO_wdt_private.iTCO_version == 2) {
 380                 iounmap(iTCO_wdt_private.gcs);
 381                 release_mem_region(iTCO_wdt_private.gcs_res->start,
 382                                 resource_size(iTCO_wdt_private.gcs_res));
 383         }
 384
 385         iTCO_wdt_private.tco_res = NULL;
 386         iTCO_wdt_private.smi_res = NULL;
 387         iTCO_wdt_private.gcs_res = NULL;
 388         iTCO_wdt_private.gcs = NULL;
 389 }
 390
 391 static int iTCO_wdt_probe(struct platform_device *dev)
 392 {
 393         int ret = -ENODEV;
 394         unsigned long val32;
 395         struct lpc_ich_info *ich_info = dev_get_platdata(&dev->dev);
 396
 397         if (!ich_info)
 398                 goto out;
 399
 400         spin_lock_init(&iTCO_wdt_private.io_lock);
 401
 402         iTCO_wdt_private.tco_res =
 403                 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
 404         if (!iTCO_wdt_private.tco_res)
 405                 goto out;
 406
 407         iTCO_wdt_private.smi_res =
 408                 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
 409         if (!iTCO_wdt_private.smi_res)
 410                 goto out;
 411
 412         iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
 413         iTCO_wdt_private.dev = dev;
 414         iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
 415
 416         /*
 417          * Get the Memory-Mapped GCS register, we need it for the
 418          * NO_REBOOT flag (TCO v2).
 419          */
 420         if (iTCO_wdt_private.iTCO_version == 2) {
 421                 iTCO_wdt_private.gcs_res = platform_get_resource(dev,
 422                                                         IORESOURCE_MEM,
 423                                                         ICH_RES_MEM_GCS);
 424
 425                 if (!iTCO_wdt_private.gcs_res)
 426                         goto out;
 427
 428                 if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
 429                         resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
 430                         ret = -EBUSY;
 431                         goto out;
 432                 }
 433                 iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
 434                         resource_size(iTCO_wdt_private.gcs_res));
 435                 if (!iTCO_wdt_private.gcs) {
 436                         ret = -EIO;
 437                         goto unreg_gcs;
 438                 }
 439         }
 440
 441         /* Check chipset's NO_REBOOT bit */
 442         if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
 443                 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
 444                 ret = -ENODEV;  /* Cannot reset NO_REBOOT bit */
 445                 goto unmap_gcs;
 446         }
 447
 448         /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
 449         iTCO_wdt_set_NO_REBOOT_bit();
 450
 451         /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
 452         if (!request_region(iTCO_wdt_private.smi_res->start,
 453                         resource_size(iTCO_wdt_private.smi_res), dev->name)) {
 454                 pr_err("I/O address 0x%04llx already in use, device disabled\n",
 455                        (u64)SMI_EN);
 456                 ret = -EBUSY;
 457                 goto unmap_gcs;
 458         }
 459         if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
 460                 /*
 461                  * Bit 13: TCO_EN -> 0
 462                  * Disables TCO logic generating an SMI#
 463                  */
 464                 val32 = inl(SMI_EN);
 465                 val32 &= 0xffffdfff;    /* Turn off SMI clearing watchdog */
 466                 outl(val32, SMI_EN);
 467         }
 468
 469         if (!request_region(iTCO_wdt_private.tco_res->start,
 470                         resource_size(iTCO_wdt_private.tco_res), dev->name)) {
 471                 pr_err("I/O address 0x%04llx already in use, device disabled\n",
 472                        (u64)TCOBASE);
 473                 ret = -EBUSY;
 474                 goto unreg_smi;
 475         }
 476
 477         pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
 478                 ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);
 479
 480         /* Clear out the (probably old) status */
 481         outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
 482         outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
 483         outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
 484
 485         iTCO_wdt_watchdog_dev.bootstatus = 0;
 486         iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
 487         watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
 488         iTCO_wdt_watchdog_dev.parent = dev->dev.parent;
 489
 490         /* Make sure the watchdog is not running */
 491         iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
 492
 493         /* Check that the heartbeat value is within it's range;
 494            if not reset to the default */
 495         if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
 496                 iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
 497                 pr_info("timeout value out of range, using %d\n",
 498                         WATCHDOG_TIMEOUT);
 499         }
 500
 501         ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
 502         if (ret != 0) {
 503                 pr_err("cannot register watchdog device (err=%d)\n", ret);
 504                 goto unreg_tco;
 505         }
 506
 507         pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
 508                 heartbeat, nowayout);
 509
 510         return 0;
 511
 512 unreg_tco:
 513         release_region(iTCO_wdt_private.tco_res->start,
 514                         resource_size(iTCO_wdt_private.tco_res));
 515 unreg_smi:
 516         release_region(iTCO_wdt_private.smi_res->start,
 517                         resource_size(iTCO_wdt_private.smi_res));
 518 unmap_gcs:
 519         if (iTCO_wdt_private.iTCO_version == 2)
 520                 iounmap(iTCO_wdt_private.gcs);
 521 unreg_gcs:
 522         if (iTCO_wdt_private.iTCO_version == 2)
 523                 release_mem_region(iTCO_wdt_private.gcs_res->start,
 524                                 resource_size(iTCO_wdt_private.gcs_res));
 525 out:
 526         iTCO_wdt_private.tco_res = NULL;
 527         iTCO_wdt_private.smi_res = NULL;
 528         iTCO_wdt_private.gcs_res = NULL;
 529         iTCO_wdt_private.gcs = NULL;
 530
 531         return ret;
 532 }
 533
 534 static int iTCO_wdt_remove(struct platform_device *dev)
 535 {
 536         if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
 537                 iTCO_wdt_cleanup();
 538
 539         return 0;
 540 }
 541
 542 static void iTCO_wdt_shutdown(struct platform_device *dev)
 543 {
 544         iTCO_wdt_stop(NULL);
 545 }
 546
 547 static struct platform_driver iTCO_wdt_driver = {
 548         .probe          = iTCO_wdt_probe,
 549         .remove         = iTCO_wdt_remove,
 550         .shutdown       = iTCO_wdt_shutdown,
 551         .driver         = {
 552                 .owner  = THIS_MODULE,
 553                 .name   = DRV_NAME,
 554         },
 555 };
 556
 557 static int __init iTCO_wdt_init_module(void)
 558 {
 559         int err;
 560
 561         pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
 562
 563         err = platform_driver_register(&iTCO_wdt_driver);
 564         if (err)
 565                 return err;
 566
 567         return 0;
 568 }
 569
 570 static void __exit iTCO_wdt_cleanup_module(void)
 571 {
 572         platform_driver_unregister(&iTCO_wdt_driver);
 573         pr_info("Watchdog Module Unloaded\n");
 574 }
 575
 576 module_init(iTCO_wdt_init_module);
 577 module_exit(iTCO_wdt_cleanup_module);
 578
 579 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
 580 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
 581 MODULE_VERSION(DRV_VERSION);
 582 MODULE_LICENSE("GPL");
 583 MODULE_ALIAS("platform:" DRV_NAME);