arch/arm/boot/dts/tegra114.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra114";
   5         interrupt-parent = <&gic>;
   6
   7         gic: interrupt-controller {
   8                 compatible = "arm,cortex-a15-gic";
   9                 #interrupt-cells = <3>;
  10                 interrupt-controller;
  11                 reg = <0x50041000 0x1000>,
  12                       <0x50042000 0x1000>,
  13                       <0x50044000 0x2000>,
  14                       <0x50046000 0x2000>;
  15                 interrupts = <1 9 0xf04>;
  16         };
  17
  18         timer@60005000 {
  19                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
  20                 reg = <0x60005000 0x400>;
  21                 interrupts = <0 0 0x04
  22                               0 1 0x04
  23                               0 41 0x04
  24                               0 42 0x04
  25                               0 121 0x04
  26                               0 122 0x04>;
  27         };
  28
  29         tegra_car: clock {
  30                 compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
  31                 reg = <0x60006000 0x1000>;
  32                 #clock-cells = <1>;
  33         };
  34
  35         ahb: ahb {
  36                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
  37                 reg = <0x6000c004 0x14c>;
  38         };
  39
  40         gpio: gpio {
  41                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
  42                 reg = <0x6000d000 0x1000>;
  43                 interrupts = <0 32 0x04
  44                               0 33 0x04
  45                               0 34 0x04
  46                               0 35 0x04
  47                               0 55 0x04
  48                               0 87 0x04
  49                               0 89 0x04
  50                               0 125 0x04>;
  51                 #gpio-cells = <2>;
  52                 gpio-controller;
  53                 #interrupt-cells = <2>;
  54                 interrupt-controller;
  55         };
  56
  57         pinmux: pinmux {
  58                 compatible = "nvidia,tegra114-pinmux";
  59                 reg = <0x70000868 0x148         /* Pad control registers */
  60                        0x70003000 0x40c>;       /* Mux registers */
  61         };
  62
  63         serial@70006000 {
  64                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  65                 reg = <0x70006000 0x40>;
  66                 reg-shift = <2>;
  67                 interrupts = <0 36 0x04>;
  68                 status = "disabled";
  69         };
  70
  71         serial@70006040 {
  72                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  73                 reg = <0x70006040 0x40>;
  74                 reg-shift = <2>;
  75                 interrupts = <0 37 0x04>;
  76                 status = "disabled";
  77         };
  78
  79         serial@70006200 {
  80                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  81                 reg = <0x70006200 0x100>;
  82                 reg-shift = <2>;
  83                 interrupts = <0 46 0x04>;
  84                 status = "disabled";
  85         };
  86
  87         serial@70006300 {
  88                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  89                 reg = <0x70006300 0x100>;
  90                 reg-shift = <2>;
  91                 interrupts = <0 90 0x04>;
  92                 status = "disabled";
  93         };
  94
  95         rtc {
  96                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
  97                 reg = <0x7000e000 0x100>;
  98                 interrupts = <0 2 0x04>;
  99         };
 100
 101         pmc {
 102                 compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
 103                 reg = <0x7000e400 0x400>;
 104         };
 105
 106         iommu {
 107                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 108                 reg = <0x7000f010 0x02c
 109                        0x7000f1f0 0x010
 110                        0x7000f228 0x074>;
 111                 nvidia,#asids = <4>;
 112                 dma-window = <0 0x40000000>;
 113                 nvidia,swgroups = <0x18659fe>;
 114                 nvidia,ahb = <&ahb>;
 115         };
 116
 117         cpus {
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120
 121                 cpu@0 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a15";
 124                         reg = <0>;
 125                 };
 126
 127                 cpu@1 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a15";
 130                         reg = <1>;
 131                 };
 132
 133                 cpu@2 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a15";
 136                         reg = <2>;
 137                 };
 138
 139                 cpu@3 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a15";
 142                         reg = <3>;
 143                 };
 144         };
 145
 146         timer {
 147                 compatible = "arm,armv7-timer";
 148                 interrupts = <1 13 0xf08>,
 149                              <1 14 0xf08>,
 150                              <1 11 0xf08>,
 151                              <1 10 0xf08>;
 152         };
 153 };