| blob | dfe371ec2749843cef7726f5fb5e75d55e670456 |
1 /*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
6 *
7 * HBI-0249A
8 */
10 /dts-v1/;
12 / {
13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 chosen { };
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <0>;
40 };
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <1>;
46 };
48 cpu2: cpu@2 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a7";
51 reg = <0x100>;
52 };
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a7";
57 reg = <0x101>;
58 };
60 cpu4: cpu@4 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a7";
63 reg = <0x102>;
64 };
65 };
67 memory@80000000 {
68 device_type = "memory";
69 reg = <0 0x80000000 0 0x40000000>;
70 };
72 wdt@2a490000 {
73 compatible = "arm,sp805", "arm,primecell";
74 reg = <0 0x2a490000 0 0x1000>;
75 interrupts = <0 98 4>;
76 clocks = <&oscclk6a>, <&oscclk6a>;
77 clock-names = "wdogclk", "apb_pclk";
78 };
80 hdlcd@2b000000 {
81 compatible = "arm,hdlcd";
82 reg = <0 0x2b000000 0 0x1000>;
83 interrupts = <0 85 4>;
84 clocks = <&oscclk5>;
85 clock-names = "pxlclk";
86 };
88 memory-controller@2b0a0000 {
89 compatible = "arm,pl341", "arm,primecell";
90 reg = <0 0x2b0a0000 0 0x1000>;
91 clocks = <&oscclk6a>;
92 clock-names = "apb_pclk";
93 };
95 gic: interrupt-controller@2c001000 {
96 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
97 #interrupt-cells = <3>;
98 #address-cells = <0>;
99 interrupt-controller;
100 reg = <0 0x2c001000 0 0x1000>,
101 <0 0x2c002000 0 0x1000>,
102 <0 0x2c004000 0 0x2000>,
103 <0 0x2c006000 0 0x2000>;
104 interrupts = <1 9 0xf04>;
105 };
107 memory-controller@7ffd0000 {
108 compatible = "arm,pl354", "arm,primecell";
109 reg = <0 0x7ffd0000 0 0x1000>;
110 interrupts = <0 86 4>,
111 <0 87 4>;
112 clocks = <&oscclk6a>;
113 clock-names = "apb_pclk";
114 };
116 dma@7ff00000 {
117 compatible = "arm,pl330", "arm,primecell";
118 reg = <0 0x7ff00000 0 0x1000>;
119 interrupts = <0 92 4>,
120 <0 88 4>,
121 <0 89 4>,
122 <0 90 4>,
123 <0 91 4>;
124 clocks = <&oscclk6a>;
125 clock-names = "apb_pclk";
126 };
128 timer {
129 compatible = "arm,armv7-timer";
130 interrupts = <1 13 0xf08>,
131 <1 14 0xf08>,
132 <1 11 0xf08>,
133 <1 10 0xf08>;
134 };
136 pmu {
137 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
138 interrupts = <0 68 4>,
139 <0 69 4>;
140 };
142 oscclk6a: oscclk6a {
143 /* Reference 24MHz clock */
144 compatible = "fixed-clock";
145 #clock-cells = <0>;
146 clock-frequency = <24000000>;
147 clock-output-names = "oscclk6a";
148 };
150 dcc {
151 compatible = "arm,vexpress,config-bus";
152 arm,vexpress,config-bridge = <&v2m_sysreg>;
154 osc@0 {
155 /* A15 PLL 0 reference clock */
156 compatible = "arm,vexpress-osc";
157 arm,vexpress-sysreg,func = <1 0>;
158 freq-range = <17000000 50000000>;
159 #clock-cells = <0>;
160 clock-output-names = "oscclk0";
161 };
163 osc@1 {
164 /* A15 PLL 1 reference clock */
165 compatible = "arm,vexpress-osc";
166 arm,vexpress-sysreg,func = <1 1>;
167 freq-range = <17000000 50000000>;
168 #clock-cells = <0>;
169 clock-output-names = "oscclk1";
170 };
172 osc@2 {
173 /* A7 PLL 0 reference clock */
174 compatible = "arm,vexpress-osc";
175 arm,vexpress-sysreg,func = <1 2>;
176 freq-range = <17000000 50000000>;
177 #clock-cells = <0>;
178 clock-output-names = "oscclk2";
179 };
181 osc@3 {
182 /* A7 PLL 1 reference clock */
183 compatible = "arm,vexpress-osc";
184 arm,vexpress-sysreg,func = <1 3>;
185 freq-range = <17000000 50000000>;
186 #clock-cells = <0>;
187 clock-output-names = "oscclk3";
188 };
190 osc@4 {
191 /* External AXI master clock */
192 compatible = "arm,vexpress-osc";
193 arm,vexpress-sysreg,func = <1 4>;
194 freq-range = <20000000 40000000>;
195 #clock-cells = <0>;
196 clock-output-names = "oscclk4";
197 };
199 oscclk5: osc@5 {
200 /* HDLCD PLL reference clock */
201 compatible = "arm,vexpress-osc";
202 arm,vexpress-sysreg,func = <1 5>;
203 freq-range = <23750000 165000000>;
204 #clock-cells = <0>;
205 clock-output-names = "oscclk5";
206 };
208 smbclk: osc@6 {
209 /* Static memory controller clock */
210 compatible = "arm,vexpress-osc";
211 arm,vexpress-sysreg,func = <1 6>;
212 freq-range = <20000000 40000000>;
213 #clock-cells = <0>;
214 clock-output-names = "oscclk6";
215 };
217 osc@7 {
218 /* SYS PLL reference clock */
219 compatible = "arm,vexpress-osc";
220 arm,vexpress-sysreg,func = <1 7>;
221 freq-range = <17000000 50000000>;
222 #clock-cells = <0>;
223 clock-output-names = "oscclk7";
224 };
226 osc@8 {
227 /* DDR2 PLL reference clock */
228 compatible = "arm,vexpress-osc";
229 arm,vexpress-sysreg,func = <1 8>;
230 freq-range = <20000000 50000000>;
231 #clock-cells = <0>;
232 clock-output-names = "oscclk8";
233 };
235 volt@0 {
236 /* A15 CPU core voltage */
237 compatible = "arm,vexpress-volt";
238 arm,vexpress-sysreg,func = <2 0>;
239 regulator-name = "A15 Vcore";
240 regulator-min-microvolt = <800000>;
241 regulator-max-microvolt = <1050000>;
242 regulator-always-on;
243 label = "A15 Vcore";
244 };
246 volt@1 {
247 /* A7 CPU core voltage */
248 compatible = "arm,vexpress-volt";
249 arm,vexpress-sysreg,func = <2 1>;
250 regulator-name = "A7 Vcore";
251 regulator-min-microvolt = <800000>;
252 regulator-max-microvolt = <1050000>;
253 regulator-always-on;
254 label = "A7 Vcore";
255 };
257 amp@0 {
258 /* Total current for the two A15 cores */
259 compatible = "arm,vexpress-amp";
260 arm,vexpress-sysreg,func = <3 0>;
261 label = "A15 Icore";
262 };
264 amp@1 {
265 /* Total current for the three A7 cores */
266 compatible = "arm,vexpress-amp";
267 arm,vexpress-sysreg,func = <3 1>;
268 label = "A7 Icore";
269 };
271 temp@0 {
272 /* DCC internal temperature */
273 compatible = "arm,vexpress-temp";
274 arm,vexpress-sysreg,func = <4 0>;
275 label = "DCC";
276 };
278 power@0 {
279 /* Total power for the two A15 cores */
280 compatible = "arm,vexpress-power";
281 arm,vexpress-sysreg,func = <12 0>;
282 label = "A15 Pcore";
283 };
284 power@1 {
285 /* Total power for the three A7 cores */
286 compatible = "arm,vexpress-power";
287 arm,vexpress-sysreg,func = <12 1>;
288 label = "A7 Pcore";
289 };
291 energy@0 {
292 /* Total energy for the two A15 cores */
293 compatible = "arm,vexpress-energy";
294 arm,vexpress-sysreg,func = <13 0>;
295 label = "A15 Jcore";
296 };
298 energy@2 {
299 /* Total energy for the three A7 cores */
300 compatible = "arm,vexpress-energy";
301 arm,vexpress-sysreg,func = <13 2>;
302 label = "A7 Jcore";
303 };
304 };
306 smb {
307 compatible = "simple-bus";
309 #address-cells = <2>;
310 #size-cells = <1>;
311 ranges = <0 0 0 0x08000000 0x04000000>,
312 <1 0 0 0x14000000 0x04000000>,
313 <2 0 0 0x18000000 0x04000000>,
314 <3 0 0 0x1c000000 0x04000000>,
315 <4 0 0 0x0c000000 0x04000000>,
316 <5 0 0 0x10000000 0x04000000>;
318 #interrupt-cells = <1>;
319 interrupt-map-mask = <0 0 63>;
320 interrupt-map = <0 0 0 &gic 0 0 4>,
321 <0 0 1 &gic 0 1 4>,
322 <0 0 2 &gic 0 2 4>,
323 <0 0 3 &gic 0 3 4>,
324 <0 0 4 &gic 0 4 4>,
325 <0 0 5 &gic 0 5 4>,
326 <0 0 6 &gic 0 6 4>,
327 <0 0 7 &gic 0 7 4>,
328 <0 0 8 &gic 0 8 4>,
329 <0 0 9 &gic 0 9 4>,
330 <0 0 10 &gic 0 10 4>,
331 <0 0 11 &gic 0 11 4>,
332 <0 0 12 &gic 0 12 4>,
333 <0 0 13 &gic 0 13 4>,
334 <0 0 14 &gic 0 14 4>,
335 <0 0 15 &gic 0 15 4>,
336 <0 0 16 &gic 0 16 4>,
337 <0 0 17 &gic 0 17 4>,
338 <0 0 18 &gic 0 18 4>,
339 <0 0 19 &gic 0 19 4>,
340 <0 0 20 &gic 0 20 4>,
341 <0 0 21 &gic 0 21 4>,
342 <0 0 22 &gic 0 22 4>,
343 <0 0 23 &gic 0 23 4>,
344 <0 0 24 &gic 0 24 4>,
345 <0 0 25 &gic 0 25 4>,
346 <0 0 26 &gic 0 26 4>,
347 <0 0 27 &gic 0 27 4>,
348 <0 0 28 &gic 0 28 4>,
349 <0 0 29 &gic 0 29 4>,
350 <0 0 30 &gic 0 30 4>,
351 <0 0 31 &gic 0 31 4>,
352 <0 0 32 &gic 0 32 4>,
353 <0 0 33 &gic 0 33 4>,
354 <0 0 34 &gic 0 34 4>,
355 <0 0 35 &gic 0 35 4>,
356 <0 0 36 &gic 0 36 4>,
357 <0 0 37 &gic 0 37 4>,
358 <0 0 38 &gic 0 38 4>,
359 <0 0 39 &gic 0 39 4>,
360 <0 0 40 &gic 0 40 4>,
361 <0 0 41 &gic 0 41 4>,
362 <0 0 42 &gic 0 42 4>;
364 /include/ "vexpress-v2m-rs1.dtsi"
365 };
366 };