arch/arm/boot/dts/wm8505.dtsi

   1 /*
   2  * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
   3  *
   4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "wm,wm8505";
  13
  14         cpus {
  15                 cpu@0 {
  16                         compatible = "arm,arm926ejs";
  17                 };
  18         };
  19
  20         soc {
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 compatible = "simple-bus";
  24                 ranges;
  25                 interrupt-parent = <&intc0>;
  26
  27                 intc0: interrupt-controller@d8140000 {
  28                         compatible = "via,vt8500-intc";
  29                         interrupt-controller;
  30                         reg = <0xd8140000 0x10000>;
  31                         #interrupt-cells = <1>;
  32                 };
  33
  34                 /* Secondary IC cascaded to intc0 */
  35                 intc1: interrupt-controller@d8150000 {
  36                         compatible = "via,vt8500-intc";
  37                         interrupt-controller;
  38                         #interrupt-cells = <1>;
  39                         reg = <0xD8150000 0x10000>;
  40                         interrupts = <56 57 58 59 60 61 62 63>;
  41                 };
  42
  43                 gpio: gpio-controller@d8110000 {
  44                         compatible = "wm,wm8505-gpio";
  45                         gpio-controller;
  46                         reg = <0xd8110000 0x10000>;
  47                         #gpio-cells = <3>;
  48                 };
  49
  50                 pmc@d8130000 {
  51                         compatible = "via,vt8500-pmc";
  52                         reg = <0xd8130000 0x1000>;
  53                         clocks {
  54                                 #address-cells = <1>;
  55                                 #size-cells = <0>;
  56
  57                                 ref24: ref24M {
  58                                         #clock-cells = <0>;
  59                                         compatible = "fixed-clock";
  60                                         clock-frequency = <24000000>;
  61                                 };
  62
  63                                 clkuart0: uart0 {
  64                                         #clock-cells = <0>;
  65                                         compatible = "via,vt8500-device-clock";
  66                                         clocks = <&ref24>;
  67                                         enable-reg = <0x250>;
  68                                         enable-bit = <1>;
  69                                 };
  70
  71                                 clkuart1: uart1 {
  72                                         #clock-cells = <0>;
  73                                         compatible = "via,vt8500-device-clock";
  74                                         clocks = <&ref24>;
  75                                         enable-reg = <0x250>;
  76                                         enable-bit = <2>;
  77                                 };
  78
  79                                 clkuart2: uart2 {
  80                                         #clock-cells = <0>;
  81                                         compatible = "via,vt8500-device-clock";
  82                                         clocks = <&ref24>;
  83                                         enable-reg = <0x250>;
  84                                         enable-bit = <3>;
  85                                 };
  86
  87                                 clkuart3: uart3 {
  88                                         #clock-cells = <0>;
  89                                         compatible = "via,vt8500-device-clock";
  90                                         clocks = <&ref24>;
  91                                         enable-reg = <0x250>;
  92                                         enable-bit = <4>;
  93                                 };
  94
  95                                 clkuart4: uart4 {
  96                                         #clock-cells = <0>;
  97                                         compatible = "via,vt8500-device-clock";
  98                                         clocks = <&ref24>;
  99                                         enable-reg = <0x250>;
 100                                         enable-bit = <22>;
 101                                 };
 102
 103                                 clkuart5: uart5 {
 104                                         #clock-cells = <0>;
 105                                         compatible = "via,vt8500-device-clock";
 106                                         clocks = <&ref24>;
 107                                         enable-reg = <0x250>;
 108                                         enable-bit = <23>;
 109                                 };
 110                         };
 111                 };
 112
 113                 timer@d8130100 {
 114                         compatible = "via,vt8500-timer";
 115                         reg = <0xd8130100 0x28>;
 116                         interrupts = <36>;
 117                 };
 118
 119                 ehci@d8007100 {
 120                         compatible = "via,vt8500-ehci";
 121                         reg = <0xd8007100 0x200>;
 122                         interrupts = <1>;
 123                 };
 124
 125                 uhci@d8007300 {
 126                         compatible = "platform-uhci";
 127                         reg = <0xd8007300 0x200>;
 128                         interrupts = <0>;
 129                 };
 130
 131                 fb@d8050800 {
 132                         compatible = "wm,wm8505-fb";
 133                         reg = <0xd8050800 0x200>;
 134                         display = <&display>;
 135                         default-mode = <&mode0>;
 136                 };
 137
 138                 ge_rops@d8050400 {
 139                         compatible = "wm,prizm-ge-rops";
 140                         reg = <0xd8050400 0x100>;
 141                 };
 142
 143                 uart@d8200000 {
 144                         compatible = "via,vt8500-uart";
 145                         reg = <0xd8200000 0x1040>;
 146                         interrupts = <32>;
 147                         clocks = <&clkuart0>;
 148                 };
 149
 150                 uart@d82b0000 {
 151                         compatible = "via,vt8500-uart";
 152                         reg = <0xd82b0000 0x1040>;
 153                         interrupts = <33>;
 154                         clocks = <&clkuart1>;
 155                 };
 156
 157                 uart@d8210000 {
 158                         compatible = "via,vt8500-uart";
 159                         reg = <0xd8210000 0x1040>;
 160                         interrupts = <47>;
 161                         clocks = <&clkuart2>;
 162                 };
 163
 164                 uart@d82c0000 {
 165                         compatible = "via,vt8500-uart";
 166                         reg = <0xd82c0000 0x1040>;
 167                         interrupts = <50>;
 168                         clocks = <&clkuart3>;
 169                 };
 170
 171                 uart@d8370000 {
 172                         compatible = "via,vt8500-uart";
 173                         reg = <0xd8370000 0x1040>;
 174                         interrupts = <31>;
 175                         clocks = <&clkuart4>;
 176                 };
 177
 178                 uart@d8380000 {
 179                         compatible = "via,vt8500-uart";
 180                         reg = <0xd8380000 0x1040>;
 181                         interrupts = <30>;
 182                         clocks = <&clkuart5>;
 183                 };
 184
 185                 rtc@d8100000 {
 186                         compatible = "via,vt8500-rtc";
 187                         reg = <0xd8100000 0x10000>;
 188                         interrupts = <48>;
 189                 };
 190         };
 191 };