arch/arm/mach-gemini/gpio.c

   1 /*
   2  * Gemini gpiochip and interrupt routines
   3  *
   4  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   5  *
   6  * Based on plat-mxc/gpio.c:
   7  *  MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   8  *  Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/gpio.h>
  21
  22 #include <mach/hardware.h>
  23 #include <mach/irqs.h>
  24
  25 #define GPIO_BASE(x)            IO_ADDRESS(GEMINI_GPIO_BASE(x))
  26
  27 /* GPIO registers definition */
  28 #define GPIO_DATA_OUT           0x0
  29 #define GPIO_DATA_IN            0x4
  30 #define GPIO_DIR                0x8
  31 #define GPIO_DATA_SET           0x10
  32 #define GPIO_DATA_CLR           0x14
  33 #define GPIO_PULL_EN            0x18
  34 #define GPIO_PULL_TYPE          0x1C
  35 #define GPIO_INT_EN             0x20
  36 #define GPIO_INT_STAT           0x24
  37 #define GPIO_INT_MASK           0x2C
  38 #define GPIO_INT_CLR            0x30
  39 #define GPIO_INT_TYPE           0x34
  40 #define GPIO_INT_BOTH_EDGE      0x38
  41 #define GPIO_INT_LEVEL          0x3C
  42 #define GPIO_DEBOUNCE_EN        0x40
  43 #define GPIO_DEBOUNCE_PRESCALE  0x44
  44
  45 #define GPIO_PORT_NUM           3
  46
  47 static void _set_gpio_irqenable(unsigned int base, unsigned int index,
  48                                 int enable)
  49 {
  50         unsigned int reg;
  51
  52         reg = __raw_readl(base + GPIO_INT_EN);
  53         reg = (reg & (~(1 << index))) | (!!enable << index);
  54         __raw_writel(reg, base + GPIO_INT_EN);
  55 }
  56
  57 static void gpio_ack_irq(struct irq_data *d)
  58 {
  59         unsigned int gpio = irq_to_gpio(d->irq);
  60         unsigned int base = GPIO_BASE(gpio / 32);
  61
  62         __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
  63 }
  64
  65 static void gpio_mask_irq(struct irq_data *d)
  66 {
  67         unsigned int gpio = irq_to_gpio(d->irq);
  68         unsigned int base = GPIO_BASE(gpio / 32);
  69
  70         _set_gpio_irqenable(base, gpio % 32, 0);
  71 }
  72
  73 static void gpio_unmask_irq(struct irq_data *d)
  74 {
  75         unsigned int gpio = irq_to_gpio(d->irq);
  76         unsigned int base = GPIO_BASE(gpio / 32);
  77
  78         _set_gpio_irqenable(base, gpio % 32, 1);
  79 }
  80
  81 static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
  82 {
  83         unsigned int gpio = irq_to_gpio(d->irq);
  84         unsigned int gpio_mask = 1 << (gpio % 32);
  85         unsigned int base = GPIO_BASE(gpio / 32);
  86         unsigned int reg_both, reg_level, reg_type;
  87
  88         reg_type = __raw_readl(base + GPIO_INT_TYPE);
  89         reg_level = __raw_readl(base + GPIO_INT_LEVEL);
  90         reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
  91
  92         switch (type) {
  93         case IRQ_TYPE_EDGE_BOTH:
  94                 reg_type &= ~gpio_mask;
  95                 reg_both |= gpio_mask;
  96                 break;
  97         case IRQ_TYPE_EDGE_RISING:
  98                 reg_type &= ~gpio_mask;
  99                 reg_both &= ~gpio_mask;
 100                 reg_level &= ~gpio_mask;
 101                 break;
 102         case IRQ_TYPE_EDGE_FALLING:
 103                 reg_type &= ~gpio_mask;
 104                 reg_both &= ~gpio_mask;
 105                 reg_level |= gpio_mask;
 106                 break;
 107         case IRQ_TYPE_LEVEL_HIGH:
 108                 reg_type |= gpio_mask;
 109                 reg_level &= ~gpio_mask;
 110                 break;
 111         case IRQ_TYPE_LEVEL_LOW:
 112                 reg_type |= gpio_mask;
 113                 reg_level |= gpio_mask;
 114                 break;
 115         default:
 116                 return -EINVAL;
 117         }
 118
 119         __raw_writel(reg_type, base + GPIO_INT_TYPE);
 120         __raw_writel(reg_level, base + GPIO_INT_LEVEL);
 121         __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
 122
 123         gpio_ack_irq(d->irq);
 124
 125         return 0;
 126 }
 127
 128 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 129 {
 130         unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
 131         unsigned int gpio_irq_no, irq_stat;
 132
 133         irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
 134
 135         gpio_irq_no = GPIO_IRQ_BASE + port * 32;
 136         for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
 137
 138                 if ((irq_stat & 1) == 0)
 139                         continue;
 140
 141                 generic_handle_irq(gpio_irq_no);
 142         }
 143 }
 144
 145 static struct irq_chip gpio_irq_chip = {
 146         .name = "GPIO",
 147         .irq_ack = gpio_ack_irq,
 148         .irq_mask = gpio_mask_irq,
 149         .irq_unmask = gpio_unmask_irq,
 150         .irq_set_type = gpio_set_irq_type,
 151 };
 152
 153 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
 154                                 int dir)
 155 {
 156         unsigned int base = GPIO_BASE(offset / 32);
 157         unsigned int reg;
 158
 159         reg = __raw_readl(base + GPIO_DIR);
 160         if (dir)
 161                 reg |= 1 << (offset % 32);
 162         else
 163                 reg &= ~(1 << (offset % 32));
 164         __raw_writel(reg, base + GPIO_DIR);
 165 }
 166
 167 static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 168 {
 169         unsigned int base = GPIO_BASE(offset / 32);
 170
 171         if (value)
 172                 __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
 173         else
 174                 __raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR);
 175 }
 176
 177 static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
 178 {
 179         unsigned int base = GPIO_BASE(offset / 32);
 180
 181         return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
 182 }
 183
 184 static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 185 {
 186         _set_gpio_direction(chip, offset, 0);
 187         return 0;
 188 }
 189
 190 static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 191                                         int value)
 192 {
 193         _set_gpio_direction(chip, offset, 1);
 194         gemini_gpio_set(chip, offset, value);
 195         return 0;
 196 }
 197
 198 static struct gpio_chip gemini_gpio_chip = {
 199         .label                  = "Gemini",
 200         .direction_input        = gemini_gpio_direction_input,
 201         .get                    = gemini_gpio_get,
 202         .direction_output       = gemini_gpio_direction_output,
 203         .set                    = gemini_gpio_set,
 204         .base                   = 0,
 205         .ngpio                  = GPIO_PORT_NUM * 32,
 206 };
 207
 208 void __init gemini_gpio_init(void)
 209 {
 210         int i, j;
 211
 212         for (i = 0; i < GPIO_PORT_NUM; i++) {
 213                 /* disable, unmask and clear all interrupts */
 214                 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN);
 215                 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK);
 216                 __raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR);
 217
 218                 for (j = GPIO_IRQ_BASE + i * 32;
 219                      j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
 220                         irq_set_chip_and_handler(j, &gpio_irq_chip,
 221                                                  handle_edge_irq);
 222                         set_irq_flags(j, IRQF_VALID);
 223                 }
 224
 225                 irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
 226                 irq_set_handler_data(IRQ_GPIO(i), (void *)i);
 227         }
 228
 229         BUG_ON(gpiochip_add(&gemini_gpio_chip));
 230 }