arch/powerpc/boot/dts/mpc5121.dtsi

   1 /*
   2  * base MPC5121 Device Tree Source
   3  *
   4  * Copyright 2007-2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "mpc5121";
  16         compatible = "fsl,mpc5121";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19         interrupt-parent = <&ipic>;
  20
  21         aliases {
  22                 ethernet0 = &eth0;
  23                 pci = &pci;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,5121@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <0x20>;     /* 32 bytes */
  34                         i-cache-line-size = <0x20>;     /* 32 bytes */
  35                         d-cache-size = <0x8000>;        /* L1, 32K */
  36                         i-cache-size = <0x8000>;        /* L1, 32K */
  37                         timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
  38                         bus-frequency = <198000000>;    /* 198 MHz csb bus */
  39                         clock-frequency = <396000000>;  /* 396 MHz ppc core */
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <0x00000000 0x10000000>;  /* 256MB at 0 */
  46         };
  47
  48         mbx@20000000 {
  49                 compatible = "fsl,mpc5121-mbx";
  50                 reg = <0x20000000 0x4000>;
  51                 interrupts = <66 0x8>;
  52         };
  53
  54         sram@30000000 {
  55                 compatible = "fsl,mpc5121-sram";
  56                 reg = <0x30000000 0x20000>;     /* 128K at 0x30000000 */
  57         };
  58
  59         nfc@40000000 {
  60                 compatible = "fsl,mpc5121-nfc";
  61                 reg = <0x40000000 0x100000>;    /* 1M at 0x40000000 */
  62                 interrupts = <6 8>;
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65         };
  66
  67         localbus@80000020 {
  68                 compatible = "fsl,mpc5121-localbus";
  69                 #address-cells = <2>;
  70                 #size-cells = <1>;
  71                 reg = <0x80000020 0x40>;
  72                 interrupts = <7 0x8>;
  73                 ranges = <0x0 0x0 0xfc000000 0x04000000>;
  74         };
  75
  76         soc@80000000 {
  77                 compatible = "fsl,mpc5121-immr";
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 #interrupt-cells = <2>;
  81                 ranges = <0x0 0x80000000 0x400000>;
  82                 reg = <0x80000000 0x400000>;
  83                 bus-frequency = <66000000>;     /* 66 MHz ips bus */
  84
  85
  86                 /*
  87                  * IPIC
  88                  * interrupts cell = <intr #, sense>
  89                  * sense values match linux IORESOURCE_IRQ_* defines:
  90                  * sense == 8: Level, low assertion
  91                  * sense == 2: Edge, high-to-low change
  92                  */
  93                 ipic: interrupt-controller@c00 {
  94                         compatible = "fsl,mpc5121-ipic", "fsl,ipic";
  95                         interrupt-controller;
  96                         #address-cells = <0>;
  97                         #interrupt-cells = <2>;
  98                         reg = <0xc00 0x100>;
  99                 };
 100
 101                 /* Watchdog timer */
 102                 wdt@900 {
 103                         compatible = "fsl,mpc5121-wdt";
 104                         reg = <0x900 0x100>;
 105                 };
 106
 107                 /* Real time clock */
 108                 rtc@a00 {
 109                         compatible = "fsl,mpc5121-rtc";
 110                         reg = <0xa00 0x100>;
 111                         interrupts = <79 0x8 80 0x8>;
 112                 };
 113
 114                 /* Reset module */
 115                 reset@e00 {
 116                         compatible = "fsl,mpc5121-reset";
 117                         reg = <0xe00 0x100>;
 118                 };
 119
 120                 /* Clock control */
 121                 clock@f00 {
 122                         compatible = "fsl,mpc5121-clock";
 123                         reg = <0xf00 0x100>;
 124                 };
 125
 126                 /* Power Management Controller */
 127                 pmc@1000{
 128                         compatible = "fsl,mpc5121-pmc";
 129                         reg = <0x1000 0x100>;
 130                         interrupts = <83 0x8>;
 131                 };
 132
 133                 gpio@1100 {
 134                         compatible = "fsl,mpc5121-gpio";
 135                         reg = <0x1100 0x100>;
 136                         interrupts = <78 0x8>;
 137                 };
 138
 139                 can@1300 {
 140                         compatible = "fsl,mpc5121-mscan";
 141                         reg = <0x1300 0x80>;
 142                         interrupts = <12 0x8>;
 143                 };
 144
 145                 can@1380 {
 146                         compatible = "fsl,mpc5121-mscan";
 147                         reg = <0x1380 0x80>;
 148                         interrupts = <13 0x8>;
 149                 };
 150
 151                 sdhc@1500 {
 152                         compatible = "fsl,mpc5121-sdhc";
 153                         reg = <0x1500 0x100>;
 154                         interrupts = <8 0x8>;
 155                 };
 156
 157                 i2c@1700 {
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
 161                         reg = <0x1700 0x20>;
 162                         interrupts = <9 0x8>;
 163                 };
 164
 165                 i2c@1720 {
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
 169                         reg = <0x1720 0x20>;
 170                         interrupts = <10 0x8>;
 171                 };
 172
 173                 i2c@1740 {
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
 177                         reg = <0x1740 0x20>;
 178                         interrupts = <11 0x8>;
 179                 };
 180
 181                 i2ccontrol@1760 {
 182                         compatible = "fsl,mpc5121-i2c-ctrl";
 183                         reg = <0x1760 0x8>;
 184                 };
 185
 186                 axe@2000 {
 187                         compatible = "fsl,mpc5121-axe";
 188                         reg = <0x2000 0x100>;
 189                         interrupts = <42 0x8>;
 190                 };
 191
 192                 display@2100 {
 193                         compatible = "fsl,mpc5121-diu";
 194                         reg = <0x2100 0x100>;
 195                         interrupts = <64 0x8>;
 196                 };
 197
 198                 can@2300 {
 199                         compatible = "fsl,mpc5121-mscan";
 200                         reg = <0x2300 0x80>;
 201                         interrupts = <90 0x8>;
 202                 };
 203
 204                 can@2380 {
 205                         compatible = "fsl,mpc5121-mscan";
 206                         reg = <0x2380 0x80>;
 207                         interrupts = <91 0x8>;
 208                 };
 209
 210                 viu@2400 {
 211                         compatible = "fsl,mpc5121-viu";
 212                         reg = <0x2400 0x400>;
 213                         interrupts = <67 0x8>;
 214                 };
 215
 216                 mdio@2800 {
 217                         compatible = "fsl,mpc5121-fec-mdio";
 218                         reg = <0x2800 0x800>;
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221                 };
 222
 223                 eth0: ethernet@2800 {
 224                         device_type = "network";
 225                         compatible = "fsl,mpc5121-fec";
 226                         reg = <0x2800 0x800>;
 227                         local-mac-address = [ 00 00 00 00 00 00 ];
 228                         interrupts = <4 0x8>;
 229                 };
 230
 231                 /* USB1 using external ULPI PHY */
 232                 usb@3000 {
 233                         compatible = "fsl,mpc5121-usb2-dr";
 234                         reg = <0x3000 0x600>;
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         interrupts = <43 0x8>;
 238                         dr_mode = "otg";
 239                         phy_type = "ulpi";
 240                 };
 241
 242                 /* USB0 using internal UTMI PHY */
 243                 usb@4000 {
 244                         compatible = "fsl,mpc5121-usb2-dr";
 245                         reg = <0x4000 0x600>;
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         interrupts = <44 0x8>;
 249                         dr_mode = "otg";
 250                         phy_type = "utmi_wide";
 251                 };
 252
 253                 /* IO control */
 254                 ioctl@a000 {
 255                         compatible = "fsl,mpc5121-ioctl";
 256                         reg = <0xA000 0x1000>;
 257                 };
 258
 259                 /* LocalPlus controller */
 260                 lpc@10000 {
 261                         compatible = "fsl,mpc5121-lpc";
 262                         reg = <0x10000 0x200>;
 263                 };
 264
 265                 pata@10200 {
 266                         compatible = "fsl,mpc5121-pata";
 267                         reg = <0x10200 0x100>;
 268                         interrupts = <5 0x8>;
 269                 };
 270
 271                 /* 512x PSCs are not 52xx PSC compatible */
 272
 273                 /* PSC0 */
 274                 psc@11000 {
 275                         compatible = "fsl,mpc5121-psc";
 276                         reg = <0x11000 0x100>;
 277                         interrupts = <40 0x8>;
 278                         fsl,rx-fifo-size = <16>;
 279                         fsl,tx-fifo-size = <16>;
 280                 };
 281
 282                 /* PSC1 */
 283                 psc@11100 {
 284                         compatible = "fsl,mpc5121-psc";
 285                         reg = <0x11100 0x100>;
 286                         interrupts = <40 0x8>;
 287                         fsl,rx-fifo-size = <16>;
 288                         fsl,tx-fifo-size = <16>;
 289                 };
 290
 291                 /* PSC2 */
 292                 psc@11200 {
 293                         compatible = "fsl,mpc5121-psc";
 294                         reg = <0x11200 0x100>;
 295                         interrupts = <40 0x8>;
 296                         fsl,rx-fifo-size = <16>;
 297                         fsl,tx-fifo-size = <16>;
 298                 };
 299
 300                 /* PSC3 */
 301                 psc@11300 {
 302                         compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
 303                         reg = <0x11300 0x100>;
 304                         interrupts = <40 0x8>;
 305                         fsl,rx-fifo-size = <16>;
 306                         fsl,tx-fifo-size = <16>;
 307                 };
 308
 309                 /* PSC4 */
 310                 psc@11400 {
 311                         compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
 312                         reg = <0x11400 0x100>;
 313                         interrupts = <40 0x8>;
 314                         fsl,rx-fifo-size = <16>;
 315                         fsl,tx-fifo-size = <16>;
 316                 };
 317
 318                 /* PSC5 */
 319                 psc@11500 {
 320                         compatible = "fsl,mpc5121-psc";
 321                         reg = <0x11500 0x100>;
 322                         interrupts = <40 0x8>;
 323                         fsl,rx-fifo-size = <16>;
 324                         fsl,tx-fifo-size = <16>;
 325                 };
 326
 327                 /* PSC6 */
 328                 psc@11600 {
 329                         compatible = "fsl,mpc5121-psc";
 330                         reg = <0x11600 0x100>;
 331                         interrupts = <40 0x8>;
 332                         fsl,rx-fifo-size = <16>;
 333                         fsl,tx-fifo-size = <16>;
 334                 };
 335
 336                 /* PSC7 */
 337                 psc@11700 {
 338                         compatible = "fsl,mpc5121-psc";
 339                         reg = <0x11700 0x100>;
 340                         interrupts = <40 0x8>;
 341                         fsl,rx-fifo-size = <16>;
 342                         fsl,tx-fifo-size = <16>;
 343                 };
 344
 345                 /* PSC8 */
 346                 psc@11800 {
 347                         compatible = "fsl,mpc5121-psc";
 348                         reg = <0x11800 0x100>;
 349                         interrupts = <40 0x8>;
 350                         fsl,rx-fifo-size = <16>;
 351                         fsl,tx-fifo-size = <16>;
 352                 };
 353
 354                 /* PSC9 */
 355                 psc@11900 {
 356                         compatible = "fsl,mpc5121-psc";
 357                         reg = <0x11900 0x100>;
 358                         interrupts = <40 0x8>;
 359                         fsl,rx-fifo-size = <16>;
 360                         fsl,tx-fifo-size = <16>;
 361                 };
 362
 363                 /* PSC10 */
 364                 psc@11a00 {
 365                         compatible = "fsl,mpc5121-psc";
 366                         reg = <0x11a00 0x100>;
 367                         interrupts = <40 0x8>;
 368                         fsl,rx-fifo-size = <16>;
 369                         fsl,tx-fifo-size = <16>;
 370                 };
 371
 372                 /* PSC11 */
 373                 psc@11b00 {
 374                         compatible = "fsl,mpc5121-psc";
 375                         reg = <0x11b00 0x100>;
 376                         interrupts = <40 0x8>;
 377                         fsl,rx-fifo-size = <16>;
 378                         fsl,tx-fifo-size = <16>;
 379                 };
 380
 381                 pscfifo@11f00 {
 382                         compatible = "fsl,mpc5121-psc-fifo";
 383                         reg = <0x11f00 0x100>;
 384                         interrupts = <40 0x8>;
 385                 };
 386
 387                 dma@14000 {
 388                         compatible = "fsl,mpc5121-dma";
 389                         reg = <0x14000 0x1800>;
 390                         interrupts = <65 0x8>;
 391                 };
 392         };
 393
 394         pci: pci@80008500 {
 395                 compatible = "fsl,mpc5121-pci";
 396                 device_type = "pci";
 397                 interrupts = <1 0x8>;
 398                 clock-frequency = <0>;
 399                 #address-cells = <3>;
 400                 #size-cells = <2>;
 401                 #interrupt-cells = <1>;
 402
 403                 reg = <0x80008500 0x100 /* internal registers */
 404                        0x80008300 0x8>; /* config space access registers */
 405                 bus-range = <0x0 0x0>;
 406                 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 407                           0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
 408                           0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
 409         };
 410 };