arch/sh/boards/mach-dreamcast/irq.c

   1 /*
   2  * arch/sh/boards/dreamcast/irq.c
   3  *
   4  * Holly IRQ support for the Sega Dreamcast.
   5  *
   6  * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
   7  *
   8  * This file is part of the LinuxDC project (www.linuxdc.org)
   9  * Released under the terms of the GNU GPL v2.0
  10  */
  11 #include <linux/irq.h>
  12 #include <linux/io.h>
  13 #include <linux/irq.h>
  14 #include <linux/export.h>
  15 #include <linux/err.h>
  16 #include <mach/sysasic.h>
  17
  18 /*
  19  * Dreamcast System ASIC Hardware Events -
  20  *
  21  * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
  22  * hardware events from system peripherals and triggering an SH7750 IRQ.
  23  * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
  24  * set in the Event Mask Registers (EMRs).  When a hardware event is
  25  * triggered, its corresponding bit in the Event Status Registers (ESRs)
  26  * is set, and that bit should be rewritten to the ESR to acknowledge that
  27  * event.
  28  *
  29  * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908.  Event
  30  * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
  31  * There are three groups of EMRs that parallel the ESRs.  Each EMR group
  32  * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
  33  * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
  34  * triggers IRQ 9.
  35  *
  36  * In the kernel, these events are mapped to virtual IRQs so that drivers can
  37  * respond to them as they would a normal interrupt.  In order to keep this
  38  * mapping simple, the events are mapped as:
  39  *
  40  * 6900/6910 - Events  0-31, IRQ 13
  41  * 6904/6924 - Events 32-63, IRQ 11
  42  * 6908/6938 - Events 64-95, IRQ  9
  43  *
  44  */
  45
  46 #define ESR_BASE 0x005f6900    /* Base event status register */
  47 #define EMR_BASE 0x005f6910    /* Base event mask register */
  48
  49 /*
  50  * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
  51  * 1 = 0x6920, 2 = 0x6930; also determine the event offset.
  52  */
  53 #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
  54
  55 /* Return the hardware event's bit position within the EMR/ESR */
  56 #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
  57
  58 /*
  59  * For each of these *_irq routines, the IRQ passed in is the virtual IRQ
  60  * (logically mapped to the corresponding bit for the hardware event).
  61  */
  62
  63 /* Disable the hardware event by masking its bit in its EMR */
  64 static inline void disable_systemasic_irq(struct irq_data *data)
  65 {
  66         unsigned int irq = data->irq;
  67         __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
  68         __u32 mask;
  69
  70         mask = inl(emr);
  71         mask &= ~(1 << EVENT_BIT(irq));
  72         outl(mask, emr);
  73 }
  74
  75 /* Enable the hardware event by setting its bit in its EMR */
  76 static inline void enable_systemasic_irq(struct irq_data *data)
  77 {
  78         unsigned int irq = data->irq;
  79         __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
  80         __u32 mask;
  81
  82         mask = inl(emr);
  83         mask |= (1 << EVENT_BIT(irq));
  84         outl(mask, emr);
  85 }
  86
  87 /* Acknowledge a hardware event by writing its bit back to its ESR */
  88 static void mask_ack_systemasic_irq(struct irq_data *data)
  89 {
  90         unsigned int irq = data->irq;
  91         __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
  92         disable_systemasic_irq(data);
  93         outl((1 << EVENT_BIT(irq)), esr);
  94 }
  95
  96 struct irq_chip systemasic_int = {
  97         .name           = "System ASIC",
  98         .irq_mask       = disable_systemasic_irq,
  99         .irq_mask_ack   = mask_ack_systemasic_irq,
 100         .irq_unmask     = enable_systemasic_irq,
 101 };
 102
 103 /*
 104  * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
 105  */
 106 int systemasic_irq_demux(int irq)
 107 {
 108         __u32 emr, esr, status, level;
 109         __u32 j, bit;
 110
 111         switch (irq) {
 112         case 13:
 113                 level = 0;
 114                 break;
 115         case 11:
 116                 level = 1;
 117                 break;
 118         case  9:
 119                 level = 2;
 120                 break;
 121         default:
 122                 return irq;
 123         }
 124         emr = EMR_BASE + (level << 4) + (level << 2);
 125         esr = ESR_BASE + (level << 2);
 126
 127         /* Mask the ESR to filter any spurious, unwanted interrupts */
 128         status = inl(esr);
 129         status &= inl(emr);
 130
 131         /* Now scan and find the first set bit as the event to map */
 132         for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
 133                 if (status & bit) {
 134                         irq = HW_EVENT_IRQ_BASE + j + (level << 5);
 135                         return irq;
 136                 }
 137         }
 138
 139         /* Not reached */
 140         return irq;
 141 }
 142
 143 void systemasic_irq_init(void)
 144 {
 145         int irq_base, i;
 146
 147         irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
 148                                    HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
 149         if (IS_ERR_VALUE(irq_base)) {
 150                 pr_err("%s: failed hooking irqs\n", __func__);
 151                 return;
 152         }
 153
 154         for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
 155                 irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
 156 }