2 * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
4 * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
12 /* This weird monster likes to use the very upper parts of
13 36bit PA for these things :) */
15 /* CSR space (for each XDBUS)
16 * ------------------------------------------------------------------------
17 * | 0xFE | DEVID | | XDBUS ID | |
18 * ------------------------------------------------------------------------
19 * 35 28 27 20 19 10 9 8 7 0
22 #define CSR_BASE_ADDR 0xe0000000
23 #define CSR_CPU_SHIFT (32 - 4 - 5)
24 #define CSR_XDBUS_SHIFT 8
26 #define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
28 /* ECSR space (not for each XDBUS)
29 * ------------------------------------------------------------------------
30 * | 0xF | DEVID[7:1] | |
31 * ------------------------------------------------------------------------
35 #define ECSR_BASE_ADDR 0x00000000
36 #define ECSR_CPU_SHIFT (32 - 5)
37 #define ECSR_DEV_SHIFT (32 - 8)
39 #define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
40 #define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
43 #define BW_LOCAL_BASE 0xfff00000
45 #define BW_CID 0x00000000
46 #define BW_DBUS_CTRL 0x00000008
47 #define BW_DBUS_DATA 0x00000010
48 #define BW_CTRL 0x00001000
49 #define BW_INTR_TABLE 0x00001040
50 #define BW_INTR_TABLE_CLEAR 0x00001080
51 #define BW_PRESCALER 0x000010c0
52 #define BW_PTIMER_LIMIT 0x00002000
53 #define BW_PTIMER_COUNTER2 0x00002004
54 #define BW_PTIMER_NDLIMIT 0x00002008
55 #define BW_PTIMER_CTRL 0x0000200c
56 #define BW_PTIMER_COUNTER 0x00002010
57 #define BW_TIMER_LIMIT 0x00003000
58 #define BW_TIMER_COUNTER2 0x00003004
59 #define BW_TIMER_NDLIMIT 0x00003008
60 #define BW_TIMER_CTRL 0x0000300c
61 #define BW_TIMER_COUNTER 0x00003010
64 #define BW_CTRL_USER_TIMER 0x00000004 /* Is User Timer Free run enabled */
67 #define BB_LOCAL_BASE 0xf0000000
69 #define BB_STAT1 0x00100000
70 #define BB_STAT2 0x00120000
71 #define BB_STAT3 0x00140000
72 #define BB_LEDS 0x002e0000
74 /* Bits in BB_STAT2 */
75 #define BB_STAT2_AC_INTR 0x04 /* Aiee! 5ms and power is gone... */
76 #define BB_STAT2_TMP_INTR 0x10 /* My Penguins are burning. Are you able to smell it? */
77 #define BB_STAT2_FAN_INTR 0x20 /* My fan refuses to work */
78 #define BB_STAT2_PWR_INTR 0x40 /* On SC2000, one of the two ACs died. Ok, we go on... */
79 #define BB_STAT2_MASK (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
81 /* Cache Controller */
82 #define CC_BASE 0x1F00000
83 #define CC_DATSTREAM 0x1F00000 /* Data stream register */
84 #define CC_DATSIZE 0x1F0003F /* Size */
85 #define CC_SRCSTREAM 0x1F00100 /* Source stream register */
86 #define CC_DESSTREAM 0x1F00200 /* Destination stream register */
87 #define CC_RMCOUNT 0x1F00300 /* Count of references and misses */
88 #define CC_IPEN 0x1F00406 /* Pending Interrupts */
89 #define CC_IMSK 0x1F00506 /* Interrupt Mask */
90 #define CC_ICLR 0x1F00606 /* Clear pending Interrupts */
91 #define CC_IGEN 0x1F00704 /* Generate Interrupt register */
92 #define CC_STEST 0x1F00804 /* Internal self-test */
93 #define CC_CREG 0x1F00A04 /* Control register */
94 #define CC_SREG 0x1F00B00 /* Status register */
95 #define CC_RREG 0x1F00C04 /* Reset register */
96 #define CC_EREG 0x1F00E00 /* Error code register */
97 #define CC_CID 0x1F00F04 /* Component ID */
101 static inline int bw_get_intr_mask(int sbus_level
)
105 __asm__
__volatile__ ("lduha [%1] %2, %0" :
107 "r" (BW_LOCAL_BASE
+ BW_INTR_TABLE
+ (sbus_level
<< 3)),
112 static inline void bw_clear_intr_mask(int sbus_level
, int mask
)
114 __asm__
__volatile__ ("stha %0, [%1] %2" : :
116 "r" (BW_LOCAL_BASE
+ BW_INTR_TABLE_CLEAR
+ (sbus_level
<< 3)),
120 static inline unsigned bw_get_prof_limit(int cpu
)
124 __asm__
__volatile__ ("lda [%1] %2, %0" :
126 "r" (CSR_BASE(cpu
) + BW_PTIMER_LIMIT
),
131 static inline void bw_set_prof_limit(int cpu
, unsigned limit
)
133 __asm__
__volatile__ ("sta %0, [%1] %2" : :
135 "r" (CSR_BASE(cpu
) + BW_PTIMER_LIMIT
),
139 static inline unsigned bw_get_ctrl(int cpu
)
143 __asm__
__volatile__ ("lda [%1] %2, %0" :
145 "r" (CSR_BASE(cpu
) + BW_CTRL
),
150 static inline void bw_set_ctrl(int cpu
, unsigned ctrl
)
152 __asm__
__volatile__ ("sta %0, [%1] %2" : :
154 "r" (CSR_BASE(cpu
) + BW_CTRL
),
158 static inline unsigned cc_get_ipen(void)
162 __asm__
__volatile__ ("lduha [%1] %2, %0" :
169 static inline void cc_set_iclr(unsigned clear
)
171 __asm__
__volatile__ ("stha %0, [%1] %2" : :
177 static inline unsigned cc_get_imsk(void)
181 __asm__
__volatile__ ("lduha [%1] %2, %0" :
188 static inline void cc_set_imsk(unsigned mask
)
190 __asm__
__volatile__ ("stha %0, [%1] %2" : :
196 static inline unsigned cc_get_imsk_other(int cpuid
)
200 __asm__
__volatile__ ("lduha [%1] %2, %0" :
202 "r" (ECSR_BASE(cpuid
) | CC_IMSK
),
207 static inline void cc_set_imsk_other(int cpuid
, unsigned mask
)
209 __asm__
__volatile__ ("stha %0, [%1] %2" : :
211 "r" (ECSR_BASE(cpuid
) | CC_IMSK
),
215 static inline void cc_set_igen(unsigned gen
)
217 __asm__
__volatile__ ("sta %0, [%1] %2" : :
223 #endif /* !__ASSEMBLY__ */
225 #endif /* !(_SPARC_OBIO_H) */