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locking/refcounts: Include fewer headers in <linux/refcount.h>
[linux/fpc-iii.git] / drivers / clk / meson / gxbb.c
blob240658404367f38670b79a2d40fcd1cdba92c67b
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Michael Turquette <mturquette@baylibre.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/init.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15
16 #include "clkc.h"
17 #include "gxbb.h"
18 #include "clk-regmap.h"
19
20 static DEFINE_SPINLOCK(meson_clk_lock);
21
22 static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
23 PLL_RATE(96000000, 32, 1, 3),
24 PLL_RATE(99000000, 33, 1, 3),
25 PLL_RATE(102000000, 34, 1, 3),
26 PLL_RATE(105000000, 35, 1, 3),
27 PLL_RATE(108000000, 36, 1, 3),
28 PLL_RATE(111000000, 37, 1, 3),
29 PLL_RATE(114000000, 38, 1, 3),
30 PLL_RATE(117000000, 39, 1, 3),
31 PLL_RATE(120000000, 40, 1, 3),
32 PLL_RATE(123000000, 41, 1, 3),
33 PLL_RATE(126000000, 42, 1, 3),
34 PLL_RATE(129000000, 43, 1, 3),
35 PLL_RATE(132000000, 44, 1, 3),
36 PLL_RATE(135000000, 45, 1, 3),
37 PLL_RATE(138000000, 46, 1, 3),
38 PLL_RATE(141000000, 47, 1, 3),
39 PLL_RATE(144000000, 48, 1, 3),
40 PLL_RATE(147000000, 49, 1, 3),
41 PLL_RATE(150000000, 50, 1, 3),
42 PLL_RATE(153000000, 51, 1, 3),
43 PLL_RATE(156000000, 52, 1, 3),
44 PLL_RATE(159000000, 53, 1, 3),
45 PLL_RATE(162000000, 54, 1, 3),
46 PLL_RATE(165000000, 55, 1, 3),
47 PLL_RATE(168000000, 56, 1, 3),
48 PLL_RATE(171000000, 57, 1, 3),
49 PLL_RATE(174000000, 58, 1, 3),
50 PLL_RATE(177000000, 59, 1, 3),
51 PLL_RATE(180000000, 60, 1, 3),
52 PLL_RATE(183000000, 61, 1, 3),
53 PLL_RATE(186000000, 62, 1, 3),
54 PLL_RATE(192000000, 32, 1, 2),
55 PLL_RATE(198000000, 33, 1, 2),
56 PLL_RATE(204000000, 34, 1, 2),
57 PLL_RATE(210000000, 35, 1, 2),
58 PLL_RATE(216000000, 36, 1, 2),
59 PLL_RATE(222000000, 37, 1, 2),
60 PLL_RATE(228000000, 38, 1, 2),
61 PLL_RATE(234000000, 39, 1, 2),
62 PLL_RATE(240000000, 40, 1, 2),
63 PLL_RATE(246000000, 41, 1, 2),
64 PLL_RATE(252000000, 42, 1, 2),
65 PLL_RATE(258000000, 43, 1, 2),
66 PLL_RATE(264000000, 44, 1, 2),
67 PLL_RATE(270000000, 45, 1, 2),
68 PLL_RATE(276000000, 46, 1, 2),
69 PLL_RATE(282000000, 47, 1, 2),
70 PLL_RATE(288000000, 48, 1, 2),
71 PLL_RATE(294000000, 49, 1, 2),
72 PLL_RATE(300000000, 50, 1, 2),
73 PLL_RATE(306000000, 51, 1, 2),
74 PLL_RATE(312000000, 52, 1, 2),
75 PLL_RATE(318000000, 53, 1, 2),
76 PLL_RATE(324000000, 54, 1, 2),
77 PLL_RATE(330000000, 55, 1, 2),
78 PLL_RATE(336000000, 56, 1, 2),
79 PLL_RATE(342000000, 57, 1, 2),
80 PLL_RATE(348000000, 58, 1, 2),
81 PLL_RATE(354000000, 59, 1, 2),
82 PLL_RATE(360000000, 60, 1, 2),
83 PLL_RATE(366000000, 61, 1, 2),
84 PLL_RATE(372000000, 62, 1, 2),
85 PLL_RATE(384000000, 32, 1, 1),
86 PLL_RATE(396000000, 33, 1, 1),
87 PLL_RATE(408000000, 34, 1, 1),
88 PLL_RATE(420000000, 35, 1, 1),
89 PLL_RATE(432000000, 36, 1, 1),
90 PLL_RATE(444000000, 37, 1, 1),
91 PLL_RATE(456000000, 38, 1, 1),
92 PLL_RATE(468000000, 39, 1, 1),
93 PLL_RATE(480000000, 40, 1, 1),
94 PLL_RATE(492000000, 41, 1, 1),
95 PLL_RATE(504000000, 42, 1, 1),
96 PLL_RATE(516000000, 43, 1, 1),
97 PLL_RATE(528000000, 44, 1, 1),
98 PLL_RATE(540000000, 45, 1, 1),
99 PLL_RATE(552000000, 46, 1, 1),
100 PLL_RATE(564000000, 47, 1, 1),
101 PLL_RATE(576000000, 48, 1, 1),
102 PLL_RATE(588000000, 49, 1, 1),
103 PLL_RATE(600000000, 50, 1, 1),
104 PLL_RATE(612000000, 51, 1, 1),
105 PLL_RATE(624000000, 52, 1, 1),
106 PLL_RATE(636000000, 53, 1, 1),
107 PLL_RATE(648000000, 54, 1, 1),
108 PLL_RATE(660000000, 55, 1, 1),
109 PLL_RATE(672000000, 56, 1, 1),
110 PLL_RATE(684000000, 57, 1, 1),
111 PLL_RATE(696000000, 58, 1, 1),
112 PLL_RATE(708000000, 59, 1, 1),
113 PLL_RATE(720000000, 60, 1, 1),
114 PLL_RATE(732000000, 61, 1, 1),
115 PLL_RATE(744000000, 62, 1, 1),
116 PLL_RATE(768000000, 32, 1, 0),
117 PLL_RATE(792000000, 33, 1, 0),
118 PLL_RATE(816000000, 34, 1, 0),
119 PLL_RATE(840000000, 35, 1, 0),
120 PLL_RATE(864000000, 36, 1, 0),
121 PLL_RATE(888000000, 37, 1, 0),
122 PLL_RATE(912000000, 38, 1, 0),
123 PLL_RATE(936000000, 39, 1, 0),
124 PLL_RATE(960000000, 40, 1, 0),
125 PLL_RATE(984000000, 41, 1, 0),
126 PLL_RATE(1008000000, 42, 1, 0),
127 PLL_RATE(1032000000, 43, 1, 0),
128 PLL_RATE(1056000000, 44, 1, 0),
129 PLL_RATE(1080000000, 45, 1, 0),
130 PLL_RATE(1104000000, 46, 1, 0),
131 PLL_RATE(1128000000, 47, 1, 0),
132 PLL_RATE(1152000000, 48, 1, 0),
133 PLL_RATE(1176000000, 49, 1, 0),
134 PLL_RATE(1200000000, 50, 1, 0),
135 PLL_RATE(1224000000, 51, 1, 0),
136 PLL_RATE(1248000000, 52, 1, 0),
137 PLL_RATE(1272000000, 53, 1, 0),
138 PLL_RATE(1296000000, 54, 1, 0),
139 PLL_RATE(1320000000, 55, 1, 0),
140 PLL_RATE(1344000000, 56, 1, 0),
141 PLL_RATE(1368000000, 57, 1, 0),
142 PLL_RATE(1392000000, 58, 1, 0),
143 PLL_RATE(1416000000, 59, 1, 0),
144 PLL_RATE(1440000000, 60, 1, 0),
145 PLL_RATE(1464000000, 61, 1, 0),
146 PLL_RATE(1488000000, 62, 1, 0),
147 { /* sentinel */ },
148 };
149
150 static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
151 PLL_RATE(504000000, 42, 1, 1),
152 PLL_RATE(516000000, 43, 1, 1),
153 PLL_RATE(528000000, 44, 1, 1),
154 PLL_RATE(540000000, 45, 1, 1),
155 PLL_RATE(552000000, 46, 1, 1),
156 PLL_RATE(564000000, 47, 1, 1),
157 PLL_RATE(576000000, 48, 1, 1),
158 PLL_RATE(588000000, 49, 1, 1),
159 PLL_RATE(600000000, 50, 1, 1),
160 PLL_RATE(612000000, 51, 1, 1),
161 PLL_RATE(624000000, 52, 1, 1),
162 PLL_RATE(636000000, 53, 1, 1),
163 PLL_RATE(648000000, 54, 1, 1),
164 PLL_RATE(660000000, 55, 1, 1),
165 PLL_RATE(672000000, 56, 1, 1),
166 PLL_RATE(684000000, 57, 1, 1),
167 PLL_RATE(696000000, 58, 1, 1),
168 PLL_RATE(708000000, 59, 1, 1),
169 PLL_RATE(720000000, 60, 1, 1),
170 PLL_RATE(732000000, 61, 1, 1),
171 PLL_RATE(744000000, 62, 1, 1),
172 PLL_RATE(756000000, 63, 1, 1),
173 PLL_RATE(768000000, 64, 1, 1),
174 PLL_RATE(780000000, 65, 1, 1),
175 PLL_RATE(792000000, 66, 1, 1),
176 { /* sentinel */ },
177 };
178
179 static struct clk_regmap gxbb_fixed_pll = {
180 .data = &(struct meson_clk_pll_data){
181 .m = {
182 .reg_off = HHI_MPLL_CNTL,
183 .shift = 0,
184 .width = 9,
185 },
186 .n = {
187 .reg_off = HHI_MPLL_CNTL,
188 .shift = 9,
189 .width = 5,
190 },
191 .od = {
192 .reg_off = HHI_MPLL_CNTL,
193 .shift = 16,
194 .width = 2,
195 },
196 .frac = {
197 .reg_off = HHI_MPLL_CNTL2,
198 .shift = 0,
199 .width = 12,
200 },
201 .l = {
202 .reg_off = HHI_MPLL_CNTL,
203 .shift = 31,
204 .width = 1,
205 },
206 .rst = {
207 .reg_off = HHI_MPLL_CNTL,
208 .shift = 29,
209 .width = 1,
210 },
211 },
212 .hw.init = &(struct clk_init_data){
213 .name = "fixed_pll",
214 .ops = &meson_clk_pll_ro_ops,
215 .parent_names = (const char *[]){ "xtal" },
216 .num_parents = 1,
217 .flags = CLK_GET_RATE_NOCACHE,
218 },
219 };
220
221 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
222 .mult = 2,
223 .div = 1,
224 .hw.init = &(struct clk_init_data){
225 .name = "hdmi_pll_pre_mult",
226 .ops = &clk_fixed_factor_ops,
227 .parent_names = (const char *[]){ "xtal" },
228 .num_parents = 1,
229 },
230 };
231
232 static struct clk_regmap gxbb_hdmi_pll = {
233 .data = &(struct meson_clk_pll_data){
234 .m = {
235 .reg_off = HHI_HDMI_PLL_CNTL,
236 .shift = 0,
237 .width = 9,
238 },
239 .n = {
240 .reg_off = HHI_HDMI_PLL_CNTL,
241 .shift = 9,
242 .width = 5,
243 },
244 .frac = {
245 .reg_off = HHI_HDMI_PLL_CNTL2,
246 .shift = 0,
247 .width = 12,
248 },
249 .od = {
250 .reg_off = HHI_HDMI_PLL_CNTL2,
251 .shift = 16,
252 .width = 2,
253 },
254 .od2 = {
255 .reg_off = HHI_HDMI_PLL_CNTL2,
256 .shift = 22,
257 .width = 2,
258 },
259 .od3 = {
260 .reg_off = HHI_HDMI_PLL_CNTL2,
261 .shift = 18,
262 .width = 2,
263 },
264 .l = {
265 .reg_off = HHI_HDMI_PLL_CNTL,
266 .shift = 31,
267 .width = 1,
268 },
269 .rst = {
270 .reg_off = HHI_HDMI_PLL_CNTL,
271 .shift = 28,
272 .width = 1,
273 },
274 },
275 .hw.init = &(struct clk_init_data){
276 .name = "hdmi_pll",
277 .ops = &meson_clk_pll_ro_ops,
278 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
279 .num_parents = 1,
280 .flags = CLK_GET_RATE_NOCACHE,
281 },
282 };
283
284 static struct clk_regmap gxl_hdmi_pll = {
285 .data = &(struct meson_clk_pll_data){
286 .m = {
287 .reg_off = HHI_HDMI_PLL_CNTL,
288 .shift = 0,
289 .width = 9,
290 },
291 .n = {
292 .reg_off = HHI_HDMI_PLL_CNTL,
293 .shift = 9,
294 .width = 5,
295 },
296 .frac = {
297 /*
298 * On gxl, there is a register shift due to
299 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
300 * so we compute the register offset based on the PLL
301 * base to get it right
302 */
303 .reg_off = HHI_HDMI_PLL_CNTL + 4,
304 .shift = 0,
305 .width = 12,
306 },
307 .od = {
308 .reg_off = HHI_HDMI_PLL_CNTL + 8,
309 .shift = 21,
310 .width = 2,
311 },
312 .od2 = {
313 .reg_off = HHI_HDMI_PLL_CNTL + 8,
314 .shift = 23,
315 .width = 2,
316 },
317 .od3 = {
318 .reg_off = HHI_HDMI_PLL_CNTL + 8,
319 .shift = 19,
320 .width = 2,
321 },
322 .l = {
323 .reg_off = HHI_HDMI_PLL_CNTL,
324 .shift = 31,
325 .width = 1,
326 },
327 .rst = {
328 .reg_off = HHI_HDMI_PLL_CNTL,
329 .shift = 29,
330 .width = 1,
331 },
332 },
333 .hw.init = &(struct clk_init_data){
334 .name = "hdmi_pll",
335 .ops = &meson_clk_pll_ro_ops,
336 .parent_names = (const char *[]){ "xtal" },
337 .num_parents = 1,
338 .flags = CLK_GET_RATE_NOCACHE,
339 },
340 };
341
342 static struct clk_regmap gxbb_sys_pll = {
343 .data = &(struct meson_clk_pll_data){
344 .m = {
345 .reg_off = HHI_SYS_PLL_CNTL,
346 .shift = 0,
347 .width = 9,
348 },
349 .n = {
350 .reg_off = HHI_SYS_PLL_CNTL,
351 .shift = 9,
352 .width = 5,
353 },
354 .od = {
355 .reg_off = HHI_SYS_PLL_CNTL,
356 .shift = 10,
357 .width = 2,
358 },
359 .l = {
360 .reg_off = HHI_SYS_PLL_CNTL,
361 .shift = 31,
362 .width = 1,
363 },
364 .rst = {
365 .reg_off = HHI_SYS_PLL_CNTL,
366 .shift = 29,
367 .width = 1,
368 },
369 },
370 .hw.init = &(struct clk_init_data){
371 .name = "sys_pll",
372 .ops = &meson_clk_pll_ro_ops,
373 .parent_names = (const char *[]){ "xtal" },
374 .num_parents = 1,
375 .flags = CLK_GET_RATE_NOCACHE,
376 },
377 };
378
379 static const struct reg_sequence gxbb_gp0_init_regs[] = {
380 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
381 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
382 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
383 { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 },
384 };
385
386 static struct clk_regmap gxbb_gp0_pll = {
387 .data = &(struct meson_clk_pll_data){
388 .m = {
389 .reg_off = HHI_GP0_PLL_CNTL,
390 .shift = 0,
391 .width = 9,
392 },
393 .n = {
394 .reg_off = HHI_GP0_PLL_CNTL,
395 .shift = 9,
396 .width = 5,
397 },
398 .od = {
399 .reg_off = HHI_GP0_PLL_CNTL,
400 .shift = 16,
401 .width = 2,
402 },
403 .l = {
404 .reg_off = HHI_GP0_PLL_CNTL,
405 .shift = 31,
406 .width = 1,
407 },
408 .rst = {
409 .reg_off = HHI_GP0_PLL_CNTL,
410 .shift = 29,
411 .width = 1,
412 },
413 .table = gxbb_gp0_pll_rate_table,
414 .init_regs = gxbb_gp0_init_regs,
415 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
416 },
417 .hw.init = &(struct clk_init_data){
418 .name = "gp0_pll",
419 .ops = &meson_clk_pll_ops,
420 .parent_names = (const char *[]){ "xtal" },
421 .num_parents = 1,
422 .flags = CLK_GET_RATE_NOCACHE,
423 },
424 };
425
426 static const struct reg_sequence gxl_gp0_init_regs[] = {
427 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
428 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
429 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
430 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
431 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
432 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
433 };
434
435 static struct clk_regmap gxl_gp0_pll = {
436 .data = &(struct meson_clk_pll_data){
437 .m = {
438 .reg_off = HHI_GP0_PLL_CNTL,
439 .shift = 0,
440 .width = 9,
441 },
442 .n = {
443 .reg_off = HHI_GP0_PLL_CNTL,
444 .shift = 9,
445 .width = 5,
446 },
447 .od = {
448 .reg_off = HHI_GP0_PLL_CNTL,
449 .shift = 16,
450 .width = 2,
451 },
452 .frac = {
453 .reg_off = HHI_GP0_PLL_CNTL1,
454 .shift = 0,
455 .width = 10,
456 },
457 .l = {
458 .reg_off = HHI_GP0_PLL_CNTL,
459 .shift = 31,
460 .width = 1,
461 },
462 .rst = {
463 .reg_off = HHI_GP0_PLL_CNTL,
464 .shift = 29,
465 .width = 1,
466 },
467 .table = gxl_gp0_pll_rate_table,
468 .init_regs = gxl_gp0_init_regs,
469 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
470 },
471 .hw.init = &(struct clk_init_data){
472 .name = "gp0_pll",
473 .ops = &meson_clk_pll_ops,
474 .parent_names = (const char *[]){ "xtal" },
475 .num_parents = 1,
476 .flags = CLK_GET_RATE_NOCACHE,
477 },
478 };
479
480 static struct clk_fixed_factor gxbb_fclk_div2_div = {
481 .mult = 1,
482 .div = 2,
483 .hw.init = &(struct clk_init_data){
484 .name = "fclk_div2_div",
485 .ops = &clk_fixed_factor_ops,
486 .parent_names = (const char *[]){ "fixed_pll" },
487 .num_parents = 1,
488 },
489 };
490
491 static struct clk_regmap gxbb_fclk_div2 = {
492 .data = &(struct clk_regmap_gate_data){
493 .offset = HHI_MPLL_CNTL6,
494 .bit_idx = 27,
495 },
496 .hw.init = &(struct clk_init_data){
497 .name = "fclk_div2",
498 .ops = &clk_regmap_gate_ops,
499 .parent_names = (const char *[]){ "fclk_div2_div" },
500 .num_parents = 1,
501 },
502 };
503
504 static struct clk_fixed_factor gxbb_fclk_div3_div = {
505 .mult = 1,
506 .div = 3,
507 .hw.init = &(struct clk_init_data){
508 .name = "fclk_div3_div",
509 .ops = &clk_fixed_factor_ops,
510 .parent_names = (const char *[]){ "fixed_pll" },
511 .num_parents = 1,
512 },
513 };
514
515 static struct clk_regmap gxbb_fclk_div3 = {
516 .data = &(struct clk_regmap_gate_data){
517 .offset = HHI_MPLL_CNTL6,
518 .bit_idx = 28,
519 },
520 .hw.init = &(struct clk_init_data){
521 .name = "fclk_div3",
522 .ops = &clk_regmap_gate_ops,
523 .parent_names = (const char *[]){ "fclk_div3_div" },
524 .num_parents = 1,
525 },
526 };
527
528 static struct clk_fixed_factor gxbb_fclk_div4_div = {
529 .mult = 1,
530 .div = 4,
531 .hw.init = &(struct clk_init_data){
532 .name = "fclk_div4_div",
533 .ops = &clk_fixed_factor_ops,
534 .parent_names = (const char *[]){ "fixed_pll" },
535 .num_parents = 1,
536 },
537 };
538
539 static struct clk_regmap gxbb_fclk_div4 = {
540 .data = &(struct clk_regmap_gate_data){
541 .offset = HHI_MPLL_CNTL6,
542 .bit_idx = 29,
543 },
544 .hw.init = &(struct clk_init_data){
545 .name = "fclk_div4",
546 .ops = &clk_regmap_gate_ops,
547 .parent_names = (const char *[]){ "fclk_div4_div" },
548 .num_parents = 1,
549 },
550 };
551
552 static struct clk_fixed_factor gxbb_fclk_div5_div = {
553 .mult = 1,
554 .div = 5,
555 .hw.init = &(struct clk_init_data){
556 .name = "fclk_div5_div",
557 .ops = &clk_fixed_factor_ops,
558 .parent_names = (const char *[]){ "fixed_pll" },
559 .num_parents = 1,
560 },
561 };
562
563 static struct clk_regmap gxbb_fclk_div5 = {
564 .data = &(struct clk_regmap_gate_data){
565 .offset = HHI_MPLL_CNTL6,
566 .bit_idx = 30,
567 },
568 .hw.init = &(struct clk_init_data){
569 .name = "fclk_div5",
570 .ops = &clk_regmap_gate_ops,
571 .parent_names = (const char *[]){ "fclk_div5_div" },
572 .num_parents = 1,
573 },
574 };
575
576 static struct clk_fixed_factor gxbb_fclk_div7_div = {
577 .mult = 1,
578 .div = 7,
579 .hw.init = &(struct clk_init_data){
580 .name = "fclk_div7_div",
581 .ops = &clk_fixed_factor_ops,
582 .parent_names = (const char *[]){ "fixed_pll" },
583 .num_parents = 1,
584 },
585 };
586
587 static struct clk_regmap gxbb_fclk_div7 = {
588 .data = &(struct clk_regmap_gate_data){
589 .offset = HHI_MPLL_CNTL6,
590 .bit_idx = 31,
591 },
592 .hw.init = &(struct clk_init_data){
593 .name = "fclk_div7",
594 .ops = &clk_regmap_gate_ops,
595 .parent_names = (const char *[]){ "fclk_div7_div" },
596 .num_parents = 1,
597 },
598 };
599
600 static struct clk_regmap gxbb_mpll_prediv = {
601 .data = &(struct clk_regmap_div_data){
602 .offset = HHI_MPLL_CNTL5,
603 .shift = 12,
604 .width = 1,
605 },
606 .hw.init = &(struct clk_init_data){
607 .name = "mpll_prediv",
608 .ops = &clk_regmap_divider_ro_ops,
609 .parent_names = (const char *[]){ "fixed_pll" },
610 .num_parents = 1,
611 },
612 };
613
614 static struct clk_regmap gxbb_mpll0_div = {
615 .data = &(struct meson_clk_mpll_data){
616 .sdm = {
617 .reg_off = HHI_MPLL_CNTL7,
618 .shift = 0,
619 .width = 14,
620 },
621 .sdm_en = {
622 .reg_off = HHI_MPLL_CNTL7,
623 .shift = 15,
624 .width = 1,
625 },
626 .n2 = {
627 .reg_off = HHI_MPLL_CNTL7,
628 .shift = 16,
629 .width = 9,
630 },
631 .ssen = {
632 .reg_off = HHI_MPLL_CNTL,
633 .shift = 25,
634 .width = 1,
635 },
636 .lock = &meson_clk_lock,
637 },
638 .hw.init = &(struct clk_init_data){
639 .name = "mpll0_div",
640 .ops = &meson_clk_mpll_ops,
641 .parent_names = (const char *[]){ "mpll_prediv" },
642 .num_parents = 1,
643 },
644 };
645
646 static struct clk_regmap gxbb_mpll0 = {
647 .data = &(struct clk_regmap_gate_data){
648 .offset = HHI_MPLL_CNTL7,
649 .bit_idx = 14,
650 },
651 .hw.init = &(struct clk_init_data){
652 .name = "mpll0",
653 .ops = &clk_regmap_gate_ops,
654 .parent_names = (const char *[]){ "mpll0_div" },
655 .num_parents = 1,
656 .flags = CLK_SET_RATE_PARENT,
657 },
658 };
659
660 static struct clk_regmap gxbb_mpll1_div = {
661 .data = &(struct meson_clk_mpll_data){
662 .sdm = {
663 .reg_off = HHI_MPLL_CNTL8,
664 .shift = 0,
665 .width = 14,
666 },
667 .sdm_en = {
668 .reg_off = HHI_MPLL_CNTL8,
669 .shift = 15,
670 .width = 1,
671 },
672 .n2 = {
673 .reg_off = HHI_MPLL_CNTL8,
674 .shift = 16,
675 .width = 9,
676 },
677 .lock = &meson_clk_lock,
678 },
679 .hw.init = &(struct clk_init_data){
680 .name = "mpll1_div",
681 .ops = &meson_clk_mpll_ops,
682 .parent_names = (const char *[]){ "mpll_prediv" },
683 .num_parents = 1,
684 },
685 };
686
687 static struct clk_regmap gxbb_mpll1 = {
688 .data = &(struct clk_regmap_gate_data){
689 .offset = HHI_MPLL_CNTL8,
690 .bit_idx = 14,
691 },
692 .hw.init = &(struct clk_init_data){
693 .name = "mpll1",
694 .ops = &clk_regmap_gate_ops,
695 .parent_names = (const char *[]){ "mpll1_div" },
696 .num_parents = 1,
697 .flags = CLK_SET_RATE_PARENT,
698 },
699 };
700
701 static struct clk_regmap gxbb_mpll2_div = {
702 .data = &(struct meson_clk_mpll_data){
703 .sdm = {
704 .reg_off = HHI_MPLL_CNTL9,
705 .shift = 0,
706 .width = 14,
707 },
708 .sdm_en = {
709 .reg_off = HHI_MPLL_CNTL9,
710 .shift = 15,
711 .width = 1,
712 },
713 .n2 = {
714 .reg_off = HHI_MPLL_CNTL9,
715 .shift = 16,
716 .width = 9,
717 },
718 .lock = &meson_clk_lock,
719 },
720 .hw.init = &(struct clk_init_data){
721 .name = "mpll2_div",
722 .ops = &meson_clk_mpll_ops,
723 .parent_names = (const char *[]){ "mpll_prediv" },
724 .num_parents = 1,
725 },
726 };
727
728 static struct clk_regmap gxbb_mpll2 = {
729 .data = &(struct clk_regmap_gate_data){
730 .offset = HHI_MPLL_CNTL9,
731 .bit_idx = 14,
732 },
733 .hw.init = &(struct clk_init_data){
734 .name = "mpll2",
735 .ops = &clk_regmap_gate_ops,
736 .parent_names = (const char *[]){ "mpll2_div" },
737 .num_parents = 1,
738 .flags = CLK_SET_RATE_PARENT,
739 },
740 };
741
742 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
743 static const char * const clk81_parent_names[] = {
744 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
745 "fclk_div3", "fclk_div5"
746 };
747
748 static struct clk_regmap gxbb_mpeg_clk_sel = {
749 .data = &(struct clk_regmap_mux_data){
750 .offset = HHI_MPEG_CLK_CNTL,
751 .mask = 0x7,
752 .shift = 12,
753 .table = mux_table_clk81,
754 },
755 .hw.init = &(struct clk_init_data){
756 .name = "mpeg_clk_sel",
757 .ops = &clk_regmap_mux_ro_ops,
758 /*
759 * bits 14:12 selects from 8 possible parents:
760 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
761 * fclk_div4, fclk_div3, fclk_div5
762 */
763 .parent_names = clk81_parent_names,
764 .num_parents = ARRAY_SIZE(clk81_parent_names),
765 },
766 };
767
768 static struct clk_regmap gxbb_mpeg_clk_div = {
769 .data = &(struct clk_regmap_div_data){
770 .offset = HHI_MPEG_CLK_CNTL,
771 .shift = 0,
772 .width = 7,
773 },
774 .hw.init = &(struct clk_init_data){
775 .name = "mpeg_clk_div",
776 .ops = &clk_regmap_divider_ro_ops,
777 .parent_names = (const char *[]){ "mpeg_clk_sel" },
778 .num_parents = 1,
779 },
780 };
781
782 /* the mother of dragons gates */
783 static struct clk_regmap gxbb_clk81 = {
784 .data = &(struct clk_regmap_gate_data){
785 .offset = HHI_MPEG_CLK_CNTL,
786 .bit_idx = 7,
787 },
788 .hw.init = &(struct clk_init_data){
789 .name = "clk81",
790 .ops = &clk_regmap_gate_ops,
791 .parent_names = (const char *[]){ "mpeg_clk_div" },
792 .num_parents = 1,
793 .flags = CLK_IS_CRITICAL,
794 },
795 };
796
797 static struct clk_regmap gxbb_sar_adc_clk_sel = {
798 .data = &(struct clk_regmap_mux_data){
799 .offset = HHI_SAR_CLK_CNTL,
800 .mask = 0x3,
801 .shift = 9,
802 },
803 .hw.init = &(struct clk_init_data){
804 .name = "sar_adc_clk_sel",
805 .ops = &clk_regmap_mux_ops,
806 /* NOTE: The datasheet doesn't list the parents for bit 10 */
807 .parent_names = (const char *[]){ "xtal", "clk81", },
808 .num_parents = 2,
809 },
810 };
811
812 static struct clk_regmap gxbb_sar_adc_clk_div = {
813 .data = &(struct clk_regmap_div_data){
814 .offset = HHI_SAR_CLK_CNTL,
815 .shift = 0,
816 .width = 8,
817 },
818 .hw.init = &(struct clk_init_data){
819 .name = "sar_adc_clk_div",
820 .ops = &clk_regmap_divider_ops,
821 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
822 .num_parents = 1,
823 },
824 };
825
826 static struct clk_regmap gxbb_sar_adc_clk = {
827 .data = &(struct clk_regmap_gate_data){
828 .offset = HHI_SAR_CLK_CNTL,
829 .bit_idx = 8,
830 },
831 .hw.init = &(struct clk_init_data){
832 .name = "sar_adc_clk",
833 .ops = &clk_regmap_gate_ops,
834 .parent_names = (const char *[]){ "sar_adc_clk_div" },
835 .num_parents = 1,
836 .flags = CLK_SET_RATE_PARENT,
837 },
838 };
839
840 /*
841 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
842 * muxed by a glitch-free switch.
843 */
844
845 static const char * const gxbb_mali_0_1_parent_names[] = {
846 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
847 "fclk_div4", "fclk_div3", "fclk_div5"
848 };
849
850 static struct clk_regmap gxbb_mali_0_sel = {
851 .data = &(struct clk_regmap_mux_data){
852 .offset = HHI_MALI_CLK_CNTL,
853 .mask = 0x7,
854 .shift = 9,
855 },
856 .hw.init = &(struct clk_init_data){
857 .name = "mali_0_sel",
858 .ops = &clk_regmap_mux_ops,
859 /*
860 * bits 10:9 selects from 8 possible parents:
861 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
862 * fclk_div4, fclk_div3, fclk_div5
863 */
864 .parent_names = gxbb_mali_0_1_parent_names,
865 .num_parents = 8,
866 .flags = CLK_SET_RATE_NO_REPARENT,
867 },
868 };
869
870 static struct clk_regmap gxbb_mali_0_div = {
871 .data = &(struct clk_regmap_div_data){
872 .offset = HHI_MALI_CLK_CNTL,
873 .shift = 0,
874 .width = 7,
875 },
876 .hw.init = &(struct clk_init_data){
877 .name = "mali_0_div",
878 .ops = &clk_regmap_divider_ops,
879 .parent_names = (const char *[]){ "mali_0_sel" },
880 .num_parents = 1,
881 .flags = CLK_SET_RATE_NO_REPARENT,
882 },
883 };
884
885 static struct clk_regmap gxbb_mali_0 = {
886 .data = &(struct clk_regmap_gate_data){
887 .offset = HHI_MALI_CLK_CNTL,
888 .bit_idx = 8,
889 },
890 .hw.init = &(struct clk_init_data){
891 .name = "mali_0",
892 .ops = &clk_regmap_gate_ops,
893 .parent_names = (const char *[]){ "mali_0_div" },
894 .num_parents = 1,
895 .flags = CLK_SET_RATE_PARENT,
896 },
897 };
898
899 static struct clk_regmap gxbb_mali_1_sel = {
900 .data = &(struct clk_regmap_mux_data){
901 .offset = HHI_MALI_CLK_CNTL,
902 .mask = 0x7,
903 .shift = 25,
904 },
905 .hw.init = &(struct clk_init_data){
906 .name = "mali_1_sel",
907 .ops = &clk_regmap_mux_ops,
908 /*
909 * bits 10:9 selects from 8 possible parents:
910 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
911 * fclk_div4, fclk_div3, fclk_div5
912 */
913 .parent_names = gxbb_mali_0_1_parent_names,
914 .num_parents = 8,
915 .flags = CLK_SET_RATE_NO_REPARENT,
916 },
917 };
918
919 static struct clk_regmap gxbb_mali_1_div = {
920 .data = &(struct clk_regmap_div_data){
921 .offset = HHI_MALI_CLK_CNTL,
922 .shift = 16,
923 .width = 7,
924 },
925 .hw.init = &(struct clk_init_data){
926 .name = "mali_1_div",
927 .ops = &clk_regmap_divider_ops,
928 .parent_names = (const char *[]){ "mali_1_sel" },
929 .num_parents = 1,
930 .flags = CLK_SET_RATE_NO_REPARENT,
931 },
932 };
933
934 static struct clk_regmap gxbb_mali_1 = {
935 .data = &(struct clk_regmap_gate_data){
936 .offset = HHI_MALI_CLK_CNTL,
937 .bit_idx = 24,
938 },
939 .hw.init = &(struct clk_init_data){
940 .name = "mali_1",
941 .ops = &clk_regmap_gate_ops,
942 .parent_names = (const char *[]){ "mali_1_div" },
943 .num_parents = 1,
944 .flags = CLK_SET_RATE_PARENT,
945 },
946 };
947
948 static const char * const gxbb_mali_parent_names[] = {
949 "mali_0", "mali_1"
950 };
951
952 static struct clk_regmap gxbb_mali = {
953 .data = &(struct clk_regmap_mux_data){
954 .offset = HHI_MALI_CLK_CNTL,
955 .mask = 1,
956 .shift = 31,
957 },
958 .hw.init = &(struct clk_init_data){
959 .name = "mali",
960 .ops = &clk_regmap_mux_ops,
961 .parent_names = gxbb_mali_parent_names,
962 .num_parents = 2,
963 .flags = CLK_SET_RATE_NO_REPARENT,
964 },
965 };
966
967 static struct clk_regmap gxbb_cts_amclk_sel = {
968 .data = &(struct clk_regmap_mux_data){
969 .offset = HHI_AUD_CLK_CNTL,
970 .mask = 0x3,
971 .shift = 9,
972 .table = (u32[]){ 1, 2, 3 },
973 },
974 .hw.init = &(struct clk_init_data){
975 .name = "cts_amclk_sel",
976 .ops = &clk_regmap_mux_ops,
977 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
978 .num_parents = 3,
979 .flags = CLK_SET_RATE_PARENT,
980 },
981 };
982
983 static struct clk_regmap gxbb_cts_amclk_div = {
984 .data = &(struct meson_clk_audio_div_data){
985 .div = {
986 .reg_off = HHI_AUD_CLK_CNTL,
987 .shift = 0,
988 .width = 8,
989 },
990 .flags = CLK_DIVIDER_ROUND_CLOSEST,
991 },
992 .hw.init = &(struct clk_init_data){
993 .name = "cts_amclk_div",
994 .ops = &meson_clk_audio_divider_ops,
995 .parent_names = (const char *[]){ "cts_amclk_sel" },
996 .num_parents = 1,
997 .flags = CLK_SET_RATE_PARENT,
998 },
999 };
1000
1001 static struct clk_regmap gxbb_cts_amclk = {
1002 .data = &(struct clk_regmap_gate_data){
1003 .offset = HHI_AUD_CLK_CNTL,
1004 .bit_idx = 8,
1005 },
1006 .hw.init = &(struct clk_init_data){
1007 .name = "cts_amclk",
1008 .ops = &clk_regmap_gate_ops,
1009 .parent_names = (const char *[]){ "cts_amclk_div" },
1010 .num_parents = 1,
1011 .flags = CLK_SET_RATE_PARENT,
1012 },
1013 };
1014
1015 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1016 .data = &(struct clk_regmap_mux_data){
1017 .offset = HHI_AUD_CLK_CNTL2,
1018 .mask = 0x3,
1019 .shift = 25,
1020 .table = (u32[]){ 1, 2, 3 },
1021 },
1022 .hw.init = &(struct clk_init_data) {
1023 .name = "cts_mclk_i958_sel",
1024 .ops = &clk_regmap_mux_ops,
1025 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1026 .num_parents = 3,
1027 .flags = CLK_SET_RATE_PARENT,
1028 },
1029 };
1030
1031 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1032 .data = &(struct clk_regmap_div_data){
1033 .offset = HHI_AUD_CLK_CNTL2,
1034 .shift = 16,
1035 .width = 8,
1036 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1037 },
1038 .hw.init = &(struct clk_init_data) {
1039 .name = "cts_mclk_i958_div",
1040 .ops = &clk_regmap_divider_ops,
1041 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
1042 .num_parents = 1,
1043 .flags = CLK_SET_RATE_PARENT,
1044 },
1045 };
1046
1047 static struct clk_regmap gxbb_cts_mclk_i958 = {
1048 .data = &(struct clk_regmap_gate_data){
1049 .offset = HHI_AUD_CLK_CNTL2,
1050 .bit_idx = 24,
1051 },
1052 .hw.init = &(struct clk_init_data){
1053 .name = "cts_mclk_i958",
1054 .ops = &clk_regmap_gate_ops,
1055 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
1056 .num_parents = 1,
1057 .flags = CLK_SET_RATE_PARENT,
1058 },
1059 };
1060
1061 static struct clk_regmap gxbb_cts_i958 = {
1062 .data = &(struct clk_regmap_mux_data){
1063 .offset = HHI_AUD_CLK_CNTL2,
1064 .mask = 0x1,
1065 .shift = 27,
1066 },
1067 .hw.init = &(struct clk_init_data){
1068 .name = "cts_i958",
1069 .ops = &clk_regmap_mux_ops,
1070 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
1071 .num_parents = 2,
1072 /*
1073 *The parent is specific to origin of the audio data. Let the
1074 * consumer choose the appropriate parent
1075 */
1076 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1077 },
1078 };
1079
1080 static struct clk_regmap gxbb_32k_clk_div = {
1081 .data = &(struct clk_regmap_div_data){
1082 .offset = HHI_32K_CLK_CNTL,
1083 .shift = 0,
1084 .width = 14,
1085 },
1086 .hw.init = &(struct clk_init_data){
1087 .name = "32k_clk_div",
1088 .ops = &clk_regmap_divider_ops,
1089 .parent_names = (const char *[]){ "32k_clk_sel" },
1090 .num_parents = 1,
1091 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1092 },
1093 };
1094
1095 static struct clk_regmap gxbb_32k_clk = {
1096 .data = &(struct clk_regmap_gate_data){
1097 .offset = HHI_32K_CLK_CNTL,
1098 .bit_idx = 15,
1099 },
1100 .hw.init = &(struct clk_init_data){
1101 .name = "32k_clk",
1102 .ops = &clk_regmap_gate_ops,
1103 .parent_names = (const char *[]){ "32k_clk_div" },
1104 .num_parents = 1,
1105 .flags = CLK_SET_RATE_PARENT,
1106 },
1107 };
1108
1109 static const char * const gxbb_32k_clk_parent_names[] = {
1110 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1111 };
1112
1113 static struct clk_regmap gxbb_32k_clk_sel = {
1114 .data = &(struct clk_regmap_mux_data){
1115 .offset = HHI_32K_CLK_CNTL,
1116 .mask = 0x3,
1117 .shift = 16,
1118 },
1119 .hw.init = &(struct clk_init_data){
1120 .name = "32k_clk_sel",
1121 .ops = &clk_regmap_mux_ops,
1122 .parent_names = gxbb_32k_clk_parent_names,
1123 .num_parents = 4,
1124 .flags = CLK_SET_RATE_PARENT,
1125 },
1126 };
1127
1128 static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1129 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1130
1131 /*
1132 * Following these parent clocks, we should also have had mpll2, mpll3
1133 * and gp0_pll but these clocks are too precious to be used here. All
1134 * the necessary rates for MMC and NAND operation can be acheived using
1135 * xtal or fclk_div clocks
1136 */
1137 };
1138
1139 /* SDIO clock */
1140 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1141 .data = &(struct clk_regmap_mux_data){
1142 .offset = HHI_SD_EMMC_CLK_CNTL,
1143 .mask = 0x7,
1144 .shift = 9,
1145 },
1146 .hw.init = &(struct clk_init_data) {
1147 .name = "sd_emmc_a_clk0_sel",
1148 .ops = &clk_regmap_mux_ops,
1149 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1150 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1151 .flags = CLK_SET_RATE_PARENT,
1152 },
1153 };
1154
1155 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1156 .data = &(struct clk_regmap_div_data){
1157 .offset = HHI_SD_EMMC_CLK_CNTL,
1158 .shift = 0,
1159 .width = 7,
1160 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1161 },
1162 .hw.init = &(struct clk_init_data) {
1163 .name = "sd_emmc_a_clk0_div",
1164 .ops = &clk_regmap_divider_ops,
1165 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1166 .num_parents = 1,
1167 .flags = CLK_SET_RATE_PARENT,
1168 },
1169 };
1170
1171 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1172 .data = &(struct clk_regmap_gate_data){
1173 .offset = HHI_SD_EMMC_CLK_CNTL,
1174 .bit_idx = 7,
1175 },
1176 .hw.init = &(struct clk_init_data){
1177 .name = "sd_emmc_a_clk0",
1178 .ops = &clk_regmap_gate_ops,
1179 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1180 .num_parents = 1,
1181 .flags = CLK_SET_RATE_PARENT,
1182 },
1183 };
1184
1185 /* SDcard clock */
1186 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1187 .data = &(struct clk_regmap_mux_data){
1188 .offset = HHI_SD_EMMC_CLK_CNTL,
1189 .mask = 0x7,
1190 .shift = 25,
1191 },
1192 .hw.init = &(struct clk_init_data) {
1193 .name = "sd_emmc_b_clk0_sel",
1194 .ops = &clk_regmap_mux_ops,
1195 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1196 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1197 .flags = CLK_SET_RATE_PARENT,
1198 },
1199 };
1200
1201 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1202 .data = &(struct clk_regmap_div_data){
1203 .offset = HHI_SD_EMMC_CLK_CNTL,
1204 .shift = 16,
1205 .width = 7,
1206 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1207 },
1208 .hw.init = &(struct clk_init_data) {
1209 .name = "sd_emmc_b_clk0_div",
1210 .ops = &clk_regmap_divider_ops,
1211 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1212 .num_parents = 1,
1213 .flags = CLK_SET_RATE_PARENT,
1214 },
1215 };
1216
1217 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1218 .data = &(struct clk_regmap_gate_data){
1219 .offset = HHI_SD_EMMC_CLK_CNTL,
1220 .bit_idx = 23,
1221 },
1222 .hw.init = &(struct clk_init_data){
1223 .name = "sd_emmc_b_clk0",
1224 .ops = &clk_regmap_gate_ops,
1225 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1226 .num_parents = 1,
1227 .flags = CLK_SET_RATE_PARENT,
1228 },
1229 };
1230
1231 /* EMMC/NAND clock */
1232 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1233 .data = &(struct clk_regmap_mux_data){
1234 .offset = HHI_NAND_CLK_CNTL,
1235 .mask = 0x7,
1236 .shift = 9,
1237 },
1238 .hw.init = &(struct clk_init_data) {
1239 .name = "sd_emmc_c_clk0_sel",
1240 .ops = &clk_regmap_mux_ops,
1241 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1242 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1243 .flags = CLK_SET_RATE_PARENT,
1244 },
1245 };
1246
1247 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1248 .data = &(struct clk_regmap_div_data){
1249 .offset = HHI_NAND_CLK_CNTL,
1250 .shift = 0,
1251 .width = 7,
1252 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1253 },
1254 .hw.init = &(struct clk_init_data) {
1255 .name = "sd_emmc_c_clk0_div",
1256 .ops = &clk_regmap_divider_ops,
1257 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1258 .num_parents = 1,
1259 .flags = CLK_SET_RATE_PARENT,
1260 },
1261 };
1262
1263 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1264 .data = &(struct clk_regmap_gate_data){
1265 .offset = HHI_NAND_CLK_CNTL,
1266 .bit_idx = 7,
1267 },
1268 .hw.init = &(struct clk_init_data){
1269 .name = "sd_emmc_c_clk0",
1270 .ops = &clk_regmap_gate_ops,
1271 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1272 .num_parents = 1,
1273 .flags = CLK_SET_RATE_PARENT,
1274 },
1275 };
1276
1277 /* VPU Clock */
1278
1279 static const char * const gxbb_vpu_parent_names[] = {
1280 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1281 };
1282
1283 static struct clk_regmap gxbb_vpu_0_sel = {
1284 .data = &(struct clk_regmap_mux_data){
1285 .offset = HHI_VPU_CLK_CNTL,
1286 .mask = 0x3,
1287 .shift = 9,
1288 },
1289 .hw.init = &(struct clk_init_data){
1290 .name = "vpu_0_sel",
1291 .ops = &clk_regmap_mux_ops,
1292 /*
1293 * bits 9:10 selects from 4 possible parents:
1294 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1295 */
1296 .parent_names = gxbb_vpu_parent_names,
1297 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1298 .flags = CLK_SET_RATE_NO_REPARENT,
1299 },
1300 };
1301
1302 static struct clk_regmap gxbb_vpu_0_div = {
1303 .data = &(struct clk_regmap_div_data){
1304 .offset = HHI_VPU_CLK_CNTL,
1305 .shift = 0,
1306 .width = 7,
1307 },
1308 .hw.init = &(struct clk_init_data){
1309 .name = "vpu_0_div",
1310 .ops = &clk_regmap_divider_ops,
1311 .parent_names = (const char *[]){ "vpu_0_sel" },
1312 .num_parents = 1,
1313 .flags = CLK_SET_RATE_PARENT,
1314 },
1315 };
1316
1317 static struct clk_regmap gxbb_vpu_0 = {
1318 .data = &(struct clk_regmap_gate_data){
1319 .offset = HHI_VPU_CLK_CNTL,
1320 .bit_idx = 8,
1321 },
1322 .hw.init = &(struct clk_init_data) {
1323 .name = "vpu_0",
1324 .ops = &clk_regmap_gate_ops,
1325 .parent_names = (const char *[]){ "vpu_0_div" },
1326 .num_parents = 1,
1327 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1328 },
1329 };
1330
1331 static struct clk_regmap gxbb_vpu_1_sel = {
1332 .data = &(struct clk_regmap_mux_data){
1333 .offset = HHI_VPU_CLK_CNTL,
1334 .mask = 0x3,
1335 .shift = 25,
1336 },
1337 .hw.init = &(struct clk_init_data){
1338 .name = "vpu_1_sel",
1339 .ops = &clk_regmap_mux_ops,
1340 /*
1341 * bits 25:26 selects from 4 possible parents:
1342 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1343 */
1344 .parent_names = gxbb_vpu_parent_names,
1345 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1346 .flags = CLK_SET_RATE_NO_REPARENT,
1347 },
1348 };
1349
1350 static struct clk_regmap gxbb_vpu_1_div = {
1351 .data = &(struct clk_regmap_div_data){
1352 .offset = HHI_VPU_CLK_CNTL,
1353 .shift = 16,
1354 .width = 7,
1355 },
1356 .hw.init = &(struct clk_init_data){
1357 .name = "vpu_1_div",
1358 .ops = &clk_regmap_divider_ops,
1359 .parent_names = (const char *[]){ "vpu_1_sel" },
1360 .num_parents = 1,
1361 .flags = CLK_SET_RATE_PARENT,
1362 },
1363 };
1364
1365 static struct clk_regmap gxbb_vpu_1 = {
1366 .data = &(struct clk_regmap_gate_data){
1367 .offset = HHI_VPU_CLK_CNTL,
1368 .bit_idx = 24,
1369 },
1370 .hw.init = &(struct clk_init_data) {
1371 .name = "vpu_1",
1372 .ops = &clk_regmap_gate_ops,
1373 .parent_names = (const char *[]){ "vpu_1_div" },
1374 .num_parents = 1,
1375 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1376 },
1377 };
1378
1379 static struct clk_regmap gxbb_vpu = {
1380 .data = &(struct clk_regmap_mux_data){
1381 .offset = HHI_VPU_CLK_CNTL,
1382 .mask = 1,
1383 .shift = 31,
1384 },
1385 .hw.init = &(struct clk_init_data){
1386 .name = "vpu",
1387 .ops = &clk_regmap_mux_ops,
1388 /*
1389 * bit 31 selects from 2 possible parents:
1390 * vpu_0 or vpu_1
1391 */
1392 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1393 .num_parents = 2,
1394 .flags = CLK_SET_RATE_NO_REPARENT,
1395 },
1396 };
1397
1398 /* VAPB Clock */
1399
1400 static const char * const gxbb_vapb_parent_names[] = {
1401 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1402 };
1403
1404 static struct clk_regmap gxbb_vapb_0_sel = {
1405 .data = &(struct clk_regmap_mux_data){
1406 .offset = HHI_VAPBCLK_CNTL,
1407 .mask = 0x3,
1408 .shift = 9,
1409 },
1410 .hw.init = &(struct clk_init_data){
1411 .name = "vapb_0_sel",
1412 .ops = &clk_regmap_mux_ops,
1413 /*
1414 * bits 9:10 selects from 4 possible parents:
1415 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1416 */
1417 .parent_names = gxbb_vapb_parent_names,
1418 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1419 .flags = CLK_SET_RATE_NO_REPARENT,
1420 },
1421 };
1422
1423 static struct clk_regmap gxbb_vapb_0_div = {
1424 .data = &(struct clk_regmap_div_data){
1425 .offset = HHI_VAPBCLK_CNTL,
1426 .shift = 0,
1427 .width = 7,
1428 },
1429 .hw.init = &(struct clk_init_data){
1430 .name = "vapb_0_div",
1431 .ops = &clk_regmap_divider_ops,
1432 .parent_names = (const char *[]){ "vapb_0_sel" },
1433 .num_parents = 1,
1434 .flags = CLK_SET_RATE_PARENT,
1435 },
1436 };
1437
1438 static struct clk_regmap gxbb_vapb_0 = {
1439 .data = &(struct clk_regmap_gate_data){
1440 .offset = HHI_VAPBCLK_CNTL,
1441 .bit_idx = 8,
1442 },
1443 .hw.init = &(struct clk_init_data) {
1444 .name = "vapb_0",
1445 .ops = &clk_regmap_gate_ops,
1446 .parent_names = (const char *[]){ "vapb_0_div" },
1447 .num_parents = 1,
1448 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1449 },
1450 };
1451
1452 static struct clk_regmap gxbb_vapb_1_sel = {
1453 .data = &(struct clk_regmap_mux_data){
1454 .offset = HHI_VAPBCLK_CNTL,
1455 .mask = 0x3,
1456 .shift = 25,
1457 },
1458 .hw.init = &(struct clk_init_data){
1459 .name = "vapb_1_sel",
1460 .ops = &clk_regmap_mux_ops,
1461 /*
1462 * bits 25:26 selects from 4 possible parents:
1463 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1464 */
1465 .parent_names = gxbb_vapb_parent_names,
1466 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1467 .flags = CLK_SET_RATE_NO_REPARENT,
1468 },
1469 };
1470
1471 static struct clk_regmap gxbb_vapb_1_div = {
1472 .data = &(struct clk_regmap_div_data){
1473 .offset = HHI_VAPBCLK_CNTL,
1474 .shift = 16,
1475 .width = 7,
1476 },
1477 .hw.init = &(struct clk_init_data){
1478 .name = "vapb_1_div",
1479 .ops = &clk_regmap_divider_ops,
1480 .parent_names = (const char *[]){ "vapb_1_sel" },
1481 .num_parents = 1,
1482 .flags = CLK_SET_RATE_PARENT,
1483 },
1484 };
1485
1486 static struct clk_regmap gxbb_vapb_1 = {
1487 .data = &(struct clk_regmap_gate_data){
1488 .offset = HHI_VAPBCLK_CNTL,
1489 .bit_idx = 24,
1490 },
1491 .hw.init = &(struct clk_init_data) {
1492 .name = "vapb_1",
1493 .ops = &clk_regmap_gate_ops,
1494 .parent_names = (const char *[]){ "vapb_1_div" },
1495 .num_parents = 1,
1496 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1497 },
1498 };
1499
1500 static struct clk_regmap gxbb_vapb_sel = {
1501 .data = &(struct clk_regmap_mux_data){
1502 .offset = HHI_VAPBCLK_CNTL,
1503 .mask = 1,
1504 .shift = 31,
1505 },
1506 .hw.init = &(struct clk_init_data){
1507 .name = "vapb_sel",
1508 .ops = &clk_regmap_mux_ops,
1509 /*
1510 * bit 31 selects from 2 possible parents:
1511 * vapb_0 or vapb_1
1512 */
1513 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1514 .num_parents = 2,
1515 .flags = CLK_SET_RATE_NO_REPARENT,
1516 },
1517 };
1518
1519 static struct clk_regmap gxbb_vapb = {
1520 .data = &(struct clk_regmap_gate_data){
1521 .offset = HHI_VAPBCLK_CNTL,
1522 .bit_idx = 30,
1523 },
1524 .hw.init = &(struct clk_init_data) {
1525 .name = "vapb",
1526 .ops = &clk_regmap_gate_ops,
1527 .parent_names = (const char *[]){ "vapb_sel" },
1528 .num_parents = 1,
1529 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1530 },
1531 };
1532
1533 /* VDEC clocks */
1534
1535 static const char * const gxbb_vdec_parent_names[] = {
1536 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1537 };
1538
1539 static struct clk_regmap gxbb_vdec_1_sel = {
1540 .data = &(struct clk_regmap_mux_data){
1541 .offset = HHI_VDEC_CLK_CNTL,
1542 .mask = 0x3,
1543 .shift = 9,
1544 .flags = CLK_MUX_ROUND_CLOSEST,
1545 },
1546 .hw.init = &(struct clk_init_data){
1547 .name = "vdec_1_sel",
1548 .ops = &clk_regmap_mux_ops,
1549 .parent_names = gxbb_vdec_parent_names,
1550 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1551 .flags = CLK_SET_RATE_PARENT,
1552 },
1553 };
1554
1555 static struct clk_regmap gxbb_vdec_1_div = {
1556 .data = &(struct clk_regmap_div_data){
1557 .offset = HHI_VDEC_CLK_CNTL,
1558 .shift = 0,
1559 .width = 7,
1560 },
1561 .hw.init = &(struct clk_init_data){
1562 .name = "vdec_1_div",
1563 .ops = &clk_regmap_divider_ops,
1564 .parent_names = (const char *[]){ "vdec_1_sel" },
1565 .num_parents = 1,
1566 .flags = CLK_SET_RATE_PARENT,
1567 },
1568 };
1569
1570 static struct clk_regmap gxbb_vdec_1 = {
1571 .data = &(struct clk_regmap_gate_data){
1572 .offset = HHI_VDEC_CLK_CNTL,
1573 .bit_idx = 8,
1574 },
1575 .hw.init = &(struct clk_init_data) {
1576 .name = "vdec_1",
1577 .ops = &clk_regmap_gate_ops,
1578 .parent_names = (const char *[]){ "vdec_1_div" },
1579 .num_parents = 1,
1580 .flags = CLK_SET_RATE_PARENT,
1581 },
1582 };
1583
1584 static struct clk_regmap gxbb_vdec_hevc_sel = {
1585 .data = &(struct clk_regmap_mux_data){
1586 .offset = HHI_VDEC2_CLK_CNTL,
1587 .mask = 0x3,
1588 .shift = 25,
1589 .flags = CLK_MUX_ROUND_CLOSEST,
1590 },
1591 .hw.init = &(struct clk_init_data){
1592 .name = "vdec_hevc_sel",
1593 .ops = &clk_regmap_mux_ops,
1594 .parent_names = gxbb_vdec_parent_names,
1595 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1596 .flags = CLK_SET_RATE_PARENT,
1597 },
1598 };
1599
1600 static struct clk_regmap gxbb_vdec_hevc_div = {
1601 .data = &(struct clk_regmap_div_data){
1602 .offset = HHI_VDEC2_CLK_CNTL,
1603 .shift = 16,
1604 .width = 7,
1605 },
1606 .hw.init = &(struct clk_init_data){
1607 .name = "vdec_hevc_div",
1608 .ops = &clk_regmap_divider_ops,
1609 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1610 .num_parents = 1,
1611 .flags = CLK_SET_RATE_PARENT,
1612 },
1613 };
1614
1615 static struct clk_regmap gxbb_vdec_hevc = {
1616 .data = &(struct clk_regmap_gate_data){
1617 .offset = HHI_VDEC2_CLK_CNTL,
1618 .bit_idx = 24,
1619 },
1620 .hw.init = &(struct clk_init_data) {
1621 .name = "vdec_hevc",
1622 .ops = &clk_regmap_gate_ops,
1623 .parent_names = (const char *[]){ "vdec_hevc_div" },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 },
1627 };
1628
1629 /* Everything Else (EE) domain gates */
1630 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1631 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1632 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1633 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1634 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1635 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1636 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1637 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
1638 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1639 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1640 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1641 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1642 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1643 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1644 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1645 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1646 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1647 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1648 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1649 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1650 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1651 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1652
1653 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1654 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1655 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1656 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1657 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1658 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1659 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1660 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1661 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1662 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1663 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1664 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1665 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1666 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1667 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1668 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1669 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1670 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1671 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1672 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1673 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1674 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1675 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1676 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1677 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
1678
1679 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1680 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1681 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1682 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1683 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1684 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1685 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1686 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1687 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1688 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
1689 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1690 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1691 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
1692
1693 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1694 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1695 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1696 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1697 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1698 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1699 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1700 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1701 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1702 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1703 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1704 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1705 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1706 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1707 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1708 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
1709
1710 /* Always On (AO) domain gates */
1711
1712 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1713 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1714 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1715 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1716 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
1717
1718 /* Array of all clocks provided by this provider */
1719
1720 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1721 .hws = {
1722 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1723 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1724 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1725 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1726 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1727 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1728 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1729 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1730 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1731 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1732 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1733 [CLKID_CLK81] = &gxbb_clk81.hw,
1734 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1735 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1736 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1737 [CLKID_DDR] = &gxbb_ddr.hw,
1738 [CLKID_DOS] = &gxbb_dos.hw,
1739 [CLKID_ISA] = &gxbb_isa.hw,
1740 [CLKID_PL301] = &gxbb_pl301.hw,
1741 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1742 [CLKID_SPICC] = &gxbb_spicc.hw,
1743 [CLKID_I2C] = &gxbb_i2c.hw,
1744 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1745 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1746 [CLKID_RNG0] = &gxbb_rng0.hw,
1747 [CLKID_UART0] = &gxbb_uart0.hw,
1748 [CLKID_SDHC] = &gxbb_sdhc.hw,
1749 [CLKID_STREAM] = &gxbb_stream.hw,
1750 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1751 [CLKID_SDIO] = &gxbb_sdio.hw,
1752 [CLKID_ABUF] = &gxbb_abuf.hw,
1753 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1754 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1755 [CLKID_SPI] = &gxbb_spi.hw,
1756 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1757 [CLKID_ETH] = &gxbb_eth.hw,
1758 [CLKID_DEMUX] = &gxbb_demux.hw,
1759 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1760 [CLKID_IEC958] = &gxbb_iec958.hw,
1761 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1762 [CLKID_AMCLK] = &gxbb_amclk.hw,
1763 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1764 [CLKID_MIXER] = &gxbb_mixer.hw,
1765 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1766 [CLKID_ADC] = &gxbb_adc.hw,
1767 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1768 [CLKID_AIU] = &gxbb_aiu.hw,
1769 [CLKID_UART1] = &gxbb_uart1.hw,
1770 [CLKID_G2D] = &gxbb_g2d.hw,
1771 [CLKID_USB0] = &gxbb_usb0.hw,
1772 [CLKID_USB1] = &gxbb_usb1.hw,
1773 [CLKID_RESET] = &gxbb_reset.hw,
1774 [CLKID_NAND] = &gxbb_nand.hw,
1775 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1776 [CLKID_USB] = &gxbb_usb.hw,
1777 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1778 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1779 [CLKID_EFUSE] = &gxbb_efuse.hw,
1780 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1781 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1782 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1783 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1784 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1785 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1786 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1787 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1788 [CLKID_DVIN] = &gxbb_dvin.hw,
1789 [CLKID_UART2] = &gxbb_uart2.hw,
1790 [CLKID_SANA] = &gxbb_sana.hw,
1791 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1792 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1793 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1794 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1795 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1796 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1797 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1798 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1799 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1800 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1801 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1802 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1803 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1804 [CLKID_RNG1] = &gxbb_rng1.hw,
1805 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1806 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1807 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1808 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1809 [CLKID_EDP] = &gxbb_edp.hw,
1810 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1811 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1812 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1813 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1814 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1815 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1816 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1817 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1818 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1819 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1820 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1821 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1822 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1823 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1824 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1825 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1826 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1827 [CLKID_MALI] = &gxbb_mali.hw,
1828 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1829 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1830 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1831 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1832 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1833 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1834 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1835 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1836 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1837 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
1838 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1839 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1840 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1841 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1842 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1843 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1844 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1845 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1846 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1847 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1848 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1849 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1850 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1851 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1852 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1853 [CLKID_VPU] = &gxbb_vpu.hw,
1854 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1855 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1856 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1857 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1858 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1859 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1860 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1861 [CLKID_VAPB] = &gxbb_vapb.hw,
1862 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
1863 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
1864 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
1865 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
1866 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1867 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1868 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1869 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1870 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1871 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1872 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
1873 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
1874 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
1875 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
1876 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
1877 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
1878 [NR_CLKS] = NULL,
1879 },
1880 .num = NR_CLKS,
1881 };
1882
1883 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1884 .hws = {
1885 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1886 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
1887 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1888 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1889 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1890 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1891 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1892 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1893 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw,
1894 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1895 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1896 [CLKID_CLK81] = &gxbb_clk81.hw,
1897 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1898 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1899 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1900 [CLKID_DDR] = &gxbb_ddr.hw,
1901 [CLKID_DOS] = &gxbb_dos.hw,
1902 [CLKID_ISA] = &gxbb_isa.hw,
1903 [CLKID_PL301] = &gxbb_pl301.hw,
1904 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1905 [CLKID_SPICC] = &gxbb_spicc.hw,
1906 [CLKID_I2C] = &gxbb_i2c.hw,
1907 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1908 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1909 [CLKID_RNG0] = &gxbb_rng0.hw,
1910 [CLKID_UART0] = &gxbb_uart0.hw,
1911 [CLKID_SDHC] = &gxbb_sdhc.hw,
1912 [CLKID_STREAM] = &gxbb_stream.hw,
1913 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1914 [CLKID_SDIO] = &gxbb_sdio.hw,
1915 [CLKID_ABUF] = &gxbb_abuf.hw,
1916 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1917 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1918 [CLKID_SPI] = &gxbb_spi.hw,
1919 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1920 [CLKID_ETH] = &gxbb_eth.hw,
1921 [CLKID_DEMUX] = &gxbb_demux.hw,
1922 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1923 [CLKID_IEC958] = &gxbb_iec958.hw,
1924 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1925 [CLKID_AMCLK] = &gxbb_amclk.hw,
1926 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1927 [CLKID_MIXER] = &gxbb_mixer.hw,
1928 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1929 [CLKID_ADC] = &gxbb_adc.hw,
1930 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1931 [CLKID_AIU] = &gxbb_aiu.hw,
1932 [CLKID_UART1] = &gxbb_uart1.hw,
1933 [CLKID_G2D] = &gxbb_g2d.hw,
1934 [CLKID_USB0] = &gxbb_usb0.hw,
1935 [CLKID_USB1] = &gxbb_usb1.hw,
1936 [CLKID_RESET] = &gxbb_reset.hw,
1937 [CLKID_NAND] = &gxbb_nand.hw,
1938 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1939 [CLKID_USB] = &gxbb_usb.hw,
1940 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1941 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1942 [CLKID_EFUSE] = &gxbb_efuse.hw,
1943 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1944 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1945 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1946 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1947 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1948 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1949 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1950 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1951 [CLKID_DVIN] = &gxbb_dvin.hw,
1952 [CLKID_UART2] = &gxbb_uart2.hw,
1953 [CLKID_SANA] = &gxbb_sana.hw,
1954 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1955 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1956 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1957 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1958 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1959 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1960 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1961 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1962 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1963 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1964 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1965 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1966 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1967 [CLKID_RNG1] = &gxbb_rng1.hw,
1968 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1969 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1970 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1971 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1972 [CLKID_EDP] = &gxbb_edp.hw,
1973 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1974 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1975 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1976 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1977 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1978 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1979 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1980 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1981 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1982 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1983 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1984 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1985 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1986 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1987 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1988 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1989 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1990 [CLKID_MALI] = &gxbb_mali.hw,
1991 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1992 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1993 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1994 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1995 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1996 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1997 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1998 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1999 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
2000 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
2001 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
2002 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
2003 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
2004 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
2005 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
2006 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
2007 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
2008 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
2009 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
2010 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
2011 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
2012 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
2013 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
2014 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
2015 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
2016 [CLKID_VPU] = &gxbb_vpu.hw,
2017 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
2018 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
2019 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
2020 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
2021 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
2022 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2023 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2024 [CLKID_VAPB] = &gxbb_vapb.hw,
2025 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
2026 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2027 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2028 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
2029 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
2030 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
2031 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
2032 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
2033 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2034 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2035 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2036 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2037 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2038 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2039 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
2040 [NR_CLKS] = NULL,
2041 },
2042 .num = NR_CLKS,
2043 };
2044
2045 static struct clk_regmap *const gxbb_clk_regmaps[] = {
2046 &gxbb_gp0_pll,
2047 &gxbb_hdmi_pll,
2048 };
2049
2050 static struct clk_regmap *const gxl_clk_regmaps[] = {
2051 &gxl_gp0_pll,
2052 &gxl_hdmi_pll,
2053 };
2054
2055 static struct clk_regmap *const gx_clk_regmaps[] = {
2056 &gxbb_clk81,
2057 &gxbb_ddr,
2058 &gxbb_dos,
2059 &gxbb_isa,
2060 &gxbb_pl301,
2061 &gxbb_periphs,
2062 &gxbb_spicc,
2063 &gxbb_i2c,
2064 &gxbb_sar_adc,
2065 &gxbb_smart_card,
2066 &gxbb_rng0,
2067 &gxbb_uart0,
2068 &gxbb_sdhc,
2069 &gxbb_stream,
2070 &gxbb_async_fifo,
2071 &gxbb_sdio,
2072 &gxbb_abuf,
2073 &gxbb_hiu_iface,
2074 &gxbb_assist_misc,
2075 &gxbb_spi,
2076 &gxbb_i2s_spdif,
2077 &gxbb_eth,
2078 &gxbb_demux,
2079 &gxbb_aiu_glue,
2080 &gxbb_iec958,
2081 &gxbb_i2s_out,
2082 &gxbb_amclk,
2083 &gxbb_aififo2,
2084 &gxbb_mixer,
2085 &gxbb_mixer_iface,
2086 &gxbb_adc,
2087 &gxbb_blkmv,
2088 &gxbb_aiu,
2089 &gxbb_uart1,
2090 &gxbb_g2d,
2091 &gxbb_usb0,
2092 &gxbb_usb1,
2093 &gxbb_reset,
2094 &gxbb_nand,
2095 &gxbb_dos_parser,
2096 &gxbb_usb,
2097 &gxbb_vdin1,
2098 &gxbb_ahb_arb0,
2099 &gxbb_efuse,
2100 &gxbb_boot_rom,
2101 &gxbb_ahb_data_bus,
2102 &gxbb_ahb_ctrl_bus,
2103 &gxbb_hdmi_intr_sync,
2104 &gxbb_hdmi_pclk,
2105 &gxbb_usb1_ddr_bridge,
2106 &gxbb_usb0_ddr_bridge,
2107 &gxbb_mmc_pclk,
2108 &gxbb_dvin,
2109 &gxbb_uart2,
2110 &gxbb_sana,
2111 &gxbb_vpu_intr,
2112 &gxbb_sec_ahb_ahb3_bridge,
2113 &gxbb_clk81_a53,
2114 &gxbb_vclk2_venci0,
2115 &gxbb_vclk2_venci1,
2116 &gxbb_vclk2_vencp0,
2117 &gxbb_vclk2_vencp1,
2118 &gxbb_gclk_venci_int0,
2119 &gxbb_gclk_vencp_int,
2120 &gxbb_dac_clk,
2121 &gxbb_aoclk_gate,
2122 &gxbb_iec958_gate,
2123 &gxbb_enc480p,
2124 &gxbb_rng1,
2125 &gxbb_gclk_venci_int1,
2126 &gxbb_vclk2_venclmcc,
2127 &gxbb_vclk2_vencl,
2128 &gxbb_vclk_other,
2129 &gxbb_edp,
2130 &gxbb_ao_media_cpu,
2131 &gxbb_ao_ahb_sram,
2132 &gxbb_ao_ahb_bus,
2133 &gxbb_ao_iface,
2134 &gxbb_ao_i2c,
2135 &gxbb_emmc_a,
2136 &gxbb_emmc_b,
2137 &gxbb_emmc_c,
2138 &gxbb_sar_adc_clk,
2139 &gxbb_mali_0,
2140 &gxbb_mali_1,
2141 &gxbb_cts_amclk,
2142 &gxbb_cts_mclk_i958,
2143 &gxbb_32k_clk,
2144 &gxbb_sd_emmc_a_clk0,
2145 &gxbb_sd_emmc_b_clk0,
2146 &gxbb_sd_emmc_c_clk0,
2147 &gxbb_vpu_0,
2148 &gxbb_vpu_1,
2149 &gxbb_vapb_0,
2150 &gxbb_vapb_1,
2151 &gxbb_vapb,
2152 &gxbb_mpeg_clk_div,
2153 &gxbb_sar_adc_clk_div,
2154 &gxbb_mali_0_div,
2155 &gxbb_mali_1_div,
2156 &gxbb_cts_mclk_i958_div,
2157 &gxbb_32k_clk_div,
2158 &gxbb_sd_emmc_a_clk0_div,
2159 &gxbb_sd_emmc_b_clk0_div,
2160 &gxbb_sd_emmc_c_clk0_div,
2161 &gxbb_vpu_0_div,
2162 &gxbb_vpu_1_div,
2163 &gxbb_vapb_0_div,
2164 &gxbb_vapb_1_div,
2165 &gxbb_mpeg_clk_sel,
2166 &gxbb_sar_adc_clk_sel,
2167 &gxbb_mali_0_sel,
2168 &gxbb_mali_1_sel,
2169 &gxbb_mali,
2170 &gxbb_cts_amclk_sel,
2171 &gxbb_cts_mclk_i958_sel,
2172 &gxbb_cts_i958,
2173 &gxbb_32k_clk_sel,
2174 &gxbb_sd_emmc_a_clk0_sel,
2175 &gxbb_sd_emmc_b_clk0_sel,
2176 &gxbb_sd_emmc_c_clk0_sel,
2177 &gxbb_vpu_0_sel,
2178 &gxbb_vpu_1_sel,
2179 &gxbb_vpu,
2180 &gxbb_vapb_0_sel,
2181 &gxbb_vapb_1_sel,
2182 &gxbb_vapb_sel,
2183 &gxbb_mpll0,
2184 &gxbb_mpll1,
2185 &gxbb_mpll2,
2186 &gxbb_mpll0_div,
2187 &gxbb_mpll1_div,
2188 &gxbb_mpll2_div,
2189 &gxbb_cts_amclk_div,
2190 &gxbb_fixed_pll,
2191 &gxbb_sys_pll,
2192 &gxbb_mpll_prediv,
2193 &gxbb_fclk_div2,
2194 &gxbb_fclk_div3,
2195 &gxbb_fclk_div4,
2196 &gxbb_fclk_div5,
2197 &gxbb_fclk_div7,
2198 &gxbb_vdec_1_sel,
2199 &gxbb_vdec_1_div,
2200 &gxbb_vdec_1,
2201 &gxbb_vdec_hevc_sel,
2202 &gxbb_vdec_hevc_div,
2203 &gxbb_vdec_hevc,
2204 };
2205
2206 struct clkc_data {
2207 struct clk_regmap *const *regmap_clks;
2208 unsigned int regmap_clks_count;
2209 struct clk_hw_onecell_data *hw_onecell_data;
2210 };
2211
2212 static const struct clkc_data gxbb_clkc_data = {
2213 .regmap_clks = gxbb_clk_regmaps,
2214 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
2215 .hw_onecell_data = &gxbb_hw_onecell_data,
2216 };
2217
2218 static const struct clkc_data gxl_clkc_data = {
2219 .regmap_clks = gxl_clk_regmaps,
2220 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
2221 .hw_onecell_data = &gxl_hw_onecell_data,
2222 };
2223
2224 static const struct of_device_id clkc_match_table[] = {
2225 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
2226 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
2227 {},
2228 };
2229
2230 static const struct regmap_config clkc_regmap_config = {
2231 .reg_bits = 32,
2232 .val_bits = 32,
2233 .reg_stride = 4,
2234 };
2235
2236 static int gxbb_clkc_probe(struct platform_device *pdev)
2237 {
2238 const struct clkc_data *clkc_data;
2239 struct resource *res;
2240 void __iomem *clk_base;
2241 struct regmap *map;
2242 int ret, i;
2243 struct device *dev = &pdev->dev;
2244
2245 clkc_data = of_device_get_match_data(dev);
2246 if (!clkc_data)
2247 return -EINVAL;
2248
2249 /* Get the hhi system controller node if available */
2250 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
2251 if (IS_ERR(map)) {
2252 dev_err(dev,
2253 "failed to get HHI regmap - Trying obsolete regs\n");
2254
2255 /*
2256 * FIXME: HHI registers should be accessed through
2257 * the appropriate system controller. This is required because
2258 * there is more than just clocks in this register space
2259 *
2260 * This fallback method is only provided temporarily until
2261 * all the platform DTs are properly using the syscon node
2262 */
2263 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2264 if (!res)
2265 return -EINVAL;
2266
2267 clk_base = devm_ioremap(dev, res->start, resource_size(res));
2268 if (!clk_base) {
2269 dev_err(dev, "Unable to map clk base\n");
2270 return -ENXIO;
2271 }
2272
2273 map = devm_regmap_init_mmio(dev, clk_base,
2274 &clkc_regmap_config);
2275 if (IS_ERR(map))
2276 return PTR_ERR(map);
2277 }
2278
2279 /* Populate regmap for the common regmap backed clocks */
2280 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
2281 gx_clk_regmaps[i]->map = map;
2282
2283 /* Populate regmap for soc specific clocks */
2284 for (i = 0; i < clkc_data->regmap_clks_count; i++)
2285 clkc_data->regmap_clks[i]->map = map;
2286
2287 /* Register all clks */
2288 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
2289 /* array might be sparse */
2290 if (!clkc_data->hw_onecell_data->hws[i])
2291 continue;
2292
2293 ret = devm_clk_hw_register(dev,
2294 clkc_data->hw_onecell_data->hws[i]);
2295 if (ret) {
2296 dev_err(dev, "Clock registration failed\n");
2297 return ret;
2298 }
2299 }
2300
2301 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2302 clkc_data->hw_onecell_data);
2303 }
2304
2305 static struct platform_driver gxbb_driver = {
2306 .probe = gxbb_clkc_probe,
2307 .driver = {
2308 .name = "gxbb-clkc",
2309 .of_match_table = clkc_match_table,
2310 },
2311 };
2312
2313 builtin_platform_driver(gxbb_driver);
Linux with added FPC-III support