drivers/pinctrl/freescale/pinctrl-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Core driver for the imx pin controller
   4 //
   5 // Copyright (C) 2012 Freescale Semiconductor, Inc.
   6 // Copyright (C) 2012 Linaro Ltd.
   7 //
   8 // Author: Dong Aisheng <dong.aisheng@linaro.org>
   9
  10 #include <linux/err.h>
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/pinctrl/machine.h>
  18 #include <linux/pinctrl/pinconf.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/slab.h>
  22 #include <linux/regmap.h>
  23
  24 #include "../core.h"
  25 #include "../pinconf.h"
  26 #include "../pinmux.h"
  27 #include "pinctrl-imx.h"
  28
  29 /* The bits in CONFIG cell defined in binding doc*/
  30 #define IMX_NO_PAD_CTL  0x80000000      /* no pin config need */
  31 #define IMX_PAD_SION 0x40000000         /* set SION */
  32
  33 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
  34                                 struct pinctrl_dev *pctldev,
  35                                 const char *name)
  36 {
  37         const struct group_desc *grp = NULL;
  38         int i;
  39
  40         for (i = 0; i < pctldev->num_groups; i++) {
  41                 grp = pinctrl_generic_get_group(pctldev, i);
  42                 if (grp && !strcmp(grp->name, name))
  43                         break;
  44         }
  45
  46         return grp;
  47 }
  48
  49 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  50                    unsigned offset)
  51 {
  52         seq_printf(s, "%s", dev_name(pctldev->dev));
  53 }
  54
  55 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
  56                         struct device_node *np,
  57                         struct pinctrl_map **map, unsigned *num_maps)
  58 {
  59         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  60         const struct group_desc *grp;
  61         struct pinctrl_map *new_map;
  62         struct device_node *parent;
  63         int map_num = 1;
  64         int i, j;
  65
  66         /*
  67          * first find the group of this node and check if we need create
  68          * config maps for pins
  69          */
  70         grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
  71         if (!grp) {
  72                 dev_err(ipctl->dev, "unable to find group for node %s\n",
  73                         np->name);
  74                 return -EINVAL;
  75         }
  76
  77         for (i = 0; i < grp->num_pins; i++) {
  78                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
  79
  80                 if (!(pin->config & IMX_NO_PAD_CTL))
  81                         map_num++;
  82         }
  83
  84         new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
  85                                 GFP_KERNEL);
  86         if (!new_map)
  87                 return -ENOMEM;
  88
  89         *map = new_map;
  90         *num_maps = map_num;
  91
  92         /* create mux map */
  93         parent = of_get_parent(np);
  94         if (!parent) {
  95                 kfree(new_map);
  96                 return -EINVAL;
  97         }
  98         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
  99         new_map[0].data.mux.function = parent->name;
 100         new_map[0].data.mux.group = np->name;
 101         of_node_put(parent);
 102
 103         /* create config map */
 104         new_map++;
 105         for (i = j = 0; i < grp->num_pins; i++) {
 106                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 107
 108                 if (!(pin->config & IMX_NO_PAD_CTL)) {
 109                         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
 110                         new_map[j].data.configs.group_or_pin =
 111                                         pin_get_name(pctldev, pin->pin);
 112                         new_map[j].data.configs.configs = &pin->config;
 113                         new_map[j].data.configs.num_configs = 1;
 114                         j++;
 115                 }
 116         }
 117
 118         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 119                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 120
 121         return 0;
 122 }
 123
 124 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
 125                                 struct pinctrl_map *map, unsigned num_maps)
 126 {
 127         kfree(map);
 128 }
 129
 130 static const struct pinctrl_ops imx_pctrl_ops = {
 131         .get_groups_count = pinctrl_generic_get_group_count,
 132         .get_group_name = pinctrl_generic_get_group_name,
 133         .get_group_pins = pinctrl_generic_get_group_pins,
 134         .pin_dbg_show = imx_pin_dbg_show,
 135         .dt_node_to_map = imx_dt_node_to_map,
 136         .dt_free_map = imx_dt_free_map,
 137
 138 };
 139
 140 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 141                        unsigned group)
 142 {
 143         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 144         const struct imx_pinctrl_soc_info *info = ipctl->info;
 145         const struct imx_pin_reg *pin_reg;
 146         unsigned int npins, pin_id;
 147         int i;
 148         struct group_desc *grp = NULL;
 149         struct function_desc *func = NULL;
 150
 151         /*
 152          * Configure the mux mode for each pin in the group for a specific
 153          * function.
 154          */
 155         grp = pinctrl_generic_get_group(pctldev, group);
 156         if (!grp)
 157                 return -EINVAL;
 158
 159         func = pinmux_generic_get_function(pctldev, selector);
 160         if (!func)
 161                 return -EINVAL;
 162
 163         npins = grp->num_pins;
 164
 165         dev_dbg(ipctl->dev, "enable function %s group %s\n",
 166                 func->name, grp->name);
 167
 168         for (i = 0; i < npins; i++) {
 169                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 170
 171                 pin_id = pin->pin;
 172                 pin_reg = &ipctl->pin_regs[pin_id];
 173
 174                 if (pin_reg->mux_reg == -1) {
 175                         dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
 176                                 info->pins[pin_id].name);
 177                         continue;
 178                 }
 179
 180                 if (info->flags & SHARE_MUX_CONF_REG) {
 181                         u32 reg;
 182                         reg = readl(ipctl->base + pin_reg->mux_reg);
 183                         reg &= ~info->mux_mask;
 184                         reg |= (pin->mux_mode << info->mux_shift);
 185                         writel(reg, ipctl->base + pin_reg->mux_reg);
 186                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 187                                 pin_reg->mux_reg, reg);
 188                 } else {
 189                         writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
 190                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 191                                 pin_reg->mux_reg, pin->mux_mode);
 192                 }
 193
 194                 /*
 195                  * If the select input value begins with 0xff, it's a quirky
 196                  * select input and the value should be interpreted as below.
 197                  *     31     23      15      7        0
 198                  *     | 0xff | shift | width | select |
 199                  * It's used to work around the problem that the select
 200                  * input for some pin is not implemented in the select
 201                  * input register but in some general purpose register.
 202                  * We encode the select input value, width and shift of
 203                  * the bit field into input_val cell of pin function ID
 204                  * in device tree, and then decode them here for setting
 205                  * up the select input bits in general purpose register.
 206                  */
 207                 if (pin->input_val >> 24 == 0xff) {
 208                         u32 val = pin->input_val;
 209                         u8 select = val & 0xff;
 210                         u8 width = (val >> 8) & 0xff;
 211                         u8 shift = (val >> 16) & 0xff;
 212                         u32 mask = ((1 << width) - 1) << shift;
 213                         /*
 214                          * The input_reg[i] here is actually some IOMUXC general
 215                          * purpose register, not regular select input register.
 216                          */
 217                         val = readl(ipctl->base + pin->input_reg);
 218                         val &= ~mask;
 219                         val |= select << shift;
 220                         writel(val, ipctl->base + pin->input_reg);
 221                 } else if (pin->input_reg) {
 222                         /*
 223                          * Regular select input register can never be at offset
 224                          * 0, and we only print register value for regular case.
 225                          */
 226                         if (ipctl->input_sel_base)
 227                                 writel(pin->input_val, ipctl->input_sel_base +
 228                                                 pin->input_reg);
 229                         else
 230                                 writel(pin->input_val, ipctl->base +
 231                                                 pin->input_reg);
 232                         dev_dbg(ipctl->dev,
 233                                 "==>select_input: offset 0x%x val 0x%x\n",
 234                                 pin->input_reg, pin->input_val);
 235                 }
 236         }
 237
 238         return 0;
 239 }
 240
 241 struct pinmux_ops imx_pmx_ops = {
 242         .get_functions_count = pinmux_generic_get_function_count,
 243         .get_function_name = pinmux_generic_get_function_name,
 244         .get_function_groups = pinmux_generic_get_function_groups,
 245         .set_mux = imx_pmx_set,
 246 };
 247
 248 /* decode generic config into raw register values */
 249 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
 250                                               unsigned long *configs,
 251                                               unsigned int num_configs)
 252 {
 253         const struct imx_pinctrl_soc_info *info = ipctl->info;
 254         const struct imx_cfg_params_decode *decode;
 255         enum pin_config_param param;
 256         u32 raw_config = 0;
 257         u32 param_val;
 258         int i, j;
 259
 260         WARN_ON(num_configs > info->num_decodes);
 261
 262         for (i = 0; i < num_configs; i++) {
 263                 param = pinconf_to_config_param(configs[i]);
 264                 param_val = pinconf_to_config_argument(configs[i]);
 265                 decode = info->decodes;
 266                 for (j = 0; j < info->num_decodes; j++) {
 267                         if (param == decode->param) {
 268                                 if (decode->invert)
 269                                         param_val = !param_val;
 270                                 raw_config |= (param_val << decode->shift)
 271                                               & decode->mask;
 272                                 break;
 273                         }
 274                         decode++;
 275                 }
 276         }
 277
 278         if (info->fixup)
 279                 info->fixup(configs, num_configs, &raw_config);
 280
 281         return raw_config;
 282 }
 283
 284 static u32 imx_pinconf_parse_generic_config(struct device_node *np,
 285                                             struct imx_pinctrl *ipctl)
 286 {
 287         const struct imx_pinctrl_soc_info *info = ipctl->info;
 288         struct pinctrl_dev *pctl = ipctl->pctl;
 289         unsigned int num_configs;
 290         unsigned long *configs;
 291         int ret;
 292
 293         if (!info->generic_pinconf)
 294                 return 0;
 295
 296         ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
 297                                               &num_configs);
 298         if (ret)
 299                 return 0;
 300
 301         return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
 302 }
 303
 304 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 305                              unsigned pin_id, unsigned long *config)
 306 {
 307         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 308         const struct imx_pinctrl_soc_info *info = ipctl->info;
 309         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 310
 311         if (pin_reg->conf_reg == -1) {
 312                 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
 313                         info->pins[pin_id].name);
 314                 return -EINVAL;
 315         }
 316
 317         *config = readl(ipctl->base + pin_reg->conf_reg);
 318
 319         if (info->flags & SHARE_MUX_CONF_REG)
 320                 *config &= ~info->mux_mask;
 321
 322         return 0;
 323 }
 324
 325 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 326                              unsigned pin_id, unsigned long *configs,
 327                              unsigned num_configs)
 328 {
 329         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 330         const struct imx_pinctrl_soc_info *info = ipctl->info;
 331         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 332         int i;
 333
 334         if (pin_reg->conf_reg == -1) {
 335                 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
 336                         info->pins[pin_id].name);
 337                 return -EINVAL;
 338         }
 339
 340         dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 341                 info->pins[pin_id].name);
 342
 343         for (i = 0; i < num_configs; i++) {
 344                 if (info->flags & SHARE_MUX_CONF_REG) {
 345                         u32 reg;
 346                         reg = readl(ipctl->base + pin_reg->conf_reg);
 347                         reg &= info->mux_mask;
 348                         reg |= configs[i];
 349                         writel(reg, ipctl->base + pin_reg->conf_reg);
 350                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 351                                 pin_reg->conf_reg, reg);
 352                 } else {
 353                         writel(configs[i], ipctl->base + pin_reg->conf_reg);
 354                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 355                                 pin_reg->conf_reg, configs[i]);
 356                 }
 357         } /* for each config */
 358
 359         return 0;
 360 }
 361
 362 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 363                                    struct seq_file *s, unsigned pin_id)
 364 {
 365         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 366         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 367         unsigned long config;
 368
 369         if (!pin_reg || pin_reg->conf_reg == -1) {
 370                 seq_puts(s, "N/A");
 371                 return;
 372         }
 373
 374         config = readl(ipctl->base + pin_reg->conf_reg);
 375         seq_printf(s, "0x%lx", config);
 376 }
 377
 378 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 379                                          struct seq_file *s, unsigned group)
 380 {
 381         struct group_desc *grp;
 382         unsigned long config;
 383         const char *name;
 384         int i, ret;
 385
 386         if (group > pctldev->num_groups)
 387                 return;
 388
 389         seq_puts(s, "\n");
 390         grp = pinctrl_generic_get_group(pctldev, group);
 391         if (!grp)
 392                 return;
 393
 394         for (i = 0; i < grp->num_pins; i++) {
 395                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 396
 397                 name = pin_get_name(pctldev, pin->pin);
 398                 ret = imx_pinconf_get(pctldev, pin->pin, &config);
 399                 if (ret)
 400                         return;
 401                 seq_printf(s, "  %s: 0x%lx\n", name, config);
 402         }
 403 }
 404
 405 static const struct pinconf_ops imx_pinconf_ops = {
 406         .pin_config_get = imx_pinconf_get,
 407         .pin_config_set = imx_pinconf_set,
 408         .pin_config_dbg_show = imx_pinconf_dbg_show,
 409         .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
 410 };
 411
 412 /*
 413  * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
 414  * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
 415  * For generic_pinconf case, there's no extra u32 CONFIG.
 416  *
 417  * PIN_FUNC_ID format:
 418  * Default:
 419  *     <mux_reg conf_reg input_reg mux_mode input_val>
 420  * SHARE_MUX_CONF_REG:
 421  *     <mux_conf_reg input_reg mux_mode input_val>
 422  */
 423 #define FSL_PIN_SIZE 24
 424 #define FSL_PIN_SHARE_SIZE 20
 425
 426 static int imx_pinctrl_parse_groups(struct device_node *np,
 427                                     struct group_desc *grp,
 428                                     struct imx_pinctrl *ipctl,
 429                                     u32 index)
 430 {
 431         const struct imx_pinctrl_soc_info *info = ipctl->info;
 432         int size, pin_size;
 433         const __be32 *list;
 434         int i;
 435         u32 config;
 436
 437         dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
 438
 439         if (info->flags & SHARE_MUX_CONF_REG)
 440                 pin_size = FSL_PIN_SHARE_SIZE;
 441         else
 442                 pin_size = FSL_PIN_SIZE;
 443
 444         if (info->generic_pinconf)
 445                 pin_size -= 4;
 446
 447         /* Initialise group */
 448         grp->name = np->name;
 449
 450         /*
 451          * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
 452          * do sanity check and calculate pins number
 453          *
 454          * First try legacy 'fsl,pins' property, then fall back to the
 455          * generic 'pinmux'.
 456          *
 457          * Note: for generic 'pinmux' case, there's no CONFIG part in
 458          * the binding format.
 459          */
 460         list = of_get_property(np, "fsl,pins", &size);
 461         if (!list) {
 462                 list = of_get_property(np, "pinmux", &size);
 463                 if (!list) {
 464                         dev_err(ipctl->dev,
 465                                 "no fsl,pins and pins property in node %pOF\n", np);
 466                         return -EINVAL;
 467                 }
 468         }
 469
 470         /* we do not check return since it's safe node passed down */
 471         if (!size || size % pin_size) {
 472                 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
 473                 return -EINVAL;
 474         }
 475
 476         /* first try to parse the generic pin config */
 477         config = imx_pinconf_parse_generic_config(np, ipctl);
 478
 479         grp->num_pins = size / pin_size;
 480         grp->data = devm_kcalloc(ipctl->dev,
 481                                  grp->num_pins, sizeof(struct imx_pin),
 482                                  GFP_KERNEL);
 483         grp->pins = devm_kcalloc(ipctl->dev,
 484                                  grp->num_pins, sizeof(unsigned int),
 485                                  GFP_KERNEL);
 486         if (!grp->pins || !grp->data)
 487                 return -ENOMEM;
 488
 489         for (i = 0; i < grp->num_pins; i++) {
 490                 u32 mux_reg = be32_to_cpu(*list++);
 491                 u32 conf_reg;
 492                 unsigned int pin_id;
 493                 struct imx_pin_reg *pin_reg;
 494                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 495
 496                 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
 497                         mux_reg = -1;
 498
 499                 if (info->flags & SHARE_MUX_CONF_REG) {
 500                         conf_reg = mux_reg;
 501                 } else {
 502                         conf_reg = be32_to_cpu(*list++);
 503                         if (!conf_reg)
 504                                 conf_reg = -1;
 505                 }
 506
 507                 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
 508                 pin_reg = &ipctl->pin_regs[pin_id];
 509                 pin->pin = pin_id;
 510                 grp->pins[i] = pin_id;
 511                 pin_reg->mux_reg = mux_reg;
 512                 pin_reg->conf_reg = conf_reg;
 513                 pin->input_reg = be32_to_cpu(*list++);
 514                 pin->mux_mode = be32_to_cpu(*list++);
 515                 pin->input_val = be32_to_cpu(*list++);
 516
 517                 if (info->generic_pinconf) {
 518                         /* generic pin config decoded */
 519                         pin->config = config;
 520                 } else {
 521                         /* legacy pin config read from devicetree */
 522                         config = be32_to_cpu(*list++);
 523
 524                         /* SION bit is in mux register */
 525                         if (config & IMX_PAD_SION)
 526                                 pin->mux_mode |= IOMUXC_CONFIG_SION;
 527                         pin->config = config & ~IMX_PAD_SION;
 528                 }
 529
 530                 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
 531                                 pin->mux_mode, pin->config);
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int imx_pinctrl_parse_functions(struct device_node *np,
 538                                        struct imx_pinctrl *ipctl,
 539                                        u32 index)
 540 {
 541         struct pinctrl_dev *pctl = ipctl->pctl;
 542         struct device_node *child;
 543         struct function_desc *func;
 544         struct group_desc *grp;
 545         u32 i = 0;
 546
 547         dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name);
 548
 549         func = pinmux_generic_get_function(pctl, index);
 550         if (!func)
 551                 return -EINVAL;
 552
 553         /* Initialise function */
 554         func->name = np->name;
 555         func->num_group_names = of_get_child_count(np);
 556         if (func->num_group_names == 0) {
 557                 dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
 558                 return -EINVAL;
 559         }
 560         func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
 561                                          sizeof(char *), GFP_KERNEL);
 562         if (!func->group_names)
 563                 return -ENOMEM;
 564
 565         for_each_child_of_node(np, child) {
 566                 func->group_names[i] = child->name;
 567
 568                 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
 569                                    GFP_KERNEL);
 570                 if (!grp)
 571                         return -ENOMEM;
 572
 573                 mutex_lock(&ipctl->mutex);
 574                 radix_tree_insert(&pctl->pin_group_tree,
 575                                   ipctl->group_index++, grp);
 576                 mutex_unlock(&ipctl->mutex);
 577
 578                 imx_pinctrl_parse_groups(child, grp, ipctl, i++);
 579         }
 580
 581         return 0;
 582 }
 583
 584 /*
 585  * Check if the DT contains pins in the direct child nodes. This indicates the
 586  * newer DT format to store pins. This function returns true if the first found
 587  * fsl,pins property is in a child of np. Otherwise false is returned.
 588  */
 589 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
 590 {
 591         struct device_node *function_np;
 592         struct device_node *pinctrl_np;
 593
 594         for_each_child_of_node(np, function_np) {
 595                 if (of_property_read_bool(function_np, "fsl,pins"))
 596                         return true;
 597
 598                 for_each_child_of_node(function_np, pinctrl_np) {
 599                         if (of_property_read_bool(pinctrl_np, "fsl,pins"))
 600                                 return false;
 601                 }
 602         }
 603
 604         return true;
 605 }
 606
 607 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 608                                 struct imx_pinctrl *ipctl)
 609 {
 610         struct device_node *np = pdev->dev.of_node;
 611         struct device_node *child;
 612         struct pinctrl_dev *pctl = ipctl->pctl;
 613         u32 nfuncs = 0;
 614         u32 i = 0;
 615         bool flat_funcs;
 616
 617         if (!np)
 618                 return -ENODEV;
 619
 620         flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
 621         if (flat_funcs) {
 622                 nfuncs = 1;
 623         } else {
 624                 nfuncs = of_get_child_count(np);
 625                 if (nfuncs == 0) {
 626                         dev_err(&pdev->dev, "no functions defined\n");
 627                         return -EINVAL;
 628                 }
 629         }
 630
 631         for (i = 0; i < nfuncs; i++) {
 632                 struct function_desc *function;
 633
 634                 function = devm_kzalloc(&pdev->dev, sizeof(*function),
 635                                         GFP_KERNEL);
 636                 if (!function)
 637                         return -ENOMEM;
 638
 639                 mutex_lock(&ipctl->mutex);
 640                 radix_tree_insert(&pctl->pin_function_tree, i, function);
 641                 mutex_unlock(&ipctl->mutex);
 642         }
 643         pctl->num_functions = nfuncs;
 644
 645         ipctl->group_index = 0;
 646         if (flat_funcs) {
 647                 pctl->num_groups = of_get_child_count(np);
 648         } else {
 649                 pctl->num_groups = 0;
 650                 for_each_child_of_node(np, child)
 651                         pctl->num_groups += of_get_child_count(child);
 652         }
 653
 654         if (flat_funcs) {
 655                 imx_pinctrl_parse_functions(np, ipctl, 0);
 656         } else {
 657                 i = 0;
 658                 for_each_child_of_node(np, child)
 659                         imx_pinctrl_parse_functions(child, ipctl, i++);
 660         }
 661
 662         return 0;
 663 }
 664
 665 /*
 666  * imx_free_resources() - free memory used by this driver
 667  * @info: info driver instance
 668  */
 669 static void imx_free_resources(struct imx_pinctrl *ipctl)
 670 {
 671         if (ipctl->pctl)
 672                 pinctrl_unregister(ipctl->pctl);
 673 }
 674
 675 int imx_pinctrl_probe(struct platform_device *pdev,
 676                       const struct imx_pinctrl_soc_info *info)
 677 {
 678         struct regmap_config config = { .name = "gpr" };
 679         struct device_node *dev_np = pdev->dev.of_node;
 680         struct pinctrl_desc *imx_pinctrl_desc;
 681         struct device_node *np;
 682         struct imx_pinctrl *ipctl;
 683         struct resource *res;
 684         struct regmap *gpr;
 685         int ret, i;
 686
 687         if (!info || !info->pins || !info->npins) {
 688                 dev_err(&pdev->dev, "wrong pinctrl info\n");
 689                 return -EINVAL;
 690         }
 691
 692         if (info->gpr_compatible) {
 693                 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
 694                 if (!IS_ERR(gpr))
 695                         regmap_attach_dev(&pdev->dev, gpr, &config);
 696         }
 697
 698         /* Create state holders etc for this driver */
 699         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 700         if (!ipctl)
 701                 return -ENOMEM;
 702
 703         ipctl->pin_regs = devm_kmalloc_array(&pdev->dev,
 704                                        info->npins, sizeof(*ipctl->pin_regs),
 705                                        GFP_KERNEL);
 706         if (!ipctl->pin_regs)
 707                 return -ENOMEM;
 708
 709         for (i = 0; i < info->npins; i++) {
 710                 ipctl->pin_regs[i].mux_reg = -1;
 711                 ipctl->pin_regs[i].conf_reg = -1;
 712         }
 713
 714         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 715         ipctl->base = devm_ioremap_resource(&pdev->dev, res);
 716         if (IS_ERR(ipctl->base))
 717                 return PTR_ERR(ipctl->base);
 718
 719         if (of_property_read_bool(dev_np, "fsl,input-sel")) {
 720                 np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
 721                 if (!np) {
 722                         dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
 723                         return -EINVAL;
 724                 }
 725
 726                 ipctl->input_sel_base = of_iomap(np, 0);
 727                 of_node_put(np);
 728                 if (!ipctl->input_sel_base) {
 729                         dev_err(&pdev->dev,
 730                                 "iomuxc input select base address not found\n");
 731                         return -ENOMEM;
 732                 }
 733         }
 734
 735         imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
 736                                         GFP_KERNEL);
 737         if (!imx_pinctrl_desc)
 738                 return -ENOMEM;
 739
 740         imx_pinctrl_desc->name = dev_name(&pdev->dev);
 741         imx_pinctrl_desc->pins = info->pins;
 742         imx_pinctrl_desc->npins = info->npins;
 743         imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
 744         imx_pinctrl_desc->pmxops = &imx_pmx_ops;
 745         imx_pinctrl_desc->confops = &imx_pinconf_ops;
 746         imx_pinctrl_desc->owner = THIS_MODULE;
 747
 748         /* for generic pinconf */
 749         imx_pinctrl_desc->custom_params = info->custom_params;
 750         imx_pinctrl_desc->num_custom_params = info->num_custom_params;
 751
 752         /* platform specific callback */
 753         imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
 754
 755         mutex_init(&ipctl->mutex);
 756
 757         ipctl->info = info;
 758         ipctl->dev = &pdev->dev;
 759         platform_set_drvdata(pdev, ipctl);
 760         ret = devm_pinctrl_register_and_init(&pdev->dev,
 761                                              imx_pinctrl_desc, ipctl,
 762                                              &ipctl->pctl);
 763         if (ret) {
 764                 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
 765                 goto free;
 766         }
 767
 768         ret = imx_pinctrl_probe_dt(pdev, ipctl);
 769         if (ret) {
 770                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 771                 goto free;
 772         }
 773
 774         dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
 775
 776         return pinctrl_enable(ipctl->pctl);
 777
 778 free:
 779         imx_free_resources(ipctl);
 780
 781         return ret;
 782 }