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locking/refcounts: Include fewer headers in <linux/refcount.h>
[linux/fpc-iii.git] / drivers / soc / renesas / rcar-sysc.c
blob95120acc4d806da630f49737cca1eede3286edae
1 /*
2 * R-Car SYSC Power management support
3 *
4 * Copyright (C) 2014 Magnus Damm
5 * Copyright (C) 2015-2017 Glider bvba
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12 #include <linux/clk/renesas.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/mm.h>
16 #include <linux/of_address.h>
17 #include <linux/pm_domain.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/io.h>
21 #include <linux/soc/renesas/rcar-sysc.h>
22
23 #include "rcar-sysc.h"
24
25 /* SYSC Common */
26 #define SYSCSR 0x00 /* SYSC Status Register */
27 #define SYSCISR 0x04 /* Interrupt Status Register */
28 #define SYSCISCR 0x08 /* Interrupt Status Clear Register */
29 #define SYSCIER 0x0c /* Interrupt Enable Register */
30 #define SYSCIMR 0x10 /* Interrupt Mask Register */
31
32 /* SYSC Status Register */
33 #define SYSCSR_PONENB 1 /* Ready for power resume requests */
34 #define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
35
36 /*
37 * Power Control Register Offsets inside the register block for each domain
38 * Note: The "CR" registers for ARM cores exist on H1 only
39 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
40 * Use PSCI on R-Car Gen3
41 */
42 #define PWRSR_OFFS 0x00 /* Power Status Register */
43 #define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
44 #define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
45 #define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
46 #define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
47 #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
48
49
50 #define SYSCSR_RETRIES 100
51 #define SYSCSR_DELAY_US 1
52
53 #define PWRER_RETRIES 100
54 #define PWRER_DELAY_US 1
55
56 #define SYSCISR_RETRIES 1000
57 #define SYSCISR_DELAY_US 1
58
59 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
60
61 static void __iomem *rcar_sysc_base;
62 static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
63
64 static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
65 {
66 unsigned int sr_bit, reg_offs;
67 int k;
68
69 if (on) {
70 sr_bit = SYSCSR_PONENB;
71 reg_offs = PWRONCR_OFFS;
72 } else {
73 sr_bit = SYSCSR_POFFENB;
74 reg_offs = PWROFFCR_OFFS;
75 }
76
77 /* Wait until SYSC is ready to accept a power request */
78 for (k = 0; k < SYSCSR_RETRIES; k++) {
79 if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
80 break;
81 udelay(SYSCSR_DELAY_US);
82 }
83
84 if (k == SYSCSR_RETRIES)
85 return -EAGAIN;
86
87 /* Submit power shutoff or power resume request */
88 iowrite32(BIT(sysc_ch->chan_bit),
89 rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
90
91 return 0;
92 }
93
94 static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
95 {
96 unsigned int isr_mask = BIT(sysc_ch->isr_bit);
97 unsigned int chan_mask = BIT(sysc_ch->chan_bit);
98 unsigned int status;
99 unsigned long flags;
100 int ret = 0;
101 int k;
102
103 spin_lock_irqsave(&rcar_sysc_lock, flags);
104
105 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
106
107 /* Submit power shutoff or resume request until it was accepted */
108 for (k = 0; k < PWRER_RETRIES; k++) {
109 ret = rcar_sysc_pwr_on_off(sysc_ch, on);
110 if (ret)
111 goto out;
112
113 status = ioread32(rcar_sysc_base +
114 sysc_ch->chan_offs + PWRER_OFFS);
115 if (!(status & chan_mask))
116 break;
117
118 udelay(PWRER_DELAY_US);
119 }
120
121 if (k == PWRER_RETRIES) {
122 ret = -EIO;
123 goto out;
124 }
125
126 /* Wait until the power shutoff or resume request has completed * */
127 for (k = 0; k < SYSCISR_RETRIES; k++) {
128 if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
129 break;
130 udelay(SYSCISR_DELAY_US);
131 }
132
133 if (k == SYSCISR_RETRIES)
134 ret = -EIO;
135
136 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
137
138 out:
139 spin_unlock_irqrestore(&rcar_sysc_lock, flags);
140
141 pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
142 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
143 return ret;
144 }
145
146 int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
147 {
148 return rcar_sysc_power(sysc_ch, false);
149 }
150
151 int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
152 {
153 return rcar_sysc_power(sysc_ch, true);
154 }
155
156 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
157 {
158 unsigned int st;
159
160 st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
161 if (st & BIT(sysc_ch->chan_bit))
162 return true;
163
164 return false;
165 }
166
167 struct rcar_sysc_pd {
168 struct generic_pm_domain genpd;
169 struct rcar_sysc_ch ch;
170 unsigned int flags;
171 char name[0];
172 };
173
174 static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
175 {
176 return container_of(d, struct rcar_sysc_pd, genpd);
177 }
178
179 static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
180 {
181 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
182
183 pr_debug("%s: %s\n", __func__, genpd->name);
184 return rcar_sysc_power_down(&pd->ch);
185 }
186
187 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
188 {
189 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
190
191 pr_debug("%s: %s\n", __func__, genpd->name);
192 return rcar_sysc_power_up(&pd->ch);
193 }
194
195 static bool has_cpg_mstp;
196
197 static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
198 {
199 struct generic_pm_domain *genpd = &pd->genpd;
200 const char *name = pd->genpd.name;
201 struct dev_power_governor *gov = &simple_qos_governor;
202
203 if (pd->flags & PD_CPU) {
204 /*
205 * This domain contains a CPU core and therefore it should
206 * only be turned off if the CPU is not in use.
207 */
208 pr_debug("PM domain %s contains %s\n", name, "CPU");
209 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
210 } else if (pd->flags & PD_SCU) {
211 /*
212 * This domain contains an SCU and cache-controller, and
213 * therefore it should only be turned off if the CPU cores are
214 * not in use.
215 */
216 pr_debug("PM domain %s contains %s\n", name, "SCU");
217 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
218 } else if (pd->flags & PD_NO_CR) {
219 /*
220 * This domain cannot be turned off.
221 */
222 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
223 }
224
225 if (!(pd->flags & (PD_CPU | PD_SCU))) {
226 /* Enable Clock Domain for I/O devices */
227 genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
228 if (has_cpg_mstp) {
229 genpd->attach_dev = cpg_mstp_attach_dev;
230 genpd->detach_dev = cpg_mstp_detach_dev;
231 } else {
232 genpd->attach_dev = cpg_mssr_attach_dev;
233 genpd->detach_dev = cpg_mssr_detach_dev;
234 }
235 }
236
237 genpd->power_off = rcar_sysc_pd_power_off;
238 genpd->power_on = rcar_sysc_pd_power_on;
239
240 if (pd->flags & (PD_CPU | PD_NO_CR)) {
241 /* Skip CPUs (handled by SMP code) and areas without control */
242 pr_debug("%s: Not touching %s\n", __func__, genpd->name);
243 goto finalize;
244 }
245
246 if (!rcar_sysc_power_is_off(&pd->ch)) {
247 pr_debug("%s: %s is already powered\n", __func__, genpd->name);
248 goto finalize;
249 }
250
251 rcar_sysc_power_up(&pd->ch);
252
253 finalize:
254 pm_genpd_init(genpd, gov, false);
255 }
256
257 static const struct of_device_id rcar_sysc_matches[] __initconst = {
258 #ifdef CONFIG_SYSC_R8A7743
259 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
260 #endif
261 #ifdef CONFIG_SYSC_R8A7745
262 { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
263 #endif
264 #ifdef CONFIG_SYSC_R8A77470
265 { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
266 #endif
267 #ifdef CONFIG_SYSC_R8A7779
268 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
269 #endif
270 #ifdef CONFIG_SYSC_R8A7790
271 { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
272 #endif
273 #ifdef CONFIG_SYSC_R8A7791
274 { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
275 /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
276 { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
277 #endif
278 #ifdef CONFIG_SYSC_R8A7792
279 { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
280 #endif
281 #ifdef CONFIG_SYSC_R8A7794
282 { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
283 #endif
284 #ifdef CONFIG_SYSC_R8A7795
285 { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
286 #endif
287 #ifdef CONFIG_SYSC_R8A7796
288 { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
289 #endif
290 #ifdef CONFIG_SYSC_R8A77965
291 { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
292 #endif
293 #ifdef CONFIG_SYSC_R8A77970
294 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
295 #endif
296 #ifdef CONFIG_SYSC_R8A77980
297 { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
298 #endif
299 #ifdef CONFIG_SYSC_R8A77990
300 { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
301 #endif
302 #ifdef CONFIG_SYSC_R8A77995
303 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
304 #endif
305 { /* sentinel */ }
306 };
307
308 struct rcar_pm_domains {
309 struct genpd_onecell_data onecell_data;
310 struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
311 };
312
313 static int __init rcar_sysc_pd_init(void)
314 {
315 const struct rcar_sysc_info *info;
316 const struct of_device_id *match;
317 struct rcar_pm_domains *domains;
318 struct device_node *np;
319 u32 syscier, syscimr;
320 void __iomem *base;
321 unsigned int i;
322 int error;
323
324 if (rcar_sysc_base)
325 return 0;
326
327 np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
328 if (!np)
329 return -ENODEV;
330
331 info = match->data;
332
333 if (info->init) {
334 error = info->init();
335 if (error)
336 return error;
337 }
338
339 has_cpg_mstp = of_find_compatible_node(NULL, NULL,
340 "renesas,cpg-mstp-clocks");
341
342 base = of_iomap(np, 0);
343 if (!base) {
344 pr_warn("%pOF: Cannot map regs\n", np);
345 error = -ENOMEM;
346 goto out_put;
347 }
348
349 rcar_sysc_base = base;
350
351 domains = kzalloc(sizeof(*domains), GFP_KERNEL);
352 if (!domains) {
353 error = -ENOMEM;
354 goto out_put;
355 }
356
357 domains->onecell_data.domains = domains->domains;
358 domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
359
360 for (i = 0, syscier = 0; i < info->num_areas; i++)
361 syscier |= BIT(info->areas[i].isr_bit);
362
363 /*
364 * Mask all interrupt sources to prevent the CPU from receiving them.
365 * Make sure not to clear reserved bits that were set before.
366 */
367 syscimr = ioread32(base + SYSCIMR);
368 syscimr |= syscier;
369 pr_debug("%pOF: syscimr = 0x%08x\n", np, syscimr);
370 iowrite32(syscimr, base + SYSCIMR);
371
372 /*
373 * SYSC needs all interrupt sources enabled to control power.
374 */
375 pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
376 iowrite32(syscier, base + SYSCIER);
377
378 for (i = 0; i < info->num_areas; i++) {
379 const struct rcar_sysc_area *area = &info->areas[i];
380 struct rcar_sysc_pd *pd;
381
382 if (!area->name) {
383 /* Skip NULLified area */
384 continue;
385 }
386
387 pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
388 if (!pd) {
389 error = -ENOMEM;
390 goto out_put;
391 }
392
393 strcpy(pd->name, area->name);
394 pd->genpd.name = pd->name;
395 pd->ch.chan_offs = area->chan_offs;
396 pd->ch.chan_bit = area->chan_bit;
397 pd->ch.isr_bit = area->isr_bit;
398 pd->flags = area->flags;
399
400 rcar_sysc_pd_setup(pd);
401 if (area->parent >= 0)
402 pm_genpd_add_subdomain(domains->domains[area->parent],
403 &pd->genpd);
404
405 domains->domains[area->isr_bit] = &pd->genpd;
406 }
407
408 error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
409
410 out_put:
411 of_node_put(np);
412 return error;
413 }
414 early_initcall(rcar_sysc_pd_init);
415
416 void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
417 unsigned int num_areas, u8 id)
418 {
419 unsigned int i;
420
421 for (i = 0; i < num_areas; i++)
422 if (areas[i].isr_bit == id) {
423 areas[i].name = NULL;
424 return;
425 }
426 }
427
428 void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
429 {
430 u32 syscimr;
431
432 if (!rcar_sysc_pd_init())
433 return;
434
435 rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
436
437 /*
438 * Mask all interrupt sources to prevent the CPU from receiving them.
439 * Make sure not to clear reserved bits that were set before.
440 */
441 syscimr = ioread32(rcar_sysc_base + SYSCIMR);
442 syscimr |= syscier;
443 pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr);
444 iowrite32(syscimr, rcar_sysc_base + SYSCIMR);
445
446 /*
447 * SYSC needs all interrupt sources enabled to control power.
448 */
449 pr_debug("%s: syscier = 0x%08x\n", __func__, syscier);
450 iowrite32(syscier, rcar_sysc_base + SYSCIER);
451 }
Linux with added FPC-III support