arch/x86/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  *
  11  * Authors:
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *
  15  * This work is licensed under the terms of the GNU GPL, version 2.  See
  16  * the COPYING file in the top-level directory.
  17  *
  18  */
  19
  20 /*
  21  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  22  * so the code in this file is compiled twice, once per pte size.
  23  */
  24
  25 #if PTTYPE == 64
  26         #define pt_element_t u64
  27         #define guest_walker guest_walker64
  28         #define FNAME(name) paging##64_##name
  29         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  30         #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
  31         #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
  32         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  33         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  34         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS 4
  37         #define CMPXCHG cmpxchg
  38         #else
  39         #define CMPXCHG cmpxchg64
  40         #define PT_MAX_FULL_LEVELS 2
  41         #endif
  42 #elif PTTYPE == 32
  43         #define pt_element_t u32
  44         #define guest_walker guest_walker32
  45         #define FNAME(name) paging##32_##name
  46         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  47         #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
  48         #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
  49         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  50         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  51         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  52         #define PT_MAX_FULL_LEVELS 2
  53         #define CMPXCHG cmpxchg
  54 #else
  55         #error Invalid PTTYPE value
  56 #endif
  57
  58 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
  59 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
  60
  61 /*
  62  * The guest_walker structure emulates the behavior of the hardware page
  63  * table walker.
  64  */
  65 struct guest_walker {
  66         int level;
  67         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  68         pt_element_t ptes[PT_MAX_FULL_LEVELS];
  69         gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
  70         unsigned pt_access;
  71         unsigned pte_access;
  72         gfn_t gfn;
  73         u32 error_code;
  74 };
  75
  76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
  77 {
  78         return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
  79 }
  80
  81 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
  82                          gfn_t table_gfn, unsigned index,
  83                          pt_element_t orig_pte, pt_element_t new_pte)
  84 {
  85         pt_element_t ret;
  86         pt_element_t *table;
  87         struct page *page;
  88
  89         page = gfn_to_page(kvm, table_gfn);
  90
  91         table = kmap_atomic(page, KM_USER0);
  92         ret = CMPXCHG(&table[index], orig_pte, new_pte);
  93         kunmap_atomic(table, KM_USER0);
  94
  95         kvm_release_page_dirty(page);
  96
  97         return (ret != orig_pte);
  98 }
  99
 100 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
 101 {
 102         unsigned access;
 103
 104         access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
 105 #if PTTYPE == 64
 106         if (is_nx(vcpu))
 107                 access &= ~(gpte >> PT64_NX_SHIFT);
 108 #endif
 109         return access;
 110 }
 111
 112 /*
 113  * Fetch a guest pte for a guest virtual address
 114  */
 115 static int FNAME(walk_addr)(struct guest_walker *walker,
 116                             struct kvm_vcpu *vcpu, gva_t addr,
 117                             int write_fault, int user_fault, int fetch_fault)
 118 {
 119         pt_element_t pte;
 120         gfn_t table_gfn;
 121         unsigned index, pt_access, pte_access;
 122         gpa_t pte_gpa;
 123         int rsvd_fault = 0;
 124
 125         trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
 126                                      fetch_fault);
 127 walk:
 128         walker->level = vcpu->arch.mmu.root_level;
 129         pte = vcpu->arch.cr3;
 130 #if PTTYPE == 64
 131         if (!is_long_mode(vcpu)) {
 132                 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
 133                 trace_kvm_mmu_paging_element(pte, walker->level);
 134                 if (!is_present_gpte(pte))
 135                         goto not_present;
 136                 --walker->level;
 137         }
 138 #endif
 139         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
 140                (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
 141
 142         pt_access = ACC_ALL;
 143
 144         for (;;) {
 145                 index = PT_INDEX(addr, walker->level);
 146
 147                 table_gfn = gpte_to_gfn(pte);
 148                 pte_gpa = gfn_to_gpa(table_gfn);
 149                 pte_gpa += index * sizeof(pt_element_t);
 150                 walker->table_gfn[walker->level - 1] = table_gfn;
 151                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 152
 153                 if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)))
 154                         goto not_present;
 155
 156                 trace_kvm_mmu_paging_element(pte, walker->level);
 157
 158                 if (!is_present_gpte(pte))
 159                         goto not_present;
 160
 161                 rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
 162                 if (rsvd_fault)
 163                         goto access_error;
 164
 165                 if (write_fault && !is_writeble_pte(pte))
 166                         if (user_fault || is_write_protection(vcpu))
 167                                 goto access_error;
 168
 169                 if (user_fault && !(pte & PT_USER_MASK))
 170                         goto access_error;
 171
 172 #if PTTYPE == 64
 173                 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
 174                         goto access_error;
 175 #endif
 176
 177                 if (!(pte & PT_ACCESSED_MASK)) {
 178                         trace_kvm_mmu_set_accessed_bit(table_gfn, index,
 179                                                        sizeof(pte));
 180                         mark_page_dirty(vcpu->kvm, table_gfn);
 181                         if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
 182                             index, pte, pte|PT_ACCESSED_MASK))
 183                                 goto walk;
 184                         pte |= PT_ACCESSED_MASK;
 185                 }
 186
 187                 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
 188
 189                 walker->ptes[walker->level - 1] = pte;
 190
 191                 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
 192                     ((walker->level == PT_DIRECTORY_LEVEL) &&
 193                                 (pte & PT_PAGE_SIZE_MASK)  &&
 194                                 (PTTYPE == 64 || is_pse(vcpu))) ||
 195                     ((walker->level == PT_PDPE_LEVEL) &&
 196                                 (pte & PT_PAGE_SIZE_MASK)  &&
 197                                 is_long_mode(vcpu))) {
 198                         int lvl = walker->level;
 199
 200                         walker->gfn = gpte_to_gfn_lvl(pte, lvl);
 201                         walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
 202                                         >> PAGE_SHIFT;
 203
 204                         if (PTTYPE == 32 &&
 205                             walker->level == PT_DIRECTORY_LEVEL &&
 206                             is_cpuid_PSE36())
 207                                 walker->gfn += pse36_gfn_delta(pte);
 208
 209                         break;
 210                 }
 211
 212                 pt_access = pte_access;
 213                 --walker->level;
 214         }
 215
 216         if (write_fault && !is_dirty_gpte(pte)) {
 217                 bool ret;
 218
 219                 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
 220                 mark_page_dirty(vcpu->kvm, table_gfn);
 221                 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
 222                             pte|PT_DIRTY_MASK);
 223                 if (ret)
 224                         goto walk;
 225                 pte |= PT_DIRTY_MASK;
 226                 walker->ptes[walker->level - 1] = pte;
 227         }
 228
 229         walker->pt_access = pt_access;
 230         walker->pte_access = pte_access;
 231         pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
 232                  __func__, (u64)pte, pt_access, pte_access);
 233         return 1;
 234
 235 not_present:
 236         walker->error_code = 0;
 237         goto err;
 238
 239 access_error:
 240         walker->error_code = PFERR_PRESENT_MASK;
 241
 242 err:
 243         if (write_fault)
 244                 walker->error_code |= PFERR_WRITE_MASK;
 245         if (user_fault)
 246                 walker->error_code |= PFERR_USER_MASK;
 247         if (fetch_fault)
 248                 walker->error_code |= PFERR_FETCH_MASK;
 249         if (rsvd_fault)
 250                 walker->error_code |= PFERR_RSVD_MASK;
 251         trace_kvm_mmu_walker_error(walker->error_code);
 252         return 0;
 253 }
 254
 255 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 256                               u64 *spte, const void *pte)
 257 {
 258         pt_element_t gpte;
 259         unsigned pte_access;
 260         pfn_t pfn;
 261
 262         gpte = *(const pt_element_t *)pte;
 263         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
 264                 if (!is_present_gpte(gpte))
 265                         __set_spte(spte, shadow_notrap_nonpresent_pte);
 266                 return;
 267         }
 268         pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
 269         pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
 270         if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
 271                 return;
 272         pfn = vcpu->arch.update_pte.pfn;
 273         if (is_error_pfn(pfn))
 274                 return;
 275         if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
 276                 return;
 277         kvm_get_pfn(pfn);
 278         /*
 279          * we call mmu_set_spte() with reset_host_protection = true beacuse that
 280          * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
 281          */
 282         mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
 283                      gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
 284                      gpte_to_gfn(gpte), pfn, true, true);
 285 }
 286
 287 /*
 288  * Fetch a shadow pte for a specific level in the paging hierarchy.
 289  */
 290 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 291                          struct guest_walker *gw,
 292                          int user_fault, int write_fault, int hlevel,
 293                          int *ptwrite, pfn_t pfn)
 294 {
 295         unsigned access = gw->pt_access;
 296         struct kvm_mmu_page *shadow_page;
 297         u64 spte, *sptep = NULL;
 298         int direct;
 299         gfn_t table_gfn;
 300         int r;
 301         int level;
 302         pt_element_t curr_pte;
 303         struct kvm_shadow_walk_iterator iterator;
 304
 305         if (!is_present_gpte(gw->ptes[gw->level - 1]))
 306                 return NULL;
 307
 308         for_each_shadow_entry(vcpu, addr, iterator) {
 309                 level = iterator.level;
 310                 sptep = iterator.sptep;
 311                 if (iterator.level == hlevel) {
 312                         mmu_set_spte(vcpu, sptep, access,
 313                                      gw->pte_access & access,
 314                                      user_fault, write_fault,
 315                                      gw->ptes[gw->level-1] & PT_DIRTY_MASK,
 316                                      ptwrite, level,
 317                                      gw->gfn, pfn, false, true);
 318                         break;
 319                 }
 320
 321                 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
 322                         struct kvm_mmu_page *child;
 323                         unsigned direct_access;
 324
 325                         if (level != gw->level)
 326                                 continue;
 327
 328                         /*
 329                          * For the direct sp, if the guest pte's dirty bit
 330                          * changed form clean to dirty, it will corrupt the
 331                          * sp's access: allow writable in the read-only sp,
 332                          * so we should update the spte at this point to get
 333                          * a new sp with the correct access.
 334                          */
 335                         direct_access = gw->pt_access & gw->pte_access;
 336                         if (!is_dirty_gpte(gw->ptes[gw->level - 1]))
 337                                 direct_access &= ~ACC_WRITE_MASK;
 338
 339                         child = page_header(*sptep & PT64_BASE_ADDR_MASK);
 340                         if (child->role.access == direct_access)
 341                                 continue;
 342
 343                         mmu_page_remove_parent_pte(child, sptep);
 344                         __set_spte(sptep, shadow_trap_nonpresent_pte);
 345                         kvm_flush_remote_tlbs(vcpu->kvm);
 346                 }
 347
 348                 if (is_large_pte(*sptep)) {
 349                         rmap_remove(vcpu->kvm, sptep);
 350                         __set_spte(sptep, shadow_trap_nonpresent_pte);
 351                         kvm_flush_remote_tlbs(vcpu->kvm);
 352                 }
 353
 354                 if (level <= gw->level) {
 355                         int delta = level - gw->level + 1;
 356                         direct = 1;
 357                         if (!is_dirty_gpte(gw->ptes[level - delta]))
 358                                 access &= ~ACC_WRITE_MASK;
 359                         table_gfn = gpte_to_gfn(gw->ptes[level - delta]);
 360                         /* advance table_gfn when emulating 1gb pages with 4k */
 361                         if (delta == 0)
 362                                 table_gfn += PT_INDEX(addr, level);
 363                         access &= gw->pte_access;
 364                 } else {
 365                         direct = 0;
 366                         table_gfn = gw->table_gfn[level - 2];
 367                 }
 368                 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
 369                                                direct, access, sptep);
 370                 if (!direct) {
 371                         r = kvm_read_guest_atomic(vcpu->kvm,
 372                                                   gw->pte_gpa[level - 2],
 373                                                   &curr_pte, sizeof(curr_pte));
 374                         if (r || curr_pte != gw->ptes[level - 2]) {
 375                                 kvm_mmu_put_page(shadow_page, sptep);
 376                                 kvm_release_pfn_clean(pfn);
 377                                 sptep = NULL;
 378                                 break;
 379                         }
 380                 }
 381
 382                 spte = __pa(shadow_page->spt)
 383                         | PT_PRESENT_MASK | PT_ACCESSED_MASK
 384                         | PT_WRITABLE_MASK | PT_USER_MASK;
 385                 *sptep = spte;
 386         }
 387
 388         return sptep;
 389 }
 390
 391 /*
 392  * Page fault handler.  There are several causes for a page fault:
 393  *   - there is no shadow pte for the guest pte
 394  *   - write access through a shadow pte marked read only so that we can set
 395  *     the dirty bit
 396  *   - write access to a shadow pte marked read only so we can update the page
 397  *     dirty bitmap, when userspace requests it
 398  *   - mmio access; in this case we will never install a present shadow pte
 399  *   - normal guest page fault due to the guest pte marked not present, not
 400  *     writable, or not executable
 401  *
 402  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 403  *           a negative value on error.
 404  */
 405 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 406                                u32 error_code)
 407 {
 408         int write_fault = error_code & PFERR_WRITE_MASK;
 409         int user_fault = error_code & PFERR_USER_MASK;
 410         int fetch_fault = error_code & PFERR_FETCH_MASK;
 411         struct guest_walker walker;
 412         u64 *sptep;
 413         int write_pt = 0;
 414         int r;
 415         pfn_t pfn;
 416         int level = PT_PAGE_TABLE_LEVEL;
 417         unsigned long mmu_seq;
 418
 419         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
 420         kvm_mmu_audit(vcpu, "pre page fault");
 421
 422         r = mmu_topup_memory_caches(vcpu);
 423         if (r)
 424                 return r;
 425
 426         /*
 427          * Look up the guest pte for the faulting address.
 428          */
 429         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 430                              fetch_fault);
 431
 432         /*
 433          * The page is not mapped by the guest.  Let the guest handle it.
 434          */
 435         if (!r) {
 436                 pgprintk("%s: guest page fault\n", __func__);
 437                 inject_page_fault(vcpu, addr, walker.error_code);
 438                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 439                 return 0;
 440         }
 441
 442         if (walker.level >= PT_DIRECTORY_LEVEL) {
 443                 level = min(walker.level, mapping_level(vcpu, walker.gfn));
 444                 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
 445         }
 446
 447         mmu_seq = vcpu->kvm->mmu_notifier_seq;
 448         smp_rmb();
 449         pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
 450
 451         /* mmio */
 452         if (is_error_pfn(pfn)) {
 453                 pgprintk("gfn %lx is mmio\n", walker.gfn);
 454                 kvm_release_pfn_clean(pfn);
 455                 return 1;
 456         }
 457
 458         spin_lock(&vcpu->kvm->mmu_lock);
 459         if (mmu_notifier_retry(vcpu, mmu_seq))
 460                 goto out_unlock;
 461         kvm_mmu_free_some_pages(vcpu);
 462         sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 463                              level, &write_pt, pfn);
 464         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
 465                  sptep, *sptep, write_pt);
 466
 467         if (!write_pt)
 468                 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
 469
 470         ++vcpu->stat.pf_fixed;
 471         kvm_mmu_audit(vcpu, "post page fault (fixed)");
 472         spin_unlock(&vcpu->kvm->mmu_lock);
 473
 474         return write_pt;
 475
 476 out_unlock:
 477         spin_unlock(&vcpu->kvm->mmu_lock);
 478         kvm_release_pfn_clean(pfn);
 479         return 0;
 480 }
 481
 482 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
 483 {
 484         struct kvm_shadow_walk_iterator iterator;
 485         int level;
 486         u64 *sptep;
 487         int need_flush = 0;
 488
 489         spin_lock(&vcpu->kvm->mmu_lock);
 490
 491         for_each_shadow_entry(vcpu, gva, iterator) {
 492                 level = iterator.level;
 493                 sptep = iterator.sptep;
 494
 495                 /* FIXME: properly handle invlpg on large guest pages */
 496                 if (level == PT_PAGE_TABLE_LEVEL  ||
 497                     ((level == PT_DIRECTORY_LEVEL && is_large_pte(*sptep))) ||
 498                     ((level == PT_PDPE_LEVEL && is_large_pte(*sptep)))) {
 499
 500                         if (is_shadow_present_pte(*sptep)) {
 501                                 rmap_remove(vcpu->kvm, sptep);
 502                                 if (is_large_pte(*sptep))
 503                                         --vcpu->kvm->stat.lpages;
 504                                 need_flush = 1;
 505                         }
 506                         __set_spte(sptep, shadow_trap_nonpresent_pte);
 507                         break;
 508                 }
 509
 510                 if (!is_shadow_present_pte(*sptep))
 511                         break;
 512         }
 513
 514         if (need_flush)
 515                 kvm_flush_remote_tlbs(vcpu->kvm);
 516         spin_unlock(&vcpu->kvm->mmu_lock);
 517 }
 518
 519 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
 520                                u32 *error)
 521 {
 522         struct guest_walker walker;
 523         gpa_t gpa = UNMAPPED_GVA;
 524         int r;
 525
 526         r = FNAME(walk_addr)(&walker, vcpu, vaddr,
 527                              !!(access & PFERR_WRITE_MASK),
 528                              !!(access & PFERR_USER_MASK),
 529                              !!(access & PFERR_FETCH_MASK));
 530
 531         if (r) {
 532                 gpa = gfn_to_gpa(walker.gfn);
 533                 gpa |= vaddr & ~PAGE_MASK;
 534         } else if (error)
 535                 *error = walker.error_code;
 536
 537         return gpa;
 538 }
 539
 540 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 541                                  struct kvm_mmu_page *sp)
 542 {
 543         int i, j, offset, r;
 544         pt_element_t pt[256 / sizeof(pt_element_t)];
 545         gpa_t pte_gpa;
 546
 547         if (sp->role.direct
 548             || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
 549                 nonpaging_prefetch_page(vcpu, sp);
 550                 return;
 551         }
 552
 553         pte_gpa = gfn_to_gpa(sp->gfn);
 554         if (PTTYPE == 32) {
 555                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 556                 pte_gpa += offset * sizeof(pt_element_t);
 557         }
 558
 559         for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
 560                 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
 561                 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
 562                 for (j = 0; j < ARRAY_SIZE(pt); ++j)
 563                         if (r || is_present_gpte(pt[j]))
 564                                 sp->spt[i+j] = shadow_trap_nonpresent_pte;
 565                         else
 566                                 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
 567         }
 568 }
 569
 570 /*
 571  * Using the cached information from sp->gfns is safe because:
 572  * - The spte has a reference to the struct page, so the pfn for a given gfn
 573  *   can't change unless all sptes pointing to it are nuked first.
 574  * - Alias changes zap the entire shadow cache.
 575  */
 576 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 577 {
 578         int i, offset, nr_present;
 579         bool reset_host_protection;
 580
 581         offset = nr_present = 0;
 582
 583         if (PTTYPE == 32)
 584                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 585
 586         for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
 587                 unsigned pte_access;
 588                 pt_element_t gpte;
 589                 gpa_t pte_gpa;
 590                 gfn_t gfn = sp->gfns[i];
 591
 592                 if (!is_shadow_present_pte(sp->spt[i]))
 593                         continue;
 594
 595                 pte_gpa = gfn_to_gpa(sp->gfn);
 596                 pte_gpa += (i+offset) * sizeof(pt_element_t);
 597
 598                 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
 599                                           sizeof(pt_element_t)))
 600                         return -EINVAL;
 601
 602                 if (gpte_to_gfn(gpte) != gfn || !is_present_gpte(gpte) ||
 603                     !(gpte & PT_ACCESSED_MASK)) {
 604                         u64 nonpresent;
 605
 606                         rmap_remove(vcpu->kvm, &sp->spt[i]);
 607                         if (is_present_gpte(gpte))
 608                                 nonpresent = shadow_trap_nonpresent_pte;
 609                         else
 610                                 nonpresent = shadow_notrap_nonpresent_pte;
 611                         __set_spte(&sp->spt[i], nonpresent);
 612                         continue;
 613                 }
 614
 615                 nr_present++;
 616                 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
 617                 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
 618                         pte_access &= ~ACC_WRITE_MASK;
 619                         reset_host_protection = 0;
 620                 } else {
 621                         reset_host_protection = 1;
 622                 }
 623                 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
 624                          is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
 625                          spte_to_pfn(sp->spt[i]), true, false,
 626                          reset_host_protection);
 627         }
 628
 629         return !nr_present;
 630 }
 631
 632 #undef pt_element_t
 633 #undef guest_walker
 634 #undef FNAME
 635 #undef PT_BASE_ADDR_MASK
 636 #undef PT_INDEX
 637 #undef PT_LEVEL_MASK
 638 #undef PT_LVL_ADDR_MASK
 639 #undef PT_LVL_OFFSET_MASK
 640 #undef PT_LEVEL_BITS
 641 #undef PT_MAX_FULL_LEVELS
 642 #undef gpte_to_gfn
 643 #undef gpte_to_gfn_lvl
 644 #undef CMPXCHG