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x86: Cleanup highmap after brk is concluded
[linux/fpc-iii.git] / drivers / net / jme.c
bloba893f45db817498cdc4251e2bf955472fd88dd15
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
41 #include "jme.h"
42
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
54
55 static int
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
57 {
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61 read_again:
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
65
66 wmb();
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68 udelay(20);
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
71 break;
72 }
73
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76 return 0;
77 }
78
79 if (again--)
80 goto read_again;
81
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83 }
84
85 static void
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
88 {
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96 wmb();
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 break;
101 }
102
103 if (i == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106 return;
107 }
108
109 static inline void
110 jme_reset_phy_processor(struct jme_adapter *jme)
111 {
112 u32 val;
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
133 return;
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139 {
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161 }
162
163 static inline void
164 jme_reset_mac_processor(struct jme_adapter *jme)
165 {
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_clear_pm(struct jme_adapter *jme)
205 {
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209 }
210
211 static int
212 jme_reload_eeprom(struct jme_adapter *jme)
213 {
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239 }
240
241 static void
242 jme_load_macaddr(struct net_device *netdev)
243 {
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259 }
260
261 static inline void
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 {
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
292 }
293
294 static void
295 jme_start_irq(struct jme_adapter *jme)
296 {
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314 }
315
316 static inline void
317 jme_stop_irq(struct jme_adapter *jme)
318 {
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 }
324
325 static u32
326 jme_linkstat_from_phy(struct jme_adapter *jme)
327 {
328 u32 phylink, bmsr;
329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336 }
337
338 static inline void
339 jme_set_phyfifoa(struct jme_adapter *jme)
340 {
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342 }
343
344 static inline void
345 jme_set_phyfifob(struct jme_adapter *jme)
346 {
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348 }
349
350 static int
351 jme_check_link(struct net_device *netdev, int testonly)
352 {
353 struct jme_adapter *jme = netdev_priv(netdev);
354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
355 char linkmsg[64];
356 int rc = 0;
357
358 linkmsg[0] = '\0';
359
360 if (jme->fpgaver)
361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
364
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
386
387 strcat(linkmsg, "Forced: ");
388 } else {
389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
393 --cnt) {
394
395 udelay(1);
396
397 if (jme->fpgaver)
398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
401 }
402 if (!cnt)
403 jeprintk(jme->pdev,
404 "Waiting speed resolve timeout.\n");
405
406 strcat(linkmsg, "ANed: ");
407 }
408
409 if (jme->phylink == phylink) {
410 rc = 1;
411 goto out;
412 }
413 if (testonly)
414 goto out;
415
416 jme->phylink = phylink;
417
418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
425 strcat(linkmsg, "10 Mbps, ");
426 break;
427 case PHY_LINK_SPEED_100M:
428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
430 strcat(linkmsg, "100 Mbps, ");
431 break;
432 case PHY_LINK_SPEED_1000M:
433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
435 strcat(linkmsg, "1000 Mbps, ");
436 break;
437 default:
438 break;
439 }
440
441 if (phylink & PHY_LINK_DUPLEX) {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
443 ghc |= GHC_DPX;
444 } else {
445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
446 TXMCS_BACKOFF |
447 TXMCS_CARRIERSENSE |
448 TXMCS_COLLISION);
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
451 TXTRHD_TXREN |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 }
454
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
463 break;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
467 break;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
470 break;
471 default:
472 break;
473 }
474 }
475
476 jwrite32(jme, JME_GPREG1, gpreg1);
477 jwrite32(jme, JME_GHC, ghc);
478 jme->reg_ghc = ghc;
479
480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 "Full-Duplex, " :
482 "Half-Duplex, ");
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 "MDI-X" :
485 "MDI");
486 msg_link(jme, "Link is up at %s.\n", linkmsg);
487 netif_carrier_on(netdev);
488 } else {
489 if (testonly)
490 goto out;
491
492 msg_link(jme, "Link is down.\n");
493 jme->phylink = 0;
494 netif_carrier_off(netdev);
495 }
496
497 out:
498 return rc;
499 }
500
501 static int
502 jme_setup_tx_resources(struct jme_adapter *jme)
503 {
504 struct jme_ring *txring = &(jme->txring[0]);
505
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
508 &(txring->dmaalloc),
509 GFP_ATOMIC);
510
511 if (!txring->alloc)
512 goto err_set_null;
513
514 /*
515 * 16 Bytes align
516 */
517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
518 RING_DESC_ALIGN);
519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
520 txring->next_to_use = 0;
521 atomic_set(&txring->next_to_clean, 0);
522 atomic_set(&txring->nr_free, jme->tx_ring_size);
523
524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
528
529 /*
530 * Initialize Transmit Descriptors
531 */
532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
533 memset(txring->bufinf, 0,
534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
535
536 return 0;
537
538 err_free_txring:
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
541 txring->alloc,
542 txring->dmaalloc);
543
544 err_set_null:
545 txring->desc = NULL;
546 txring->dmaalloc = 0;
547 txring->dma = 0;
548 txring->bufinf = NULL;
549
550 return -ENOMEM;
551 }
552
553 static void
554 jme_free_tx_resources(struct jme_adapter *jme)
555 {
556 int i;
557 struct jme_ring *txring = &(jme->txring[0]);
558 struct jme_buffer_info *txbi;
559
560 if (txring->alloc) {
561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
564 if (txbi->skb) {
565 dev_kfree_skb(txbi->skb);
566 txbi->skb = NULL;
567 }
568 txbi->mapping = 0;
569 txbi->len = 0;
570 txbi->nr_desc = 0;
571 txbi->start_xmit = 0;
572 }
573 kfree(txring->bufinf);
574 }
575
576 dma_free_coherent(&(jme->pdev->dev),
577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
578 txring->alloc,
579 txring->dmaalloc);
580
581 txring->alloc = NULL;
582 txring->desc = NULL;
583 txring->dmaalloc = 0;
584 txring->dma = 0;
585 txring->bufinf = NULL;
586 }
587 txring->next_to_use = 0;
588 atomic_set(&txring->next_to_clean, 0);
589 atomic_set(&txring->nr_free, 0);
590 }
591
592 static inline void
593 jme_enable_tx_engine(struct jme_adapter *jme)
594 {
595 /*
596 * Select Queue 0
597 */
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
599 wmb();
600
601 /*
602 * Setup TX Queue 0 DMA Bass Address
603 */
604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607
608 /*
609 * Setup TX Descptor Count
610 */
611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
612
613 /*
614 * Enable TX Engine
615 */
616 wmb();
617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
618 TXCS_SELECT_QUEUE0 |
619 TXCS_ENABLE);
620
621 }
622
623 static inline void
624 jme_restart_tx_engine(struct jme_adapter *jme)
625 {
626 /*
627 * Restart TX Engine
628 */
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
630 TXCS_SELECT_QUEUE0 |
631 TXCS_ENABLE);
632 }
633
634 static inline void
635 jme_disable_tx_engine(struct jme_adapter *jme)
636 {
637 int i;
638 u32 val;
639
640 /*
641 * Disable TX Engine
642 */
643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
644 wmb();
645
646 val = jread32(jme, JME_TXCS);
647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
648 mdelay(1);
649 val = jread32(jme, JME_TXCS);
650 rmb();
651 }
652
653 if (!i)
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
655 }
656
657 static void
658 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
659 {
660 struct jme_ring *rxring = &(jme->rxring[0]);
661 register struct rxdesc *rxdesc = rxring->desc;
662 struct jme_buffer_info *rxbi = rxring->bufinf;
663 rxdesc += i;
664 rxbi += i;
665
666 rxdesc->dw[0] = 0;
667 rxdesc->dw[1] = 0;
668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
672 if (jme->dev->features & NETIF_F_HIGHDMA)
673 rxdesc->desc1.flags = RXFLAG_64BIT;
674 wmb();
675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
676 }
677
678 static int
679 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
680 {
681 struct jme_ring *rxring = &(jme->rxring[0]);
682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
683 struct sk_buff *skb;
684
685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
687 if (unlikely(!skb))
688 return -ENOMEM;
689
690 rxbi->skb = skb;
691 rxbi->len = skb_tailroom(skb);
692 rxbi->mapping = pci_map_page(jme->pdev,
693 virt_to_page(skb->data),
694 offset_in_page(skb->data),
695 rxbi->len,
696 PCI_DMA_FROMDEVICE);
697
698 return 0;
699 }
700
701 static void
702 jme_free_rx_buf(struct jme_adapter *jme, int i)
703 {
704 struct jme_ring *rxring = &(jme->rxring[0]);
705 struct jme_buffer_info *rxbi = rxring->bufinf;
706 rxbi += i;
707
708 if (rxbi->skb) {
709 pci_unmap_page(jme->pdev,
710 rxbi->mapping,
711 rxbi->len,
712 PCI_DMA_FROMDEVICE);
713 dev_kfree_skb(rxbi->skb);
714 rxbi->skb = NULL;
715 rxbi->mapping = 0;
716 rxbi->len = 0;
717 }
718 }
719
720 static void
721 jme_free_rx_resources(struct jme_adapter *jme)
722 {
723 int i;
724 struct jme_ring *rxring = &(jme->rxring[0]);
725
726 if (rxring->alloc) {
727 if (rxring->bufinf) {
728 for (i = 0 ; i < jme->rx_ring_size ; ++i)
729 jme_free_rx_buf(jme, i);
730 kfree(rxring->bufinf);
731 }
732
733 dma_free_coherent(&(jme->pdev->dev),
734 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
735 rxring->alloc,
736 rxring->dmaalloc);
737 rxring->alloc = NULL;
738 rxring->desc = NULL;
739 rxring->dmaalloc = 0;
740 rxring->dma = 0;
741 rxring->bufinf = NULL;
742 }
743 rxring->next_to_use = 0;
744 atomic_set(&rxring->next_to_clean, 0);
745 }
746
747 static int
748 jme_setup_rx_resources(struct jme_adapter *jme)
749 {
750 int i;
751 struct jme_ring *rxring = &(jme->rxring[0]);
752
753 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
754 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
755 &(rxring->dmaalloc),
756 GFP_ATOMIC);
757 if (!rxring->alloc)
758 goto err_set_null;
759
760 /*
761 * 16 Bytes align
762 */
763 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
764 RING_DESC_ALIGN);
765 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
766 rxring->next_to_use = 0;
767 atomic_set(&rxring->next_to_clean, 0);
768
769 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
770 jme->rx_ring_size, GFP_ATOMIC);
771 if (unlikely(!(rxring->bufinf)))
772 goto err_free_rxring;
773
774 /*
775 * Initiallize Receive Descriptors
776 */
777 memset(rxring->bufinf, 0,
778 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
779 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
780 if (unlikely(jme_make_new_rx_buf(jme, i))) {
781 jme_free_rx_resources(jme);
782 return -ENOMEM;
783 }
784
785 jme_set_clean_rxdesc(jme, i);
786 }
787
788 return 0;
789
790 err_free_rxring:
791 dma_free_coherent(&(jme->pdev->dev),
792 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
793 rxring->alloc,
794 rxring->dmaalloc);
795 err_set_null:
796 rxring->desc = NULL;
797 rxring->dmaalloc = 0;
798 rxring->dma = 0;
799 rxring->bufinf = NULL;
800
801 return -ENOMEM;
802 }
803
804 static inline void
805 jme_enable_rx_engine(struct jme_adapter *jme)
806 {
807 /*
808 * Select Queue 0
809 */
810 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
811 RXCS_QUEUESEL_Q0);
812 wmb();
813
814 /*
815 * Setup RX DMA Bass Address
816 */
817 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
818 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
819 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
820
821 /*
822 * Setup RX Descriptor Count
823 */
824 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
825
826 /*
827 * Setup Unicast Filter
828 */
829 jme_set_multi(jme->dev);
830
831 /*
832 * Enable RX Engine
833 */
834 wmb();
835 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
836 RXCS_QUEUESEL_Q0 |
837 RXCS_ENABLE |
838 RXCS_QST);
839 }
840
841 static inline void
842 jme_restart_rx_engine(struct jme_adapter *jme)
843 {
844 /*
845 * Start RX Engine
846 */
847 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
848 RXCS_QUEUESEL_Q0 |
849 RXCS_ENABLE |
850 RXCS_QST);
851 }
852
853 static inline void
854 jme_disable_rx_engine(struct jme_adapter *jme)
855 {
856 int i;
857 u32 val;
858
859 /*
860 * Disable RX Engine
861 */
862 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
863 wmb();
864
865 val = jread32(jme, JME_RXCS);
866 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
867 mdelay(1);
868 val = jread32(jme, JME_RXCS);
869 rmb();
870 }
871
872 if (!i)
873 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
874
875 }
876
877 static int
878 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
879 {
880 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
881 return false;
882
883 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
884 == RXWBFLAG_TCPON)) {
885 if (flags & RXWBFLAG_IPV4)
886 msg_rx_err(jme, "TCP Checksum error\n");
887 return false;
888 }
889
890 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
891 == RXWBFLAG_UDPON)) {
892 if (flags & RXWBFLAG_IPV4)
893 msg_rx_err(jme, "UDP Checksum error.\n");
894 return false;
895 }
896
897 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
898 == RXWBFLAG_IPV4)) {
899 msg_rx_err(jme, "IPv4 Checksum error.\n");
900 return false;
901 }
902
903 return true;
904 }
905
906 static void
907 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
908 {
909 struct jme_ring *rxring = &(jme->rxring[0]);
910 struct rxdesc *rxdesc = rxring->desc;
911 struct jme_buffer_info *rxbi = rxring->bufinf;
912 struct sk_buff *skb;
913 int framesize;
914
915 rxdesc += idx;
916 rxbi += idx;
917
918 skb = rxbi->skb;
919 pci_dma_sync_single_for_cpu(jme->pdev,
920 rxbi->mapping,
921 rxbi->len,
922 PCI_DMA_FROMDEVICE);
923
924 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
925 pci_dma_sync_single_for_device(jme->pdev,
926 rxbi->mapping,
927 rxbi->len,
928 PCI_DMA_FROMDEVICE);
929
930 ++(NET_STAT(jme).rx_dropped);
931 } else {
932 framesize = le16_to_cpu(rxdesc->descwb.framesize)
933 - RX_PREPAD_SIZE;
934
935 skb_reserve(skb, RX_PREPAD_SIZE);
936 skb_put(skb, framesize);
937 skb->protocol = eth_type_trans(skb, jme->dev);
938
939 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
940 skb->ip_summed = CHECKSUM_UNNECESSARY;
941 else
942 skb->ip_summed = CHECKSUM_NONE;
943
944 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
945 if (jme->vlgrp) {
946 jme->jme_vlan_rx(skb, jme->vlgrp,
947 le16_to_cpu(rxdesc->descwb.vlan));
948 NET_STAT(jme).rx_bytes += 4;
949 } else {
950 dev_kfree_skb(skb);
951 }
952 } else {
953 jme->jme_rx(skb);
954 }
955
956 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
957 cpu_to_le16(RXWBFLAG_DEST_MUL))
958 ++(NET_STAT(jme).multicast);
959
960 NET_STAT(jme).rx_bytes += framesize;
961 ++(NET_STAT(jme).rx_packets);
962 }
963
964 jme_set_clean_rxdesc(jme, idx);
965
966 }
967
968 static int
969 jme_process_receive(struct jme_adapter *jme, int limit)
970 {
971 struct jme_ring *rxring = &(jme->rxring[0]);
972 struct rxdesc *rxdesc = rxring->desc;
973 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
974
975 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
976 goto out_inc;
977
978 if (unlikely(atomic_read(&jme->link_changing) != 1))
979 goto out_inc;
980
981 if (unlikely(!netif_carrier_ok(jme->dev)))
982 goto out_inc;
983
984 i = atomic_read(&rxring->next_to_clean);
985 while (limit > 0) {
986 rxdesc = rxring->desc;
987 rxdesc += i;
988
989 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
990 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
991 goto out;
992 --limit;
993
994 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
995
996 if (unlikely(desccnt > 1 ||
997 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
998
999 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1000 ++(NET_STAT(jme).rx_crc_errors);
1001 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1002 ++(NET_STAT(jme).rx_fifo_errors);
1003 else
1004 ++(NET_STAT(jme).rx_errors);
1005
1006 if (desccnt > 1)
1007 limit -= desccnt - 1;
1008
1009 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1010 jme_set_clean_rxdesc(jme, j);
1011 j = (j + 1) & (mask);
1012 }
1013
1014 } else {
1015 jme_alloc_and_feed_skb(jme, i);
1016 }
1017
1018 i = (i + desccnt) & (mask);
1019 }
1020
1021 out:
1022 atomic_set(&rxring->next_to_clean, i);
1023
1024 out_inc:
1025 atomic_inc(&jme->rx_cleaning);
1026
1027 return limit > 0 ? limit : 0;
1028
1029 }
1030
1031 static void
1032 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1033 {
1034 if (likely(atmp == dpi->cur)) {
1035 dpi->cnt = 0;
1036 return;
1037 }
1038
1039 if (dpi->attempt == atmp) {
1040 ++(dpi->cnt);
1041 } else {
1042 dpi->attempt = atmp;
1043 dpi->cnt = 0;
1044 }
1045
1046 }
1047
1048 static void
1049 jme_dynamic_pcc(struct jme_adapter *jme)
1050 {
1051 register struct dynpcc_info *dpi = &(jme->dpi);
1052
1053 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1054 jme_attempt_pcc(dpi, PCC_P3);
1055 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1056 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1057 jme_attempt_pcc(dpi, PCC_P2);
1058 else
1059 jme_attempt_pcc(dpi, PCC_P1);
1060
1061 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1062 if (dpi->attempt < dpi->cur)
1063 tasklet_schedule(&jme->rxclean_task);
1064 jme_set_rx_pcc(jme, dpi->attempt);
1065 dpi->cur = dpi->attempt;
1066 dpi->cnt = 0;
1067 }
1068 }
1069
1070 static void
1071 jme_start_pcc_timer(struct jme_adapter *jme)
1072 {
1073 struct dynpcc_info *dpi = &(jme->dpi);
1074 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1075 dpi->last_pkts = NET_STAT(jme).rx_packets;
1076 dpi->intr_cnt = 0;
1077 jwrite32(jme, JME_TMCSR,
1078 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1079 }
1080
1081 static inline void
1082 jme_stop_pcc_timer(struct jme_adapter *jme)
1083 {
1084 jwrite32(jme, JME_TMCSR, 0);
1085 }
1086
1087 static void
1088 jme_shutdown_nic(struct jme_adapter *jme)
1089 {
1090 u32 phylink;
1091
1092 phylink = jme_linkstat_from_phy(jme);
1093
1094 if (!(phylink & PHY_LINK_UP)) {
1095 /*
1096 * Disable all interrupt before issue timer
1097 */
1098 jme_stop_irq(jme);
1099 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1100 }
1101 }
1102
1103 static void
1104 jme_pcc_tasklet(unsigned long arg)
1105 {
1106 struct jme_adapter *jme = (struct jme_adapter *)arg;
1107 struct net_device *netdev = jme->dev;
1108
1109 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1110 jme_shutdown_nic(jme);
1111 return;
1112 }
1113
1114 if (unlikely(!netif_carrier_ok(netdev) ||
1115 (atomic_read(&jme->link_changing) != 1)
1116 )) {
1117 jme_stop_pcc_timer(jme);
1118 return;
1119 }
1120
1121 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1122 jme_dynamic_pcc(jme);
1123
1124 jme_start_pcc_timer(jme);
1125 }
1126
1127 static inline void
1128 jme_polling_mode(struct jme_adapter *jme)
1129 {
1130 jme_set_rx_pcc(jme, PCC_OFF);
1131 }
1132
1133 static inline void
1134 jme_interrupt_mode(struct jme_adapter *jme)
1135 {
1136 jme_set_rx_pcc(jme, PCC_P1);
1137 }
1138
1139 static inline int
1140 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1141 {
1142 u32 apmc;
1143 apmc = jread32(jme, JME_APMC);
1144 return apmc & JME_APMC_PSEUDO_HP_EN;
1145 }
1146
1147 static void
1148 jme_start_shutdown_timer(struct jme_adapter *jme)
1149 {
1150 u32 apmc;
1151
1152 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1153 apmc &= ~JME_APMC_EPIEN_CTRL;
1154 if (!no_extplug) {
1155 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1156 wmb();
1157 }
1158 jwrite32f(jme, JME_APMC, apmc);
1159
1160 jwrite32f(jme, JME_TIMER2, 0);
1161 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1162 jwrite32(jme, JME_TMCSR,
1163 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1164 }
1165
1166 static void
1167 jme_stop_shutdown_timer(struct jme_adapter *jme)
1168 {
1169 u32 apmc;
1170
1171 jwrite32f(jme, JME_TMCSR, 0);
1172 jwrite32f(jme, JME_TIMER2, 0);
1173 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1174
1175 apmc = jread32(jme, JME_APMC);
1176 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1177 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1178 wmb();
1179 jwrite32f(jme, JME_APMC, apmc);
1180 }
1181
1182 static void
1183 jme_link_change_tasklet(unsigned long arg)
1184 {
1185 struct jme_adapter *jme = (struct jme_adapter *)arg;
1186 struct net_device *netdev = jme->dev;
1187 int rc;
1188
1189 while (!atomic_dec_and_test(&jme->link_changing)) {
1190 atomic_inc(&jme->link_changing);
1191 msg_intr(jme, "Get link change lock failed.\n");
1192 while (atomic_read(&jme->link_changing) != 1)
1193 msg_intr(jme, "Waiting link change lock.\n");
1194 }
1195
1196 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1197 goto out;
1198
1199 jme->old_mtu = netdev->mtu;
1200 netif_stop_queue(netdev);
1201 if (jme_pseudo_hotplug_enabled(jme))
1202 jme_stop_shutdown_timer(jme);
1203
1204 jme_stop_pcc_timer(jme);
1205 tasklet_disable(&jme->txclean_task);
1206 tasklet_disable(&jme->rxclean_task);
1207 tasklet_disable(&jme->rxempty_task);
1208
1209 if (netif_carrier_ok(netdev)) {
1210 jme_reset_ghc_speed(jme);
1211 jme_disable_rx_engine(jme);
1212 jme_disable_tx_engine(jme);
1213 jme_reset_mac_processor(jme);
1214 jme_free_rx_resources(jme);
1215 jme_free_tx_resources(jme);
1216
1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218 jme_polling_mode(jme);
1219
1220 netif_carrier_off(netdev);
1221 }
1222
1223 jme_check_link(netdev, 0);
1224 if (netif_carrier_ok(netdev)) {
1225 rc = jme_setup_rx_resources(jme);
1226 if (rc) {
1227 jeprintk(jme->pdev, "Allocating resources for RX error"
1228 ", Device STOPPED!\n");
1229 goto out_enable_tasklet;
1230 }
1231
1232 rc = jme_setup_tx_resources(jme);
1233 if (rc) {
1234 jeprintk(jme->pdev, "Allocating resources for TX error"
1235 ", Device STOPPED!\n");
1236 goto err_out_free_rx_resources;
1237 }
1238
1239 jme_enable_rx_engine(jme);
1240 jme_enable_tx_engine(jme);
1241
1242 netif_start_queue(netdev);
1243
1244 if (test_bit(JME_FLAG_POLL, &jme->flags))
1245 jme_interrupt_mode(jme);
1246
1247 jme_start_pcc_timer(jme);
1248 } else if (jme_pseudo_hotplug_enabled(jme)) {
1249 jme_start_shutdown_timer(jme);
1250 }
1251
1252 goto out_enable_tasklet;
1253
1254 err_out_free_rx_resources:
1255 jme_free_rx_resources(jme);
1256 out_enable_tasklet:
1257 tasklet_enable(&jme->txclean_task);
1258 tasklet_hi_enable(&jme->rxclean_task);
1259 tasklet_hi_enable(&jme->rxempty_task);
1260 out:
1261 atomic_inc(&jme->link_changing);
1262 }
1263
1264 static void
1265 jme_rx_clean_tasklet(unsigned long arg)
1266 {
1267 struct jme_adapter *jme = (struct jme_adapter *)arg;
1268 struct dynpcc_info *dpi = &(jme->dpi);
1269
1270 jme_process_receive(jme, jme->rx_ring_size);
1271 ++(dpi->intr_cnt);
1272
1273 }
1274
1275 static int
1276 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1277 {
1278 struct jme_adapter *jme = jme_napi_priv(holder);
1279 int rest;
1280
1281 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1282
1283 while (atomic_read(&jme->rx_empty) > 0) {
1284 atomic_dec(&jme->rx_empty);
1285 ++(NET_STAT(jme).rx_dropped);
1286 jme_restart_rx_engine(jme);
1287 }
1288 atomic_inc(&jme->rx_empty);
1289
1290 if (rest) {
1291 JME_RX_COMPLETE(netdev, holder);
1292 jme_interrupt_mode(jme);
1293 }
1294
1295 JME_NAPI_WEIGHT_SET(budget, rest);
1296 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1297 }
1298
1299 static void
1300 jme_rx_empty_tasklet(unsigned long arg)
1301 {
1302 struct jme_adapter *jme = (struct jme_adapter *)arg;
1303
1304 if (unlikely(atomic_read(&jme->link_changing) != 1))
1305 return;
1306
1307 if (unlikely(!netif_carrier_ok(jme->dev)))
1308 return;
1309
1310 msg_rx_status(jme, "RX Queue Full!\n");
1311
1312 jme_rx_clean_tasklet(arg);
1313
1314 while (atomic_read(&jme->rx_empty) > 0) {
1315 atomic_dec(&jme->rx_empty);
1316 ++(NET_STAT(jme).rx_dropped);
1317 jme_restart_rx_engine(jme);
1318 }
1319 atomic_inc(&jme->rx_empty);
1320 }
1321
1322 static void
1323 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1324 {
1325 struct jme_ring *txring = &(jme->txring[0]);
1326
1327 smp_wmb();
1328 if (unlikely(netif_queue_stopped(jme->dev) &&
1329 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1330 msg_tx_done(jme, "TX Queue Waked.\n");
1331 netif_wake_queue(jme->dev);
1332 }
1333
1334 }
1335
1336 static void
1337 jme_tx_clean_tasklet(unsigned long arg)
1338 {
1339 struct jme_adapter *jme = (struct jme_adapter *)arg;
1340 struct jme_ring *txring = &(jme->txring[0]);
1341 struct txdesc *txdesc = txring->desc;
1342 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1343 int i, j, cnt = 0, max, err, mask;
1344
1345 tx_dbg(jme, "Into txclean.\n");
1346
1347 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1348 goto out;
1349
1350 if (unlikely(atomic_read(&jme->link_changing) != 1))
1351 goto out;
1352
1353 if (unlikely(!netif_carrier_ok(jme->dev)))
1354 goto out;
1355
1356 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1357 mask = jme->tx_ring_mask;
1358
1359 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1360
1361 ctxbi = txbi + i;
1362
1363 if (likely(ctxbi->skb &&
1364 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1365
1366 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1367 i, ctxbi->nr_desc, jiffies);
1368
1369 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1370
1371 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1372 ttxbi = txbi + ((i + j) & (mask));
1373 txdesc[(i + j) & (mask)].dw[0] = 0;
1374
1375 pci_unmap_page(jme->pdev,
1376 ttxbi->mapping,
1377 ttxbi->len,
1378 PCI_DMA_TODEVICE);
1379
1380 ttxbi->mapping = 0;
1381 ttxbi->len = 0;
1382 }
1383
1384 dev_kfree_skb(ctxbi->skb);
1385
1386 cnt += ctxbi->nr_desc;
1387
1388 if (unlikely(err)) {
1389 ++(NET_STAT(jme).tx_carrier_errors);
1390 } else {
1391 ++(NET_STAT(jme).tx_packets);
1392 NET_STAT(jme).tx_bytes += ctxbi->len;
1393 }
1394
1395 ctxbi->skb = NULL;
1396 ctxbi->len = 0;
1397 ctxbi->start_xmit = 0;
1398
1399 } else {
1400 break;
1401 }
1402
1403 i = (i + ctxbi->nr_desc) & mask;
1404
1405 ctxbi->nr_desc = 0;
1406 }
1407
1408 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1409 atomic_set(&txring->next_to_clean, i);
1410 atomic_add(cnt, &txring->nr_free);
1411
1412 jme_wake_queue_if_stopped(jme);
1413
1414 out:
1415 atomic_inc(&jme->tx_cleaning);
1416 }
1417
1418 static void
1419 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1420 {
1421 /*
1422 * Disable interrupt
1423 */
1424 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1425
1426 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1427 /*
1428 * Link change event is critical
1429 * all other events are ignored
1430 */
1431 jwrite32(jme, JME_IEVE, intrstat);
1432 tasklet_schedule(&jme->linkch_task);
1433 goto out_reenable;
1434 }
1435
1436 if (intrstat & INTR_TMINTR) {
1437 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1438 tasklet_schedule(&jme->pcc_task);
1439 }
1440
1441 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1442 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1443 tasklet_schedule(&jme->txclean_task);
1444 }
1445
1446 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1447 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1448 INTR_PCCRX0 |
1449 INTR_RX0EMP)) |
1450 INTR_RX0);
1451 }
1452
1453 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1454 if (intrstat & INTR_RX0EMP)
1455 atomic_inc(&jme->rx_empty);
1456
1457 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1458 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1459 jme_polling_mode(jme);
1460 JME_RX_SCHEDULE(jme);
1461 }
1462 }
1463 } else {
1464 if (intrstat & INTR_RX0EMP) {
1465 atomic_inc(&jme->rx_empty);
1466 tasklet_hi_schedule(&jme->rxempty_task);
1467 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1468 tasklet_hi_schedule(&jme->rxclean_task);
1469 }
1470 }
1471
1472 out_reenable:
1473 /*
1474 * Re-enable interrupt
1475 */
1476 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1477 }
1478
1479 static irqreturn_t
1480 jme_intr(int irq, void *dev_id)
1481 {
1482 struct net_device *netdev = dev_id;
1483 struct jme_adapter *jme = netdev_priv(netdev);
1484 u32 intrstat;
1485
1486 intrstat = jread32(jme, JME_IEVE);
1487
1488 /*
1489 * Check if it's really an interrupt for us
1490 */
1491 if (unlikely((intrstat & INTR_ENABLE) == 0))
1492 return IRQ_NONE;
1493
1494 /*
1495 * Check if the device still exist
1496 */
1497 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1498 return IRQ_NONE;
1499
1500 jme_intr_msi(jme, intrstat);
1501
1502 return IRQ_HANDLED;
1503 }
1504
1505 static irqreturn_t
1506 jme_msi(int irq, void *dev_id)
1507 {
1508 struct net_device *netdev = dev_id;
1509 struct jme_adapter *jme = netdev_priv(netdev);
1510 u32 intrstat;
1511
1512 intrstat = jread32(jme, JME_IEVE);
1513
1514 jme_intr_msi(jme, intrstat);
1515
1516 return IRQ_HANDLED;
1517 }
1518
1519 static void
1520 jme_reset_link(struct jme_adapter *jme)
1521 {
1522 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1523 }
1524
1525 static void
1526 jme_restart_an(struct jme_adapter *jme)
1527 {
1528 u32 bmcr;
1529
1530 spin_lock_bh(&jme->phy_lock);
1531 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1532 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1533 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1534 spin_unlock_bh(&jme->phy_lock);
1535 }
1536
1537 static int
1538 jme_request_irq(struct jme_adapter *jme)
1539 {
1540 int rc;
1541 struct net_device *netdev = jme->dev;
1542 irq_handler_t handler = jme_intr;
1543 int irq_flags = IRQF_SHARED;
1544
1545 if (!pci_enable_msi(jme->pdev)) {
1546 set_bit(JME_FLAG_MSI, &jme->flags);
1547 handler = jme_msi;
1548 irq_flags = 0;
1549 }
1550
1551 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1552 netdev);
1553 if (rc) {
1554 jeprintk(jme->pdev,
1555 "Unable to request %s interrupt (return: %d)\n",
1556 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1557 rc);
1558
1559 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1560 pci_disable_msi(jme->pdev);
1561 clear_bit(JME_FLAG_MSI, &jme->flags);
1562 }
1563 } else {
1564 netdev->irq = jme->pdev->irq;
1565 }
1566
1567 return rc;
1568 }
1569
1570 static void
1571 jme_free_irq(struct jme_adapter *jme)
1572 {
1573 free_irq(jme->pdev->irq, jme->dev);
1574 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1575 pci_disable_msi(jme->pdev);
1576 clear_bit(JME_FLAG_MSI, &jme->flags);
1577 jme->dev->irq = jme->pdev->irq;
1578 }
1579 }
1580
1581 static inline void
1582 jme_phy_on(struct jme_adapter *jme)
1583 {
1584 u32 bmcr;
1585
1586 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1587 bmcr &= ~BMCR_PDOWN;
1588 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1589 }
1590
1591 static int
1592 jme_open(struct net_device *netdev)
1593 {
1594 struct jme_adapter *jme = netdev_priv(netdev);
1595 int rc;
1596
1597 jme_clear_pm(jme);
1598 JME_NAPI_ENABLE(jme);
1599
1600 tasklet_enable(&jme->linkch_task);
1601 tasklet_enable(&jme->txclean_task);
1602 tasklet_hi_enable(&jme->rxclean_task);
1603 tasklet_hi_enable(&jme->rxempty_task);
1604
1605 rc = jme_request_irq(jme);
1606 if (rc)
1607 goto err_out;
1608
1609 jme_start_irq(jme);
1610
1611 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1612 jme_phy_on(jme);
1613 jme_set_settings(netdev, &jme->old_ecmd);
1614 } else {
1615 jme_reset_phy_processor(jme);
1616 }
1617
1618 jme_reset_link(jme);
1619
1620 return 0;
1621
1622 err_out:
1623 netif_stop_queue(netdev);
1624 netif_carrier_off(netdev);
1625 return rc;
1626 }
1627
1628 #ifdef CONFIG_PM
1629 static void
1630 jme_set_100m_half(struct jme_adapter *jme)
1631 {
1632 u32 bmcr, tmp;
1633
1634 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1635 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1636 BMCR_SPEED1000 | BMCR_FULLDPLX);
1637 tmp |= BMCR_SPEED100;
1638
1639 if (bmcr != tmp)
1640 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1641
1642 if (jme->fpgaver)
1643 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1644 else
1645 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1646 }
1647
1648 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1649 static void
1650 jme_wait_link(struct jme_adapter *jme)
1651 {
1652 u32 phylink, to = JME_WAIT_LINK_TIME;
1653
1654 mdelay(1000);
1655 phylink = jme_linkstat_from_phy(jme);
1656 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1657 mdelay(10);
1658 phylink = jme_linkstat_from_phy(jme);
1659 }
1660 }
1661 #endif
1662
1663 static inline void
1664 jme_phy_off(struct jme_adapter *jme)
1665 {
1666 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1667 }
1668
1669 static int
1670 jme_close(struct net_device *netdev)
1671 {
1672 struct jme_adapter *jme = netdev_priv(netdev);
1673
1674 netif_stop_queue(netdev);
1675 netif_carrier_off(netdev);
1676
1677 jme_stop_irq(jme);
1678 jme_free_irq(jme);
1679
1680 JME_NAPI_DISABLE(jme);
1681
1682 tasklet_disable(&jme->linkch_task);
1683 tasklet_disable(&jme->txclean_task);
1684 tasklet_disable(&jme->rxclean_task);
1685 tasklet_disable(&jme->rxempty_task);
1686
1687 jme_reset_ghc_speed(jme);
1688 jme_disable_rx_engine(jme);
1689 jme_disable_tx_engine(jme);
1690 jme_reset_mac_processor(jme);
1691 jme_free_rx_resources(jme);
1692 jme_free_tx_resources(jme);
1693 jme->phylink = 0;
1694 jme_phy_off(jme);
1695
1696 return 0;
1697 }
1698
1699 static int
1700 jme_alloc_txdesc(struct jme_adapter *jme,
1701 struct sk_buff *skb)
1702 {
1703 struct jme_ring *txring = &(jme->txring[0]);
1704 int idx, nr_alloc, mask = jme->tx_ring_mask;
1705
1706 idx = txring->next_to_use;
1707 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1708
1709 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1710 return -1;
1711
1712 atomic_sub(nr_alloc, &txring->nr_free);
1713
1714 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1715
1716 return idx;
1717 }
1718
1719 static void
1720 jme_fill_tx_map(struct pci_dev *pdev,
1721 struct txdesc *txdesc,
1722 struct jme_buffer_info *txbi,
1723 struct page *page,
1724 u32 page_offset,
1725 u32 len,
1726 u8 hidma)
1727 {
1728 dma_addr_t dmaaddr;
1729
1730 dmaaddr = pci_map_page(pdev,
1731 page,
1732 page_offset,
1733 len,
1734 PCI_DMA_TODEVICE);
1735
1736 pci_dma_sync_single_for_device(pdev,
1737 dmaaddr,
1738 len,
1739 PCI_DMA_TODEVICE);
1740
1741 txdesc->dw[0] = 0;
1742 txdesc->dw[1] = 0;
1743 txdesc->desc2.flags = TXFLAG_OWN;
1744 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1745 txdesc->desc2.datalen = cpu_to_le16(len);
1746 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1747 txdesc->desc2.bufaddrl = cpu_to_le32(
1748 (__u64)dmaaddr & 0xFFFFFFFFUL);
1749
1750 txbi->mapping = dmaaddr;
1751 txbi->len = len;
1752 }
1753
1754 static void
1755 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1756 {
1757 struct jme_ring *txring = &(jme->txring[0]);
1758 struct txdesc *txdesc = txring->desc, *ctxdesc;
1759 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1760 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1761 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1762 int mask = jme->tx_ring_mask;
1763 struct skb_frag_struct *frag;
1764 u32 len;
1765
1766 for (i = 0 ; i < nr_frags ; ++i) {
1767 frag = &skb_shinfo(skb)->frags[i];
1768 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1769 ctxbi = txbi + ((idx + i + 2) & (mask));
1770
1771 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1772 frag->page_offset, frag->size, hidma);
1773 }
1774
1775 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1776 ctxdesc = txdesc + ((idx + 1) & (mask));
1777 ctxbi = txbi + ((idx + 1) & (mask));
1778 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1779 offset_in_page(skb->data), len, hidma);
1780
1781 }
1782
1783 static int
1784 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1785 {
1786 if (unlikely(skb_shinfo(skb)->gso_size &&
1787 skb_header_cloned(skb) &&
1788 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1789 dev_kfree_skb(skb);
1790 return -1;
1791 }
1792
1793 return 0;
1794 }
1795
1796 static int
1797 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1798 {
1799 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1800 if (*mss) {
1801 *flags |= TXFLAG_LSEN;
1802
1803 if (skb->protocol == htons(ETH_P_IP)) {
1804 struct iphdr *iph = ip_hdr(skb);
1805
1806 iph->check = 0;
1807 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1808 iph->daddr, 0,
1809 IPPROTO_TCP,
1810 0);
1811 } else {
1812 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1813
1814 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1815 &ip6h->daddr, 0,
1816 IPPROTO_TCP,
1817 0);
1818 }
1819
1820 return 0;
1821 }
1822
1823 return 1;
1824 }
1825
1826 static void
1827 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1828 {
1829 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1830 u8 ip_proto;
1831
1832 switch (skb->protocol) {
1833 case htons(ETH_P_IP):
1834 ip_proto = ip_hdr(skb)->protocol;
1835 break;
1836 case htons(ETH_P_IPV6):
1837 ip_proto = ipv6_hdr(skb)->nexthdr;
1838 break;
1839 default:
1840 ip_proto = 0;
1841 break;
1842 }
1843
1844 switch (ip_proto) {
1845 case IPPROTO_TCP:
1846 *flags |= TXFLAG_TCPCS;
1847 break;
1848 case IPPROTO_UDP:
1849 *flags |= TXFLAG_UDPCS;
1850 break;
1851 default:
1852 msg_tx_err(jme, "Error upper layer protocol.\n");
1853 break;
1854 }
1855 }
1856 }
1857
1858 static inline void
1859 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1860 {
1861 if (vlan_tx_tag_present(skb)) {
1862 *flags |= TXFLAG_TAGON;
1863 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1864 }
1865 }
1866
1867 static int
1868 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1869 {
1870 struct jme_ring *txring = &(jme->txring[0]);
1871 struct txdesc *txdesc;
1872 struct jme_buffer_info *txbi;
1873 u8 flags;
1874
1875 txdesc = (struct txdesc *)txring->desc + idx;
1876 txbi = txring->bufinf + idx;
1877
1878 txdesc->dw[0] = 0;
1879 txdesc->dw[1] = 0;
1880 txdesc->dw[2] = 0;
1881 txdesc->dw[3] = 0;
1882 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1883 /*
1884 * Set OWN bit at final.
1885 * When kernel transmit faster than NIC.
1886 * And NIC trying to send this descriptor before we tell
1887 * it to start sending this TX queue.
1888 * Other fields are already filled correctly.
1889 */
1890 wmb();
1891 flags = TXFLAG_OWN | TXFLAG_INT;
1892 /*
1893 * Set checksum flags while not tso
1894 */
1895 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1896 jme_tx_csum(jme, skb, &flags);
1897 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1898 jme_map_tx_skb(jme, skb, idx);
1899 txdesc->desc1.flags = flags;
1900 /*
1901 * Set tx buffer info after telling NIC to send
1902 * For better tx_clean timing
1903 */
1904 wmb();
1905 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1906 txbi->skb = skb;
1907 txbi->len = skb->len;
1908 txbi->start_xmit = jiffies;
1909 if (!txbi->start_xmit)
1910 txbi->start_xmit = (0UL-1);
1911
1912 return 0;
1913 }
1914
1915 static void
1916 jme_stop_queue_if_full(struct jme_adapter *jme)
1917 {
1918 struct jme_ring *txring = &(jme->txring[0]);
1919 struct jme_buffer_info *txbi = txring->bufinf;
1920 int idx = atomic_read(&txring->next_to_clean);
1921
1922 txbi += idx;
1923
1924 smp_wmb();
1925 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1926 netif_stop_queue(jme->dev);
1927 msg_tx_queued(jme, "TX Queue Paused.\n");
1928 smp_wmb();
1929 if (atomic_read(&txring->nr_free)
1930 >= (jme->tx_wake_threshold)) {
1931 netif_wake_queue(jme->dev);
1932 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1933 }
1934 }
1935
1936 if (unlikely(txbi->start_xmit &&
1937 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1938 txbi->skb)) {
1939 netif_stop_queue(jme->dev);
1940 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1941 }
1942 }
1943
1944 /*
1945 * This function is already protected by netif_tx_lock()
1946 */
1947
1948 static netdev_tx_t
1949 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1950 {
1951 struct jme_adapter *jme = netdev_priv(netdev);
1952 int idx;
1953
1954 if (unlikely(jme_expand_header(jme, skb))) {
1955 ++(NET_STAT(jme).tx_dropped);
1956 return NETDEV_TX_OK;
1957 }
1958
1959 idx = jme_alloc_txdesc(jme, skb);
1960
1961 if (unlikely(idx < 0)) {
1962 netif_stop_queue(netdev);
1963 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1964
1965 return NETDEV_TX_BUSY;
1966 }
1967
1968 jme_fill_tx_desc(jme, skb, idx);
1969
1970 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1971 TXCS_SELECT_QUEUE0 |
1972 TXCS_QUEUE0S |
1973 TXCS_ENABLE);
1974
1975 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1976 skb_shinfo(skb)->nr_frags + 2,
1977 jiffies);
1978 jme_stop_queue_if_full(jme);
1979
1980 return NETDEV_TX_OK;
1981 }
1982
1983 static int
1984 jme_set_macaddr(struct net_device *netdev, void *p)
1985 {
1986 struct jme_adapter *jme = netdev_priv(netdev);
1987 struct sockaddr *addr = p;
1988 u32 val;
1989
1990 if (netif_running(netdev))
1991 return -EBUSY;
1992
1993 spin_lock_bh(&jme->macaddr_lock);
1994 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1995
1996 val = (addr->sa_data[3] & 0xff) << 24 |
1997 (addr->sa_data[2] & 0xff) << 16 |
1998 (addr->sa_data[1] & 0xff) << 8 |
1999 (addr->sa_data[0] & 0xff);
2000 jwrite32(jme, JME_RXUMA_LO, val);
2001 val = (addr->sa_data[5] & 0xff) << 8 |
2002 (addr->sa_data[4] & 0xff);
2003 jwrite32(jme, JME_RXUMA_HI, val);
2004 spin_unlock_bh(&jme->macaddr_lock);
2005
2006 return 0;
2007 }
2008
2009 static void
2010 jme_set_multi(struct net_device *netdev)
2011 {
2012 struct jme_adapter *jme = netdev_priv(netdev);
2013 u32 mc_hash[2] = {};
2014 int i;
2015
2016 spin_lock_bh(&jme->rxmcs_lock);
2017
2018 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2019
2020 if (netdev->flags & IFF_PROMISC) {
2021 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2022 } else if (netdev->flags & IFF_ALLMULTI) {
2023 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2024 } else if (netdev->flags & IFF_MULTICAST) {
2025 struct dev_mc_list *mclist;
2026 int bit_nr;
2027
2028 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2029 for (i = 0, mclist = netdev->mc_list;
2030 mclist && i < netdev->mc_count;
2031 ++i, mclist = mclist->next) {
2032
2033 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2034 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2035 }
2036
2037 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2038 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2039 }
2040
2041 wmb();
2042 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2043
2044 spin_unlock_bh(&jme->rxmcs_lock);
2045 }
2046
2047 static int
2048 jme_change_mtu(struct net_device *netdev, int new_mtu)
2049 {
2050 struct jme_adapter *jme = netdev_priv(netdev);
2051
2052 if (new_mtu == jme->old_mtu)
2053 return 0;
2054
2055 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2056 ((new_mtu) < IPV6_MIN_MTU))
2057 return -EINVAL;
2058
2059 if (new_mtu > 4000) {
2060 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2061 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2062 jme_restart_rx_engine(jme);
2063 } else {
2064 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2065 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2066 jme_restart_rx_engine(jme);
2067 }
2068
2069 if (new_mtu > 1900) {
2070 netdev->features &= ~(NETIF_F_HW_CSUM |
2071 NETIF_F_TSO |
2072 NETIF_F_TSO6);
2073 } else {
2074 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2075 netdev->features |= NETIF_F_HW_CSUM;
2076 if (test_bit(JME_FLAG_TSO, &jme->flags))
2077 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2078 }
2079
2080 netdev->mtu = new_mtu;
2081 jme_reset_link(jme);
2082
2083 return 0;
2084 }
2085
2086 static void
2087 jme_tx_timeout(struct net_device *netdev)
2088 {
2089 struct jme_adapter *jme = netdev_priv(netdev);
2090
2091 jme->phylink = 0;
2092 jme_reset_phy_processor(jme);
2093 if (test_bit(JME_FLAG_SSET, &jme->flags))
2094 jme_set_settings(netdev, &jme->old_ecmd);
2095
2096 /*
2097 * Force to Reset the link again
2098 */
2099 jme_reset_link(jme);
2100 }
2101
2102 static inline void jme_pause_rx(struct jme_adapter *jme)
2103 {
2104 atomic_dec(&jme->link_changing);
2105
2106 jme_set_rx_pcc(jme, PCC_OFF);
2107 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2108 JME_NAPI_DISABLE(jme);
2109 } else {
2110 tasklet_disable(&jme->rxclean_task);
2111 tasklet_disable(&jme->rxempty_task);
2112 }
2113 }
2114
2115 static inline void jme_resume_rx(struct jme_adapter *jme)
2116 {
2117 struct dynpcc_info *dpi = &(jme->dpi);
2118
2119 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2120 JME_NAPI_ENABLE(jme);
2121 } else {
2122 tasklet_hi_enable(&jme->rxclean_task);
2123 tasklet_hi_enable(&jme->rxempty_task);
2124 }
2125 dpi->cur = PCC_P1;
2126 dpi->attempt = PCC_P1;
2127 dpi->cnt = 0;
2128 jme_set_rx_pcc(jme, PCC_P1);
2129
2130 atomic_inc(&jme->link_changing);
2131 }
2132
2133 static void
2134 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2135 {
2136 struct jme_adapter *jme = netdev_priv(netdev);
2137
2138 jme_pause_rx(jme);
2139 jme->vlgrp = grp;
2140 jme_resume_rx(jme);
2141 }
2142
2143 static void
2144 jme_get_drvinfo(struct net_device *netdev,
2145 struct ethtool_drvinfo *info)
2146 {
2147 struct jme_adapter *jme = netdev_priv(netdev);
2148
2149 strcpy(info->driver, DRV_NAME);
2150 strcpy(info->version, DRV_VERSION);
2151 strcpy(info->bus_info, pci_name(jme->pdev));
2152 }
2153
2154 static int
2155 jme_get_regs_len(struct net_device *netdev)
2156 {
2157 return JME_REG_LEN;
2158 }
2159
2160 static void
2161 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2162 {
2163 int i;
2164
2165 for (i = 0 ; i < len ; i += 4)
2166 p[i >> 2] = jread32(jme, reg + i);
2167 }
2168
2169 static void
2170 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2171 {
2172 int i;
2173 u16 *p16 = (u16 *)p;
2174
2175 for (i = 0 ; i < reg_nr ; ++i)
2176 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2177 }
2178
2179 static void
2180 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2181 {
2182 struct jme_adapter *jme = netdev_priv(netdev);
2183 u32 *p32 = (u32 *)p;
2184
2185 memset(p, 0xFF, JME_REG_LEN);
2186
2187 regs->version = 1;
2188 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2189
2190 p32 += 0x100 >> 2;
2191 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2192
2193 p32 += 0x100 >> 2;
2194 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2195
2196 p32 += 0x100 >> 2;
2197 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2198
2199 p32 += 0x100 >> 2;
2200 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2201 }
2202
2203 static int
2204 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2205 {
2206 struct jme_adapter *jme = netdev_priv(netdev);
2207
2208 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2209 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2210
2211 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2212 ecmd->use_adaptive_rx_coalesce = false;
2213 ecmd->rx_coalesce_usecs = 0;
2214 ecmd->rx_max_coalesced_frames = 0;
2215 return 0;
2216 }
2217
2218 ecmd->use_adaptive_rx_coalesce = true;
2219
2220 switch (jme->dpi.cur) {
2221 case PCC_P1:
2222 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2223 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2224 break;
2225 case PCC_P2:
2226 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2227 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2228 break;
2229 case PCC_P3:
2230 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2231 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2232 break;
2233 default:
2234 break;
2235 }
2236
2237 return 0;
2238 }
2239
2240 static int
2241 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2242 {
2243 struct jme_adapter *jme = netdev_priv(netdev);
2244 struct dynpcc_info *dpi = &(jme->dpi);
2245
2246 if (netif_running(netdev))
2247 return -EBUSY;
2248
2249 if (ecmd->use_adaptive_rx_coalesce
2250 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2251 clear_bit(JME_FLAG_POLL, &jme->flags);
2252 jme->jme_rx = netif_rx;
2253 jme->jme_vlan_rx = vlan_hwaccel_rx;
2254 dpi->cur = PCC_P1;
2255 dpi->attempt = PCC_P1;
2256 dpi->cnt = 0;
2257 jme_set_rx_pcc(jme, PCC_P1);
2258 jme_interrupt_mode(jme);
2259 } else if (!(ecmd->use_adaptive_rx_coalesce)
2260 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2261 set_bit(JME_FLAG_POLL, &jme->flags);
2262 jme->jme_rx = netif_receive_skb;
2263 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2264 jme_interrupt_mode(jme);
2265 }
2266
2267 return 0;
2268 }
2269
2270 static void
2271 jme_get_pauseparam(struct net_device *netdev,
2272 struct ethtool_pauseparam *ecmd)
2273 {
2274 struct jme_adapter *jme = netdev_priv(netdev);
2275 u32 val;
2276
2277 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2278 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2279
2280 spin_lock_bh(&jme->phy_lock);
2281 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2282 spin_unlock_bh(&jme->phy_lock);
2283
2284 ecmd->autoneg =
2285 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2286 }
2287
2288 static int
2289 jme_set_pauseparam(struct net_device *netdev,
2290 struct ethtool_pauseparam *ecmd)
2291 {
2292 struct jme_adapter *jme = netdev_priv(netdev);
2293 u32 val;
2294
2295 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2296 (ecmd->tx_pause != 0)) {
2297
2298 if (ecmd->tx_pause)
2299 jme->reg_txpfc |= TXPFC_PF_EN;
2300 else
2301 jme->reg_txpfc &= ~TXPFC_PF_EN;
2302
2303 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2304 }
2305
2306 spin_lock_bh(&jme->rxmcs_lock);
2307 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2308 (ecmd->rx_pause != 0)) {
2309
2310 if (ecmd->rx_pause)
2311 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2312 else
2313 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2314
2315 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2316 }
2317 spin_unlock_bh(&jme->rxmcs_lock);
2318
2319 spin_lock_bh(&jme->phy_lock);
2320 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2321 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2322 (ecmd->autoneg != 0)) {
2323
2324 if (ecmd->autoneg)
2325 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2326 else
2327 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2328
2329 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2330 MII_ADVERTISE, val);
2331 }
2332 spin_unlock_bh(&jme->phy_lock);
2333
2334 return 0;
2335 }
2336
2337 static void
2338 jme_get_wol(struct net_device *netdev,
2339 struct ethtool_wolinfo *wol)
2340 {
2341 struct jme_adapter *jme = netdev_priv(netdev);
2342
2343 wol->supported = WAKE_MAGIC | WAKE_PHY;
2344
2345 wol->wolopts = 0;
2346
2347 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2348 wol->wolopts |= WAKE_PHY;
2349
2350 if (jme->reg_pmcs & PMCS_MFEN)
2351 wol->wolopts |= WAKE_MAGIC;
2352
2353 }
2354
2355 static int
2356 jme_set_wol(struct net_device *netdev,
2357 struct ethtool_wolinfo *wol)
2358 {
2359 struct jme_adapter *jme = netdev_priv(netdev);
2360
2361 if (wol->wolopts & (WAKE_MAGICSECURE |
2362 WAKE_UCAST |
2363 WAKE_MCAST |
2364 WAKE_BCAST |
2365 WAKE_ARP))
2366 return -EOPNOTSUPP;
2367
2368 jme->reg_pmcs = 0;
2369
2370 if (wol->wolopts & WAKE_PHY)
2371 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2372
2373 if (wol->wolopts & WAKE_MAGIC)
2374 jme->reg_pmcs |= PMCS_MFEN;
2375
2376 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2377
2378 return 0;
2379 }
2380
2381 static int
2382 jme_get_settings(struct net_device *netdev,
2383 struct ethtool_cmd *ecmd)
2384 {
2385 struct jme_adapter *jme = netdev_priv(netdev);
2386 int rc;
2387
2388 spin_lock_bh(&jme->phy_lock);
2389 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2390 spin_unlock_bh(&jme->phy_lock);
2391 return rc;
2392 }
2393
2394 static int
2395 jme_set_settings(struct net_device *netdev,
2396 struct ethtool_cmd *ecmd)
2397 {
2398 struct jme_adapter *jme = netdev_priv(netdev);
2399 int rc, fdc = 0;
2400
2401 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2402 return -EINVAL;
2403
2404 if (jme->mii_if.force_media &&
2405 ecmd->autoneg != AUTONEG_ENABLE &&
2406 (jme->mii_if.full_duplex != ecmd->duplex))
2407 fdc = 1;
2408
2409 spin_lock_bh(&jme->phy_lock);
2410 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2411 spin_unlock_bh(&jme->phy_lock);
2412
2413 if (!rc && fdc)
2414 jme_reset_link(jme);
2415
2416 if (!rc) {
2417 set_bit(JME_FLAG_SSET, &jme->flags);
2418 jme->old_ecmd = *ecmd;
2419 }
2420
2421 return rc;
2422 }
2423
2424 static u32
2425 jme_get_link(struct net_device *netdev)
2426 {
2427 struct jme_adapter *jme = netdev_priv(netdev);
2428 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2429 }
2430
2431 static u32
2432 jme_get_msglevel(struct net_device *netdev)
2433 {
2434 struct jme_adapter *jme = netdev_priv(netdev);
2435 return jme->msg_enable;
2436 }
2437
2438 static void
2439 jme_set_msglevel(struct net_device *netdev, u32 value)
2440 {
2441 struct jme_adapter *jme = netdev_priv(netdev);
2442 jme->msg_enable = value;
2443 }
2444
2445 static u32
2446 jme_get_rx_csum(struct net_device *netdev)
2447 {
2448 struct jme_adapter *jme = netdev_priv(netdev);
2449 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2450 }
2451
2452 static int
2453 jme_set_rx_csum(struct net_device *netdev, u32 on)
2454 {
2455 struct jme_adapter *jme = netdev_priv(netdev);
2456
2457 spin_lock_bh(&jme->rxmcs_lock);
2458 if (on)
2459 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2460 else
2461 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2462 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2463 spin_unlock_bh(&jme->rxmcs_lock);
2464
2465 return 0;
2466 }
2467
2468 static int
2469 jme_set_tx_csum(struct net_device *netdev, u32 on)
2470 {
2471 struct jme_adapter *jme = netdev_priv(netdev);
2472
2473 if (on) {
2474 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2475 if (netdev->mtu <= 1900)
2476 netdev->features |= NETIF_F_HW_CSUM;
2477 } else {
2478 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2479 netdev->features &= ~NETIF_F_HW_CSUM;
2480 }
2481
2482 return 0;
2483 }
2484
2485 static int
2486 jme_set_tso(struct net_device *netdev, u32 on)
2487 {
2488 struct jme_adapter *jme = netdev_priv(netdev);
2489
2490 if (on) {
2491 set_bit(JME_FLAG_TSO, &jme->flags);
2492 if (netdev->mtu <= 1900)
2493 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2494 } else {
2495 clear_bit(JME_FLAG_TSO, &jme->flags);
2496 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2497 }
2498
2499 return 0;
2500 }
2501
2502 static int
2503 jme_nway_reset(struct net_device *netdev)
2504 {
2505 struct jme_adapter *jme = netdev_priv(netdev);
2506 jme_restart_an(jme);
2507 return 0;
2508 }
2509
2510 static u8
2511 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2512 {
2513 u32 val;
2514 int to;
2515
2516 val = jread32(jme, JME_SMBCSR);
2517 to = JME_SMB_BUSY_TIMEOUT;
2518 while ((val & SMBCSR_BUSY) && --to) {
2519 msleep(1);
2520 val = jread32(jme, JME_SMBCSR);
2521 }
2522 if (!to) {
2523 msg_hw(jme, "SMB Bus Busy.\n");
2524 return 0xFF;
2525 }
2526
2527 jwrite32(jme, JME_SMBINTF,
2528 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2529 SMBINTF_HWRWN_READ |
2530 SMBINTF_HWCMD);
2531
2532 val = jread32(jme, JME_SMBINTF);
2533 to = JME_SMB_BUSY_TIMEOUT;
2534 while ((val & SMBINTF_HWCMD) && --to) {
2535 msleep(1);
2536 val = jread32(jme, JME_SMBINTF);
2537 }
2538 if (!to) {
2539 msg_hw(jme, "SMB Bus Busy.\n");
2540 return 0xFF;
2541 }
2542
2543 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2544 }
2545
2546 static void
2547 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2548 {
2549 u32 val;
2550 int to;
2551
2552 val = jread32(jme, JME_SMBCSR);
2553 to = JME_SMB_BUSY_TIMEOUT;
2554 while ((val & SMBCSR_BUSY) && --to) {
2555 msleep(1);
2556 val = jread32(jme, JME_SMBCSR);
2557 }
2558 if (!to) {
2559 msg_hw(jme, "SMB Bus Busy.\n");
2560 return;
2561 }
2562
2563 jwrite32(jme, JME_SMBINTF,
2564 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2565 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2566 SMBINTF_HWRWN_WRITE |
2567 SMBINTF_HWCMD);
2568
2569 val = jread32(jme, JME_SMBINTF);
2570 to = JME_SMB_BUSY_TIMEOUT;
2571 while ((val & SMBINTF_HWCMD) && --to) {
2572 msleep(1);
2573 val = jread32(jme, JME_SMBINTF);
2574 }
2575 if (!to) {
2576 msg_hw(jme, "SMB Bus Busy.\n");
2577 return;
2578 }
2579
2580 mdelay(2);
2581 }
2582
2583 static int
2584 jme_get_eeprom_len(struct net_device *netdev)
2585 {
2586 struct jme_adapter *jme = netdev_priv(netdev);
2587 u32 val;
2588 val = jread32(jme, JME_SMBCSR);
2589 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2590 }
2591
2592 static int
2593 jme_get_eeprom(struct net_device *netdev,
2594 struct ethtool_eeprom *eeprom, u8 *data)
2595 {
2596 struct jme_adapter *jme = netdev_priv(netdev);
2597 int i, offset = eeprom->offset, len = eeprom->len;
2598
2599 /*
2600 * ethtool will check the boundary for us
2601 */
2602 eeprom->magic = JME_EEPROM_MAGIC;
2603 for (i = 0 ; i < len ; ++i)
2604 data[i] = jme_smb_read(jme, i + offset);
2605
2606 return 0;
2607 }
2608
2609 static int
2610 jme_set_eeprom(struct net_device *netdev,
2611 struct ethtool_eeprom *eeprom, u8 *data)
2612 {
2613 struct jme_adapter *jme = netdev_priv(netdev);
2614 int i, offset = eeprom->offset, len = eeprom->len;
2615
2616 if (eeprom->magic != JME_EEPROM_MAGIC)
2617 return -EINVAL;
2618
2619 /*
2620 * ethtool will check the boundary for us
2621 */
2622 for (i = 0 ; i < len ; ++i)
2623 jme_smb_write(jme, i + offset, data[i]);
2624
2625 return 0;
2626 }
2627
2628 static const struct ethtool_ops jme_ethtool_ops = {
2629 .get_drvinfo = jme_get_drvinfo,
2630 .get_regs_len = jme_get_regs_len,
2631 .get_regs = jme_get_regs,
2632 .get_coalesce = jme_get_coalesce,
2633 .set_coalesce = jme_set_coalesce,
2634 .get_pauseparam = jme_get_pauseparam,
2635 .set_pauseparam = jme_set_pauseparam,
2636 .get_wol = jme_get_wol,
2637 .set_wol = jme_set_wol,
2638 .get_settings = jme_get_settings,
2639 .set_settings = jme_set_settings,
2640 .get_link = jme_get_link,
2641 .get_msglevel = jme_get_msglevel,
2642 .set_msglevel = jme_set_msglevel,
2643 .get_rx_csum = jme_get_rx_csum,
2644 .set_rx_csum = jme_set_rx_csum,
2645 .set_tx_csum = jme_set_tx_csum,
2646 .set_tso = jme_set_tso,
2647 .set_sg = ethtool_op_set_sg,
2648 .nway_reset = jme_nway_reset,
2649 .get_eeprom_len = jme_get_eeprom_len,
2650 .get_eeprom = jme_get_eeprom,
2651 .set_eeprom = jme_set_eeprom,
2652 };
2653
2654 static int
2655 jme_pci_dma64(struct pci_dev *pdev)
2656 {
2657 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2658 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2659 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2660 return 1;
2661
2662 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2663 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2664 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2665 return 1;
2666
2667 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2668 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2669 return 0;
2670
2671 return -1;
2672 }
2673
2674 static inline void
2675 jme_phy_init(struct jme_adapter *jme)
2676 {
2677 u16 reg26;
2678
2679 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2680 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2681 }
2682
2683 static inline void
2684 jme_check_hw_ver(struct jme_adapter *jme)
2685 {
2686 u32 chipmode;
2687
2688 chipmode = jread32(jme, JME_CHIPMODE);
2689
2690 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2691 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2692 }
2693
2694 static const struct net_device_ops jme_netdev_ops = {
2695 .ndo_open = jme_open,
2696 .ndo_stop = jme_close,
2697 .ndo_validate_addr = eth_validate_addr,
2698 .ndo_start_xmit = jme_start_xmit,
2699 .ndo_set_mac_address = jme_set_macaddr,
2700 .ndo_set_multicast_list = jme_set_multi,
2701 .ndo_change_mtu = jme_change_mtu,
2702 .ndo_tx_timeout = jme_tx_timeout,
2703 .ndo_vlan_rx_register = jme_vlan_rx_register,
2704 };
2705
2706 static int __devinit
2707 jme_init_one(struct pci_dev *pdev,
2708 const struct pci_device_id *ent)
2709 {
2710 int rc = 0, using_dac, i;
2711 struct net_device *netdev;
2712 struct jme_adapter *jme;
2713 u16 bmcr, bmsr;
2714 u32 apmc;
2715
2716 /*
2717 * set up PCI device basics
2718 */
2719 rc = pci_enable_device(pdev);
2720 if (rc) {
2721 jeprintk(pdev, "Cannot enable PCI device.\n");
2722 goto err_out;
2723 }
2724
2725 using_dac = jme_pci_dma64(pdev);
2726 if (using_dac < 0) {
2727 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2728 rc = -EIO;
2729 goto err_out_disable_pdev;
2730 }
2731
2732 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2733 jeprintk(pdev, "No PCI resource region found.\n");
2734 rc = -ENOMEM;
2735 goto err_out_disable_pdev;
2736 }
2737
2738 rc = pci_request_regions(pdev, DRV_NAME);
2739 if (rc) {
2740 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2741 goto err_out_disable_pdev;
2742 }
2743
2744 pci_set_master(pdev);
2745
2746 /*
2747 * alloc and init net device
2748 */
2749 netdev = alloc_etherdev(sizeof(*jme));
2750 if (!netdev) {
2751 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2752 rc = -ENOMEM;
2753 goto err_out_release_regions;
2754 }
2755 netdev->netdev_ops = &jme_netdev_ops;
2756 netdev->ethtool_ops = &jme_ethtool_ops;
2757 netdev->watchdog_timeo = TX_TIMEOUT;
2758 netdev->features = NETIF_F_HW_CSUM |
2759 NETIF_F_SG |
2760 NETIF_F_TSO |
2761 NETIF_F_TSO6 |
2762 NETIF_F_HW_VLAN_TX |
2763 NETIF_F_HW_VLAN_RX;
2764 if (using_dac)
2765 netdev->features |= NETIF_F_HIGHDMA;
2766
2767 SET_NETDEV_DEV(netdev, &pdev->dev);
2768 pci_set_drvdata(pdev, netdev);
2769
2770 /*
2771 * init adapter info
2772 */
2773 jme = netdev_priv(netdev);
2774 jme->pdev = pdev;
2775 jme->dev = netdev;
2776 jme->jme_rx = netif_rx;
2777 jme->jme_vlan_rx = vlan_hwaccel_rx;
2778 jme->old_mtu = netdev->mtu = 1500;
2779 jme->phylink = 0;
2780 jme->tx_ring_size = 1 << 10;
2781 jme->tx_ring_mask = jme->tx_ring_size - 1;
2782 jme->tx_wake_threshold = 1 << 9;
2783 jme->rx_ring_size = 1 << 9;
2784 jme->rx_ring_mask = jme->rx_ring_size - 1;
2785 jme->msg_enable = JME_DEF_MSG_ENABLE;
2786 jme->regs = ioremap(pci_resource_start(pdev, 0),
2787 pci_resource_len(pdev, 0));
2788 if (!(jme->regs)) {
2789 jeprintk(pdev, "Mapping PCI resource region error.\n");
2790 rc = -ENOMEM;
2791 goto err_out_free_netdev;
2792 }
2793
2794 if (no_pseudohp) {
2795 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2796 jwrite32(jme, JME_APMC, apmc);
2797 } else if (force_pseudohp) {
2798 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2799 jwrite32(jme, JME_APMC, apmc);
2800 }
2801
2802 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2803
2804 spin_lock_init(&jme->phy_lock);
2805 spin_lock_init(&jme->macaddr_lock);
2806 spin_lock_init(&jme->rxmcs_lock);
2807
2808 atomic_set(&jme->link_changing, 1);
2809 atomic_set(&jme->rx_cleaning, 1);
2810 atomic_set(&jme->tx_cleaning, 1);
2811 atomic_set(&jme->rx_empty, 1);
2812
2813 tasklet_init(&jme->pcc_task,
2814 &jme_pcc_tasklet,
2815 (unsigned long) jme);
2816 tasklet_init(&jme->linkch_task,
2817 &jme_link_change_tasklet,
2818 (unsigned long) jme);
2819 tasklet_init(&jme->txclean_task,
2820 &jme_tx_clean_tasklet,
2821 (unsigned long) jme);
2822 tasklet_init(&jme->rxclean_task,
2823 &jme_rx_clean_tasklet,
2824 (unsigned long) jme);
2825 tasklet_init(&jme->rxempty_task,
2826 &jme_rx_empty_tasklet,
2827 (unsigned long) jme);
2828 tasklet_disable_nosync(&jme->linkch_task);
2829 tasklet_disable_nosync(&jme->txclean_task);
2830 tasklet_disable_nosync(&jme->rxclean_task);
2831 tasklet_disable_nosync(&jme->rxempty_task);
2832 jme->dpi.cur = PCC_P1;
2833
2834 jme->reg_ghc = 0;
2835 jme->reg_rxcs = RXCS_DEFAULT;
2836 jme->reg_rxmcs = RXMCS_DEFAULT;
2837 jme->reg_txpfc = 0;
2838 jme->reg_pmcs = PMCS_MFEN;
2839 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2840 set_bit(JME_FLAG_TSO, &jme->flags);
2841
2842 /*
2843 * Get Max Read Req Size from PCI Config Space
2844 */
2845 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2846 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2847 switch (jme->mrrs) {
2848 case MRRS_128B:
2849 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2850 break;
2851 case MRRS_256B:
2852 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2853 break;
2854 default:
2855 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2856 break;
2857 };
2858
2859 /*
2860 * Must check before reset_mac_processor
2861 */
2862 jme_check_hw_ver(jme);
2863 jme->mii_if.dev = netdev;
2864 if (jme->fpgaver) {
2865 jme->mii_if.phy_id = 0;
2866 for (i = 1 ; i < 32 ; ++i) {
2867 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2868 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2869 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2870 jme->mii_if.phy_id = i;
2871 break;
2872 }
2873 }
2874
2875 if (!jme->mii_if.phy_id) {
2876 rc = -EIO;
2877 jeprintk(pdev, "Can not find phy_id.\n");
2878 goto err_out_unmap;
2879 }
2880
2881 jme->reg_ghc |= GHC_LINK_POLL;
2882 } else {
2883 jme->mii_if.phy_id = 1;
2884 }
2885 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2886 jme->mii_if.supports_gmii = true;
2887 else
2888 jme->mii_if.supports_gmii = false;
2889 jme->mii_if.mdio_read = jme_mdio_read;
2890 jme->mii_if.mdio_write = jme_mdio_write;
2891
2892 jme_clear_pm(jme);
2893 jme_set_phyfifoa(jme);
2894 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2895 if (!jme->fpgaver)
2896 jme_phy_init(jme);
2897 jme_phy_off(jme);
2898
2899 /*
2900 * Reset MAC processor and reload EEPROM for MAC Address
2901 */
2902 jme_reset_mac_processor(jme);
2903 rc = jme_reload_eeprom(jme);
2904 if (rc) {
2905 jeprintk(pdev,
2906 "Reload eeprom for reading MAC Address error.\n");
2907 goto err_out_unmap;
2908 }
2909 jme_load_macaddr(netdev);
2910
2911 /*
2912 * Tell stack that we are not ready to work until open()
2913 */
2914 netif_carrier_off(netdev);
2915 netif_stop_queue(netdev);
2916
2917 /*
2918 * Register netdev
2919 */
2920 rc = register_netdev(netdev);
2921 if (rc) {
2922 jeprintk(pdev, "Cannot register net device.\n");
2923 goto err_out_unmap;
2924 }
2925
2926 msg_probe(jme, "%s%s ver:%x rev:%x macaddr:%pM\n",
2927 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2928 "JMC250 Gigabit Ethernet" :
2929 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2930 "JMC260 Fast Ethernet" : "Unknown",
2931 (jme->fpgaver != 0) ? " (FPGA)" : "",
2932 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2933 jme->rev, netdev->dev_addr);
2934
2935 return 0;
2936
2937 err_out_unmap:
2938 iounmap(jme->regs);
2939 err_out_free_netdev:
2940 pci_set_drvdata(pdev, NULL);
2941 free_netdev(netdev);
2942 err_out_release_regions:
2943 pci_release_regions(pdev);
2944 err_out_disable_pdev:
2945 pci_disable_device(pdev);
2946 err_out:
2947 return rc;
2948 }
2949
2950 static void __devexit
2951 jme_remove_one(struct pci_dev *pdev)
2952 {
2953 struct net_device *netdev = pci_get_drvdata(pdev);
2954 struct jme_adapter *jme = netdev_priv(netdev);
2955
2956 unregister_netdev(netdev);
2957 iounmap(jme->regs);
2958 pci_set_drvdata(pdev, NULL);
2959 free_netdev(netdev);
2960 pci_release_regions(pdev);
2961 pci_disable_device(pdev);
2962
2963 }
2964
2965 #ifdef CONFIG_PM
2966 static int
2967 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2968 {
2969 struct net_device *netdev = pci_get_drvdata(pdev);
2970 struct jme_adapter *jme = netdev_priv(netdev);
2971
2972 atomic_dec(&jme->link_changing);
2973
2974 netif_device_detach(netdev);
2975 netif_stop_queue(netdev);
2976 jme_stop_irq(jme);
2977
2978 tasklet_disable(&jme->txclean_task);
2979 tasklet_disable(&jme->rxclean_task);
2980 tasklet_disable(&jme->rxempty_task);
2981
2982 if (netif_carrier_ok(netdev)) {
2983 if (test_bit(JME_FLAG_POLL, &jme->flags))
2984 jme_polling_mode(jme);
2985
2986 jme_stop_pcc_timer(jme);
2987 jme_reset_ghc_speed(jme);
2988 jme_disable_rx_engine(jme);
2989 jme_disable_tx_engine(jme);
2990 jme_reset_mac_processor(jme);
2991 jme_free_rx_resources(jme);
2992 jme_free_tx_resources(jme);
2993 netif_carrier_off(netdev);
2994 jme->phylink = 0;
2995 }
2996
2997 tasklet_enable(&jme->txclean_task);
2998 tasklet_hi_enable(&jme->rxclean_task);
2999 tasklet_hi_enable(&jme->rxempty_task);
3000
3001 pci_save_state(pdev);
3002 if (jme->reg_pmcs) {
3003 jme_set_100m_half(jme);
3004
3005 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3006 jme_wait_link(jme);
3007
3008 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3009
3010 pci_enable_wake(pdev, PCI_D3cold, true);
3011 } else {
3012 jme_phy_off(jme);
3013 }
3014 pci_set_power_state(pdev, PCI_D3cold);
3015
3016 return 0;
3017 }
3018
3019 static int
3020 jme_resume(struct pci_dev *pdev)
3021 {
3022 struct net_device *netdev = pci_get_drvdata(pdev);
3023 struct jme_adapter *jme = netdev_priv(netdev);
3024
3025 jme_clear_pm(jme);
3026 pci_restore_state(pdev);
3027
3028 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3029 jme_phy_on(jme);
3030 jme_set_settings(netdev, &jme->old_ecmd);
3031 } else {
3032 jme_reset_phy_processor(jme);
3033 }
3034
3035 jme_start_irq(jme);
3036 netif_device_attach(netdev);
3037
3038 atomic_inc(&jme->link_changing);
3039
3040 jme_reset_link(jme);
3041
3042 return 0;
3043 }
3044 #endif
3045
3046 static struct pci_device_id jme_pci_tbl[] = {
3047 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3048 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3049 { }
3050 };
3051
3052 static struct pci_driver jme_driver = {
3053 .name = DRV_NAME,
3054 .id_table = jme_pci_tbl,
3055 .probe = jme_init_one,
3056 .remove = __devexit_p(jme_remove_one),
3057 #ifdef CONFIG_PM
3058 .suspend = jme_suspend,
3059 .resume = jme_resume,
3060 #endif /* CONFIG_PM */
3061 };
3062
3063 static int __init
3064 jme_init_module(void)
3065 {
3066 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3067 "driver version %s\n", DRV_VERSION);
3068 return pci_register_driver(&jme_driver);
3069 }
3070
3071 static void __exit
3072 jme_cleanup_module(void)
3073 {
3074 pci_unregister_driver(&jme_driver);
3075 }
3076
3077 module_init(jme_init_module);
3078 module_exit(jme_cleanup_module);
3079
3080 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3081 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3082 MODULE_LICENSE("GPL");
3083 MODULE_VERSION(DRV_VERSION);
3084 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3085
Linux with added FPC-III support