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x86: Cleanup highmap after brk is concluded
[linux/fpc-iii.git] / drivers / net / ucc_geth.c
blobb4b25ffa3ab7c6a199852604997d00869eda1f1d
1 /*
2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_platform.h>
32
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40
41 #include "ucc_geth.h"
42 #include "fsl_pq_mdio.h"
43
44 #undef DEBUG
45
46 #define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49 #define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
60 #else
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
64
65
66 static DEFINE_SPINLOCK(ugeth_lock);
67
68 static struct {
69 u32 msg_enable;
70 } debug = { -1 };
71
72 module_param_named(debug, debug.msg_enable, int, 0);
73 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
75 static struct ucc_geth_info ugeth_primary_info = {
76 .uf_info = {
77 .bd_mem_part = MEM_PART_SYSTEM,
78 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79 .max_rx_buf_length = 1536,
80 /* adjusted at startup if max-speed 1000 */
81 .urfs = UCC_GETH_URFS_INIT,
82 .urfet = UCC_GETH_URFET_INIT,
83 .urfset = UCC_GETH_URFSET_INIT,
84 .utfs = UCC_GETH_UTFS_INIT,
85 .utfet = UCC_GETH_UTFET_INIT,
86 .utftt = UCC_GETH_UTFTT_INIT,
87 .ufpt = 256,
88 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90 .tenc = UCC_FAST_TX_ENCODING_NRZ,
91 .renc = UCC_FAST_RX_ENCODING_NRZ,
92 .tcrc = UCC_FAST_16_BIT_CRC,
93 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94 },
95 .numQueuesTx = 1,
96 .numQueuesRx = 1,
97 .extendedFilteringChainPointer = ((uint32_t) NULL),
98 .typeorlen = 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1 = 0x40,
100 .nonBackToBackIfgPart2 = 0x60,
101 .miminumInterFrameGapEnforcement = 0x50,
102 .backToBackInterFrameGap = 0x60,
103 .mblinterval = 128,
104 .nortsrbytetime = 5,
105 .fracsiz = 1,
106 .strictpriorityq = 0xff,
107 .altBebTruncation = 0xa,
108 .excessDefer = 1,
109 .maxRetransmission = 0xf,
110 .collisionWindow = 0x37,
111 .receiveFlowControl = 1,
112 .transmitFlowControl = 1,
113 .maxGroupAddrInHash = 4,
114 .maxIndAddrInHash = 4,
115 .prel = 7,
116 .maxFrameLength = 1518,
117 .minFrameLength = 64,
118 .maxD1Length = 1520,
119 .maxD2Length = 1520,
120 .vlantype = 0x8100,
121 .ecamptr = ((uint32_t) NULL),
122 .eventRegMask = UCCE_OTHER,
123 .pausePeriod = 0xf000,
124 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125 .bdRingLenTx = {
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN},
134
135 .bdRingLenRx = {
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN},
144
145 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146 .largestexternallookupkeysize =
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
148 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
151 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
156 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
158 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 };
161
162 static struct ucc_geth_info ugeth_info[8];
163
164 #ifdef DEBUG
165 static void mem_disp(u8 *addr, int size)
166 {
167 u8 *i;
168 int size16Aling = (size >> 4) << 4;
169 int size4Aling = (size >> 2) << 2;
170 int notAlign = 0;
171 if (size % 16)
172 notAlign = 1;
173
174 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
176 (u32) i,
177 *((u32 *) (i)),
178 *((u32 *) (i + 4)),
179 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180 if (notAlign == 1)
181 printk("0x%08x: ", (u32) i);
182 for (; (u32) i < (u32) addr + size4Aling; i += 4)
183 printk("%08x ", *((u32 *) (i)));
184 for (; (u32) i < (u32) addr + size; i++)
185 printk("%02x", *((u8 *) (i)));
186 if (notAlign == 1)
187 printk("\r\n");
188 }
189 #endif /* DEBUG */
190
191 static struct list_head *dequeue(struct list_head *lh)
192 {
193 unsigned long flags;
194
195 spin_lock_irqsave(&ugeth_lock, flags);
196 if (!list_empty(lh)) {
197 struct list_head *node = lh->next;
198 list_del(node);
199 spin_unlock_irqrestore(&ugeth_lock, flags);
200 return node;
201 } else {
202 spin_unlock_irqrestore(&ugeth_lock, flags);
203 return NULL;
204 }
205 }
206
207 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
208 u8 __iomem *bd)
209 {
210 struct sk_buff *skb = NULL;
211
212 skb = __skb_dequeue(&ugeth->rx_recycle);
213 if (!skb)
214 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
215 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
216 if (skb == NULL)
217 return NULL;
218
219 /* We need the data buffer to be aligned properly. We will reserve
220 * as many bytes as needed to align the data properly
221 */
222 skb_reserve(skb,
223 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225 1)));
226
227 skb->dev = ugeth->ndev;
228
229 out_be32(&((struct qe_bd __iomem *)bd)->buf,
230 dma_map_single(ugeth->dev,
231 skb->data,
232 ugeth->ug_info->uf_info.max_rx_buf_length +
233 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
234 DMA_FROM_DEVICE));
235
236 out_be32((u32 __iomem *)bd,
237 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
238
239 return skb;
240 }
241
242 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
243 {
244 u8 __iomem *bd;
245 u32 bd_status;
246 struct sk_buff *skb;
247 int i;
248
249 bd = ugeth->p_rx_bd_ring[rxQ];
250 i = 0;
251
252 do {
253 bd_status = in_be32((u32 __iomem *)bd);
254 skb = get_new_skb(ugeth, bd);
255
256 if (!skb) /* If can not allocate data buffer,
257 abort. Cleanup will be elsewhere */
258 return -ENOMEM;
259
260 ugeth->rx_skbuff[rxQ][i] = skb;
261
262 /* advance the BD pointer */
263 bd += sizeof(struct qe_bd);
264 i++;
265 } while (!(bd_status & R_W));
266
267 return 0;
268 }
269
270 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
271 u32 *p_start,
272 u8 num_entries,
273 u32 thread_size,
274 u32 thread_alignment,
275 unsigned int risc,
276 int skip_page_for_first_entry)
277 {
278 u32 init_enet_offset;
279 u8 i;
280 int snum;
281
282 for (i = 0; i < num_entries; i++) {
283 if ((snum = qe_get_snum()) < 0) {
284 if (netif_msg_ifup(ugeth))
285 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
286 return snum;
287 }
288 if ((i == 0) && skip_page_for_first_entry)
289 /* First entry of Rx does not have page */
290 init_enet_offset = 0;
291 else {
292 init_enet_offset =
293 qe_muram_alloc(thread_size, thread_alignment);
294 if (IS_ERR_VALUE(init_enet_offset)) {
295 if (netif_msg_ifup(ugeth))
296 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
297 qe_put_snum((u8) snum);
298 return -ENOMEM;
299 }
300 }
301 *(p_start++) =
302 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
303 | risc;
304 }
305
306 return 0;
307 }
308
309 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
310 u32 *p_start,
311 u8 num_entries,
312 unsigned int risc,
313 int skip_page_for_first_entry)
314 {
315 u32 init_enet_offset;
316 u8 i;
317 int snum;
318
319 for (i = 0; i < num_entries; i++) {
320 u32 val = *p_start;
321
322 /* Check that this entry was actually valid --
323 needed in case failed in allocations */
324 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
325 snum =
326 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
327 ENET_INIT_PARAM_SNUM_SHIFT;
328 qe_put_snum((u8) snum);
329 if (!((i == 0) && skip_page_for_first_entry)) {
330 /* First entry of Rx does not have page */
331 init_enet_offset =
332 (val & ENET_INIT_PARAM_PTR_MASK);
333 qe_muram_free(init_enet_offset);
334 }
335 *p_start++ = 0;
336 }
337 }
338
339 return 0;
340 }
341
342 #ifdef DEBUG
343 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
344 u32 __iomem *p_start,
345 u8 num_entries,
346 u32 thread_size,
347 unsigned int risc,
348 int skip_page_for_first_entry)
349 {
350 u32 init_enet_offset;
351 u8 i;
352 int snum;
353
354 for (i = 0; i < num_entries; i++) {
355 u32 val = in_be32(p_start);
356
357 /* Check that this entry was actually valid --
358 needed in case failed in allocations */
359 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
360 snum =
361 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
362 ENET_INIT_PARAM_SNUM_SHIFT;
363 qe_put_snum((u8) snum);
364 if (!((i == 0) && skip_page_for_first_entry)) {
365 /* First entry of Rx does not have page */
366 init_enet_offset =
367 (in_be32(p_start) &
368 ENET_INIT_PARAM_PTR_MASK);
369 ugeth_info("Init enet entry %d:", i);
370 ugeth_info("Base address: 0x%08x",
371 (u32)
372 qe_muram_addr(init_enet_offset));
373 mem_disp(qe_muram_addr(init_enet_offset),
374 thread_size);
375 }
376 p_start++;
377 }
378 }
379
380 return 0;
381 }
382 #endif
383
384 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
385 {
386 kfree(enet_addr_cont);
387 }
388
389 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
390 {
391 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
392 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
393 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
394 }
395
396 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
397 {
398 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
399
400 if (!(paddr_num < NUM_OF_PADDRS)) {
401 ugeth_warn("%s: Illagel paddr_num.", __func__);
402 return -EINVAL;
403 }
404
405 p_82xx_addr_filt =
406 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
407 addressfiltering;
408
409 /* Writing address ff.ff.ff.ff.ff.ff disables address
410 recognition for this register */
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
413 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
414
415 return 0;
416 }
417
418 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
419 u8 *p_enet_addr)
420 {
421 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
422 u32 cecr_subblock;
423
424 p_82xx_addr_filt =
425 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
426 addressfiltering;
427
428 cecr_subblock =
429 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
430
431 /* Ethernet frames are defined in Little Endian mode,
432 therefor to insert */
433 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
434
435 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
436
437 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
438 QE_CR_PROTOCOL_ETHERNET, 0);
439 }
440
441 static inline int compare_addr(u8 **addr1, u8 **addr2)
442 {
443 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
444 }
445
446 #ifdef DEBUG
447 static void get_statistics(struct ucc_geth_private *ugeth,
448 struct ucc_geth_tx_firmware_statistics *
449 tx_firmware_statistics,
450 struct ucc_geth_rx_firmware_statistics *
451 rx_firmware_statistics,
452 struct ucc_geth_hardware_statistics *hardware_statistics)
453 {
454 struct ucc_fast __iomem *uf_regs;
455 struct ucc_geth __iomem *ug_regs;
456 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
457 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
458
459 ug_regs = ugeth->ug_regs;
460 uf_regs = (struct ucc_fast __iomem *) ug_regs;
461 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
462 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
463
464 /* Tx firmware only if user handed pointer and driver actually
465 gathers Tx firmware statistics */
466 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
467 tx_firmware_statistics->sicoltx =
468 in_be32(&p_tx_fw_statistics_pram->sicoltx);
469 tx_firmware_statistics->mulcoltx =
470 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
471 tx_firmware_statistics->latecoltxfr =
472 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
473 tx_firmware_statistics->frabortduecol =
474 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
475 tx_firmware_statistics->frlostinmactxer =
476 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
477 tx_firmware_statistics->carriersenseertx =
478 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
479 tx_firmware_statistics->frtxok =
480 in_be32(&p_tx_fw_statistics_pram->frtxok);
481 tx_firmware_statistics->txfrexcessivedefer =
482 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
483 tx_firmware_statistics->txpkts256 =
484 in_be32(&p_tx_fw_statistics_pram->txpkts256);
485 tx_firmware_statistics->txpkts512 =
486 in_be32(&p_tx_fw_statistics_pram->txpkts512);
487 tx_firmware_statistics->txpkts1024 =
488 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
489 tx_firmware_statistics->txpktsjumbo =
490 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
491 }
492
493 /* Rx firmware only if user handed pointer and driver actually
494 * gathers Rx firmware statistics */
495 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
496 int i;
497 rx_firmware_statistics->frrxfcser =
498 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
499 rx_firmware_statistics->fraligner =
500 in_be32(&p_rx_fw_statistics_pram->fraligner);
501 rx_firmware_statistics->inrangelenrxer =
502 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
503 rx_firmware_statistics->outrangelenrxer =
504 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
505 rx_firmware_statistics->frtoolong =
506 in_be32(&p_rx_fw_statistics_pram->frtoolong);
507 rx_firmware_statistics->runt =
508 in_be32(&p_rx_fw_statistics_pram->runt);
509 rx_firmware_statistics->verylongevent =
510 in_be32(&p_rx_fw_statistics_pram->verylongevent);
511 rx_firmware_statistics->symbolerror =
512 in_be32(&p_rx_fw_statistics_pram->symbolerror);
513 rx_firmware_statistics->dropbsy =
514 in_be32(&p_rx_fw_statistics_pram->dropbsy);
515 for (i = 0; i < 0x8; i++)
516 rx_firmware_statistics->res0[i] =
517 p_rx_fw_statistics_pram->res0[i];
518 rx_firmware_statistics->mismatchdrop =
519 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
520 rx_firmware_statistics->underpkts =
521 in_be32(&p_rx_fw_statistics_pram->underpkts);
522 rx_firmware_statistics->pkts256 =
523 in_be32(&p_rx_fw_statistics_pram->pkts256);
524 rx_firmware_statistics->pkts512 =
525 in_be32(&p_rx_fw_statistics_pram->pkts512);
526 rx_firmware_statistics->pkts1024 =
527 in_be32(&p_rx_fw_statistics_pram->pkts1024);
528 rx_firmware_statistics->pktsjumbo =
529 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
530 rx_firmware_statistics->frlossinmacer =
531 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
532 rx_firmware_statistics->pausefr =
533 in_be32(&p_rx_fw_statistics_pram->pausefr);
534 for (i = 0; i < 0x4; i++)
535 rx_firmware_statistics->res1[i] =
536 p_rx_fw_statistics_pram->res1[i];
537 rx_firmware_statistics->removevlan =
538 in_be32(&p_rx_fw_statistics_pram->removevlan);
539 rx_firmware_statistics->replacevlan =
540 in_be32(&p_rx_fw_statistics_pram->replacevlan);
541 rx_firmware_statistics->insertvlan =
542 in_be32(&p_rx_fw_statistics_pram->insertvlan);
543 }
544
545 /* Hardware only if user handed pointer and driver actually
546 gathers hardware statistics */
547 if (hardware_statistics &&
548 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
549 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
550 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
551 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
552 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
553 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
554 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
555 hardware_statistics->txok = in_be32(&ug_regs->txok);
556 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
557 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
558 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
559 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
560 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
561 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
562 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
563 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
564 }
565 }
566
567 static void dump_bds(struct ucc_geth_private *ugeth)
568 {
569 int i;
570 int length;
571
572 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
573 if (ugeth->p_tx_bd_ring[i]) {
574 length =
575 (ugeth->ug_info->bdRingLenTx[i] *
576 sizeof(struct qe_bd));
577 ugeth_info("TX BDs[%d]", i);
578 mem_disp(ugeth->p_tx_bd_ring[i], length);
579 }
580 }
581 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
582 if (ugeth->p_rx_bd_ring[i]) {
583 length =
584 (ugeth->ug_info->bdRingLenRx[i] *
585 sizeof(struct qe_bd));
586 ugeth_info("RX BDs[%d]", i);
587 mem_disp(ugeth->p_rx_bd_ring[i], length);
588 }
589 }
590 }
591
592 static void dump_regs(struct ucc_geth_private *ugeth)
593 {
594 int i;
595
596 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
597 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
598
599 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
600 (u32) & ugeth->ug_regs->maccfg1,
601 in_be32(&ugeth->ug_regs->maccfg1));
602 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
603 (u32) & ugeth->ug_regs->maccfg2,
604 in_be32(&ugeth->ug_regs->maccfg2));
605 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
606 (u32) & ugeth->ug_regs->ipgifg,
607 in_be32(&ugeth->ug_regs->ipgifg));
608 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
609 (u32) & ugeth->ug_regs->hafdup,
610 in_be32(&ugeth->ug_regs->hafdup));
611 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
612 (u32) & ugeth->ug_regs->ifctl,
613 in_be32(&ugeth->ug_regs->ifctl));
614 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
615 (u32) & ugeth->ug_regs->ifstat,
616 in_be32(&ugeth->ug_regs->ifstat));
617 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
618 (u32) & ugeth->ug_regs->macstnaddr1,
619 in_be32(&ugeth->ug_regs->macstnaddr1));
620 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
621 (u32) & ugeth->ug_regs->macstnaddr2,
622 in_be32(&ugeth->ug_regs->macstnaddr2));
623 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
624 (u32) & ugeth->ug_regs->uempr,
625 in_be32(&ugeth->ug_regs->uempr));
626 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
627 (u32) & ugeth->ug_regs->utbipar,
628 in_be32(&ugeth->ug_regs->utbipar));
629 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
630 (u32) & ugeth->ug_regs->uescr,
631 in_be16(&ugeth->ug_regs->uescr));
632 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
633 (u32) & ugeth->ug_regs->tx64,
634 in_be32(&ugeth->ug_regs->tx64));
635 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
636 (u32) & ugeth->ug_regs->tx127,
637 in_be32(&ugeth->ug_regs->tx127));
638 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
639 (u32) & ugeth->ug_regs->tx255,
640 in_be32(&ugeth->ug_regs->tx255));
641 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
642 (u32) & ugeth->ug_regs->rx64,
643 in_be32(&ugeth->ug_regs->rx64));
644 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
645 (u32) & ugeth->ug_regs->rx127,
646 in_be32(&ugeth->ug_regs->rx127));
647 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
648 (u32) & ugeth->ug_regs->rx255,
649 in_be32(&ugeth->ug_regs->rx255));
650 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
651 (u32) & ugeth->ug_regs->txok,
652 in_be32(&ugeth->ug_regs->txok));
653 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
654 (u32) & ugeth->ug_regs->txcf,
655 in_be16(&ugeth->ug_regs->txcf));
656 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
657 (u32) & ugeth->ug_regs->tmca,
658 in_be32(&ugeth->ug_regs->tmca));
659 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
660 (u32) & ugeth->ug_regs->tbca,
661 in_be32(&ugeth->ug_regs->tbca));
662 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
663 (u32) & ugeth->ug_regs->rxfok,
664 in_be32(&ugeth->ug_regs->rxfok));
665 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
666 (u32) & ugeth->ug_regs->rxbok,
667 in_be32(&ugeth->ug_regs->rxbok));
668 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
669 (u32) & ugeth->ug_regs->rbyt,
670 in_be32(&ugeth->ug_regs->rbyt));
671 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
672 (u32) & ugeth->ug_regs->rmca,
673 in_be32(&ugeth->ug_regs->rmca));
674 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
675 (u32) & ugeth->ug_regs->rbca,
676 in_be32(&ugeth->ug_regs->rbca));
677 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
678 (u32) & ugeth->ug_regs->scar,
679 in_be32(&ugeth->ug_regs->scar));
680 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
681 (u32) & ugeth->ug_regs->scam,
682 in_be32(&ugeth->ug_regs->scam));
683
684 if (ugeth->p_thread_data_tx) {
685 int numThreadsTxNumerical;
686 switch (ugeth->ug_info->numThreadsTx) {
687 case UCC_GETH_NUM_OF_THREADS_1:
688 numThreadsTxNumerical = 1;
689 break;
690 case UCC_GETH_NUM_OF_THREADS_2:
691 numThreadsTxNumerical = 2;
692 break;
693 case UCC_GETH_NUM_OF_THREADS_4:
694 numThreadsTxNumerical = 4;
695 break;
696 case UCC_GETH_NUM_OF_THREADS_6:
697 numThreadsTxNumerical = 6;
698 break;
699 case UCC_GETH_NUM_OF_THREADS_8:
700 numThreadsTxNumerical = 8;
701 break;
702 default:
703 numThreadsTxNumerical = 0;
704 break;
705 }
706
707 ugeth_info("Thread data TXs:");
708 ugeth_info("Base address: 0x%08x",
709 (u32) ugeth->p_thread_data_tx);
710 for (i = 0; i < numThreadsTxNumerical; i++) {
711 ugeth_info("Thread data TX[%d]:", i);
712 ugeth_info("Base address: 0x%08x",
713 (u32) & ugeth->p_thread_data_tx[i]);
714 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
715 sizeof(struct ucc_geth_thread_data_tx));
716 }
717 }
718 if (ugeth->p_thread_data_rx) {
719 int numThreadsRxNumerical;
720 switch (ugeth->ug_info->numThreadsRx) {
721 case UCC_GETH_NUM_OF_THREADS_1:
722 numThreadsRxNumerical = 1;
723 break;
724 case UCC_GETH_NUM_OF_THREADS_2:
725 numThreadsRxNumerical = 2;
726 break;
727 case UCC_GETH_NUM_OF_THREADS_4:
728 numThreadsRxNumerical = 4;
729 break;
730 case UCC_GETH_NUM_OF_THREADS_6:
731 numThreadsRxNumerical = 6;
732 break;
733 case UCC_GETH_NUM_OF_THREADS_8:
734 numThreadsRxNumerical = 8;
735 break;
736 default:
737 numThreadsRxNumerical = 0;
738 break;
739 }
740
741 ugeth_info("Thread data RX:");
742 ugeth_info("Base address: 0x%08x",
743 (u32) ugeth->p_thread_data_rx);
744 for (i = 0; i < numThreadsRxNumerical; i++) {
745 ugeth_info("Thread data RX[%d]:", i);
746 ugeth_info("Base address: 0x%08x",
747 (u32) & ugeth->p_thread_data_rx[i]);
748 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
749 sizeof(struct ucc_geth_thread_data_rx));
750 }
751 }
752 if (ugeth->p_exf_glbl_param) {
753 ugeth_info("EXF global param:");
754 ugeth_info("Base address: 0x%08x",
755 (u32) ugeth->p_exf_glbl_param);
756 mem_disp((u8 *) ugeth->p_exf_glbl_param,
757 sizeof(*ugeth->p_exf_glbl_param));
758 }
759 if (ugeth->p_tx_glbl_pram) {
760 ugeth_info("TX global param:");
761 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
762 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
763 (u32) & ugeth->p_tx_glbl_pram->temoder,
764 in_be16(&ugeth->p_tx_glbl_pram->temoder));
765 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
766 (u32) & ugeth->p_tx_glbl_pram->sqptr,
767 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
768 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
769 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
770 in_be32(&ugeth->p_tx_glbl_pram->
771 schedulerbasepointer));
772 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
773 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
774 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
775 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
776 (u32) & ugeth->p_tx_glbl_pram->tstate,
777 in_be32(&ugeth->p_tx_glbl_pram->tstate));
778 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
779 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
780 ugeth->p_tx_glbl_pram->iphoffset[0]);
781 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
782 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
783 ugeth->p_tx_glbl_pram->iphoffset[1]);
784 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
785 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
786 ugeth->p_tx_glbl_pram->iphoffset[2]);
787 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
788 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
789 ugeth->p_tx_glbl_pram->iphoffset[3]);
790 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
791 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
792 ugeth->p_tx_glbl_pram->iphoffset[4]);
793 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
794 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
795 ugeth->p_tx_glbl_pram->iphoffset[5]);
796 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
797 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
798 ugeth->p_tx_glbl_pram->iphoffset[6]);
799 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
800 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
801 ugeth->p_tx_glbl_pram->iphoffset[7]);
802 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
803 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
804 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
805 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
806 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
807 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
808 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
809 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
810 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
811 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
812 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
813 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
814 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
815 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
816 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
817 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
818 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
819 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
820 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
821 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
822 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
823 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
824 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
825 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
826 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
827 (u32) & ugeth->p_tx_glbl_pram->tqptr,
828 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
829 }
830 if (ugeth->p_rx_glbl_pram) {
831 ugeth_info("RX global param:");
832 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
833 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
834 (u32) & ugeth->p_rx_glbl_pram->remoder,
835 in_be32(&ugeth->p_rx_glbl_pram->remoder));
836 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
837 (u32) & ugeth->p_rx_glbl_pram->rqptr,
838 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
839 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
840 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
841 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
842 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
843 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
844 ugeth->p_rx_glbl_pram->rxgstpack);
845 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
846 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
847 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
848 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
849 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
850 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
851 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
852 (u32) & ugeth->p_rx_glbl_pram->rstate,
853 ugeth->p_rx_glbl_pram->rstate);
854 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
855 (u32) & ugeth->p_rx_glbl_pram->mrblr,
856 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
857 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
858 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
859 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
860 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
861 (u32) & ugeth->p_rx_glbl_pram->mflr,
862 in_be16(&ugeth->p_rx_glbl_pram->mflr));
863 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
864 (u32) & ugeth->p_rx_glbl_pram->minflr,
865 in_be16(&ugeth->p_rx_glbl_pram->minflr));
866 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
867 (u32) & ugeth->p_rx_glbl_pram->maxd1,
868 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
869 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
870 (u32) & ugeth->p_rx_glbl_pram->maxd2,
871 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
872 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
873 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
874 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
875 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
876 (u32) & ugeth->p_rx_glbl_pram->l2qt,
877 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
878 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
879 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
880 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
881 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
882 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
883 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
884 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
885 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
886 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
887 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
888 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
889 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
890 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
891 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
892 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
893 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
894 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
895 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
896 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
897 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
898 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
899 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
900 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
901 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
902 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
903 (u32) & ugeth->p_rx_glbl_pram->vlantype,
904 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
905 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
906 (u32) & ugeth->p_rx_glbl_pram->vlantci,
907 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
908 for (i = 0; i < 64; i++)
909 ugeth_info
910 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
911 i,
912 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
913 ugeth->p_rx_glbl_pram->addressfiltering[i]);
914 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
915 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
916 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
917 }
918 if (ugeth->p_send_q_mem_reg) {
919 ugeth_info("Send Q memory registers:");
920 ugeth_info("Base address: 0x%08x",
921 (u32) ugeth->p_send_q_mem_reg);
922 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
923 ugeth_info("SQQD[%d]:", i);
924 ugeth_info("Base address: 0x%08x",
925 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
926 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
927 sizeof(struct ucc_geth_send_queue_qd));
928 }
929 }
930 if (ugeth->p_scheduler) {
931 ugeth_info("Scheduler:");
932 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
933 mem_disp((u8 *) ugeth->p_scheduler,
934 sizeof(*ugeth->p_scheduler));
935 }
936 if (ugeth->p_tx_fw_statistics_pram) {
937 ugeth_info("TX FW statistics pram:");
938 ugeth_info("Base address: 0x%08x",
939 (u32) ugeth->p_tx_fw_statistics_pram);
940 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
941 sizeof(*ugeth->p_tx_fw_statistics_pram));
942 }
943 if (ugeth->p_rx_fw_statistics_pram) {
944 ugeth_info("RX FW statistics pram:");
945 ugeth_info("Base address: 0x%08x",
946 (u32) ugeth->p_rx_fw_statistics_pram);
947 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
948 sizeof(*ugeth->p_rx_fw_statistics_pram));
949 }
950 if (ugeth->p_rx_irq_coalescing_tbl) {
951 ugeth_info("RX IRQ coalescing tables:");
952 ugeth_info("Base address: 0x%08x",
953 (u32) ugeth->p_rx_irq_coalescing_tbl);
954 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
955 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
956 ugeth_info("Base address: 0x%08x",
957 (u32) & ugeth->p_rx_irq_coalescing_tbl->
958 coalescingentry[i]);
959 ugeth_info
960 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
961 (u32) & ugeth->p_rx_irq_coalescing_tbl->
962 coalescingentry[i].interruptcoalescingmaxvalue,
963 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
964 coalescingentry[i].
965 interruptcoalescingmaxvalue));
966 ugeth_info
967 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
968 (u32) & ugeth->p_rx_irq_coalescing_tbl->
969 coalescingentry[i].interruptcoalescingcounter,
970 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
971 coalescingentry[i].
972 interruptcoalescingcounter));
973 }
974 }
975 if (ugeth->p_rx_bd_qs_tbl) {
976 ugeth_info("RX BD QS tables:");
977 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
978 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
979 ugeth_info("RX BD QS table[%d]:", i);
980 ugeth_info("Base address: 0x%08x",
981 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
982 ugeth_info
983 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
984 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
985 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
986 ugeth_info
987 ("bdptr : addr - 0x%08x, val - 0x%08x",
988 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
989 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
990 ugeth_info
991 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
992 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
993 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
994 externalbdbaseptr));
995 ugeth_info
996 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
997 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
998 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
999 ugeth_info("ucode RX Prefetched BDs:");
1000 ugeth_info("Base address: 0x%08x",
1001 (u32)
1002 qe_muram_addr(in_be32
1003 (&ugeth->p_rx_bd_qs_tbl[i].
1004 bdbaseptr)));
1005 mem_disp((u8 *)
1006 qe_muram_addr(in_be32
1007 (&ugeth->p_rx_bd_qs_tbl[i].
1008 bdbaseptr)),
1009 sizeof(struct ucc_geth_rx_prefetched_bds));
1010 }
1011 }
1012 if (ugeth->p_init_enet_param_shadow) {
1013 int size;
1014 ugeth_info("Init enet param shadow:");
1015 ugeth_info("Base address: 0x%08x",
1016 (u32) ugeth->p_init_enet_param_shadow);
1017 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1018 sizeof(*ugeth->p_init_enet_param_shadow));
1019
1020 size = sizeof(struct ucc_geth_thread_rx_pram);
1021 if (ugeth->ug_info->rxExtendedFiltering) {
1022 size +=
1023 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1024 if (ugeth->ug_info->largestexternallookupkeysize ==
1025 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1026 size +=
1027 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1028 if (ugeth->ug_info->largestexternallookupkeysize ==
1029 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1030 size +=
1031 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1032 }
1033
1034 dump_init_enet_entries(ugeth,
1035 &(ugeth->p_init_enet_param_shadow->
1036 txthread[0]),
1037 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1038 sizeof(struct ucc_geth_thread_tx_pram),
1039 ugeth->ug_info->riscTx, 0);
1040 dump_init_enet_entries(ugeth,
1041 &(ugeth->p_init_enet_param_shadow->
1042 rxthread[0]),
1043 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1044 ugeth->ug_info->riscRx, 1);
1045 }
1046 }
1047 #endif /* DEBUG */
1048
1049 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1050 u32 __iomem *maccfg1_register,
1051 u32 __iomem *maccfg2_register)
1052 {
1053 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1054 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1055 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1056 }
1057
1058 static int init_half_duplex_params(int alt_beb,
1059 int back_pressure_no_backoff,
1060 int no_backoff,
1061 int excess_defer,
1062 u8 alt_beb_truncation,
1063 u8 max_retransmissions,
1064 u8 collision_window,
1065 u32 __iomem *hafdup_register)
1066 {
1067 u32 value = 0;
1068
1069 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1070 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1071 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1072 return -EINVAL;
1073
1074 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1075
1076 if (alt_beb)
1077 value |= HALFDUP_ALT_BEB;
1078 if (back_pressure_no_backoff)
1079 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1080 if (no_backoff)
1081 value |= HALFDUP_NO_BACKOFF;
1082 if (excess_defer)
1083 value |= HALFDUP_EXCESSIVE_DEFER;
1084
1085 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1086
1087 value |= collision_window;
1088
1089 out_be32(hafdup_register, value);
1090 return 0;
1091 }
1092
1093 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1094 u8 non_btb_ipg,
1095 u8 min_ifg,
1096 u8 btb_ipg,
1097 u32 __iomem *ipgifg_register)
1098 {
1099 u32 value = 0;
1100
1101 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1102 IPG part 2 */
1103 if (non_btb_cs_ipg > non_btb_ipg)
1104 return -EINVAL;
1105
1106 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1107 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1108 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1109 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1110 return -EINVAL;
1111
1112 value |=
1113 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1114 IPGIFG_NBTB_CS_IPG_MASK);
1115 value |=
1116 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1117 IPGIFG_NBTB_IPG_MASK);
1118 value |=
1119 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1120 IPGIFG_MIN_IFG_MASK);
1121 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1122
1123 out_be32(ipgifg_register, value);
1124 return 0;
1125 }
1126
1127 int init_flow_control_params(u32 automatic_flow_control_mode,
1128 int rx_flow_control_enable,
1129 int tx_flow_control_enable,
1130 u16 pause_period,
1131 u16 extension_field,
1132 u32 __iomem *upsmr_register,
1133 u32 __iomem *uempr_register,
1134 u32 __iomem *maccfg1_register)
1135 {
1136 u32 value = 0;
1137
1138 /* Set UEMPR register */
1139 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1140 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1141 out_be32(uempr_register, value);
1142
1143 /* Set UPSMR register */
1144 setbits32(upsmr_register, automatic_flow_control_mode);
1145
1146 value = in_be32(maccfg1_register);
1147 if (rx_flow_control_enable)
1148 value |= MACCFG1_FLOW_RX;
1149 if (tx_flow_control_enable)
1150 value |= MACCFG1_FLOW_TX;
1151 out_be32(maccfg1_register, value);
1152
1153 return 0;
1154 }
1155
1156 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1157 int auto_zero_hardware_statistics,
1158 u32 __iomem *upsmr_register,
1159 u16 __iomem *uescr_register)
1160 {
1161 u16 uescr_value = 0;
1162
1163 /* Enable hardware statistics gathering if requested */
1164 if (enable_hardware_statistics)
1165 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1166
1167 /* Clear hardware statistics counters */
1168 uescr_value = in_be16(uescr_register);
1169 uescr_value |= UESCR_CLRCNT;
1170 /* Automatically zero hardware statistics counters on read,
1171 if requested */
1172 if (auto_zero_hardware_statistics)
1173 uescr_value |= UESCR_AUTOZ;
1174 out_be16(uescr_register, uescr_value);
1175
1176 return 0;
1177 }
1178
1179 static int init_firmware_statistics_gathering_mode(int
1180 enable_tx_firmware_statistics,
1181 int enable_rx_firmware_statistics,
1182 u32 __iomem *tx_rmon_base_ptr,
1183 u32 tx_firmware_statistics_structure_address,
1184 u32 __iomem *rx_rmon_base_ptr,
1185 u32 rx_firmware_statistics_structure_address,
1186 u16 __iomem *temoder_register,
1187 u32 __iomem *remoder_register)
1188 {
1189 /* Note: this function does not check if */
1190 /* the parameters it receives are NULL */
1191
1192 if (enable_tx_firmware_statistics) {
1193 out_be32(tx_rmon_base_ptr,
1194 tx_firmware_statistics_structure_address);
1195 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1196 }
1197
1198 if (enable_rx_firmware_statistics) {
1199 out_be32(rx_rmon_base_ptr,
1200 rx_firmware_statistics_structure_address);
1201 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1202 }
1203
1204 return 0;
1205 }
1206
1207 static int init_mac_station_addr_regs(u8 address_byte_0,
1208 u8 address_byte_1,
1209 u8 address_byte_2,
1210 u8 address_byte_3,
1211 u8 address_byte_4,
1212 u8 address_byte_5,
1213 u32 __iomem *macstnaddr1_register,
1214 u32 __iomem *macstnaddr2_register)
1215 {
1216 u32 value = 0;
1217
1218 /* Example: for a station address of 0x12345678ABCD, */
1219 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1220
1221 /* MACSTNADDR1 Register: */
1222
1223 /* 0 7 8 15 */
1224 /* station address byte 5 station address byte 4 */
1225 /* 16 23 24 31 */
1226 /* station address byte 3 station address byte 2 */
1227 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1228 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1229 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1230 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1231
1232 out_be32(macstnaddr1_register, value);
1233
1234 /* MACSTNADDR2 Register: */
1235
1236 /* 0 7 8 15 */
1237 /* station address byte 1 station address byte 0 */
1238 /* 16 23 24 31 */
1239 /* reserved reserved */
1240 value = 0;
1241 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1242 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1243
1244 out_be32(macstnaddr2_register, value);
1245
1246 return 0;
1247 }
1248
1249 static int init_check_frame_length_mode(int length_check,
1250 u32 __iomem *maccfg2_register)
1251 {
1252 u32 value = 0;
1253
1254 value = in_be32(maccfg2_register);
1255
1256 if (length_check)
1257 value |= MACCFG2_LC;
1258 else
1259 value &= ~MACCFG2_LC;
1260
1261 out_be32(maccfg2_register, value);
1262 return 0;
1263 }
1264
1265 static int init_preamble_length(u8 preamble_length,
1266 u32 __iomem *maccfg2_register)
1267 {
1268 if ((preamble_length < 3) || (preamble_length > 7))
1269 return -EINVAL;
1270
1271 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1272 preamble_length << MACCFG2_PREL_SHIFT);
1273
1274 return 0;
1275 }
1276
1277 static int init_rx_parameters(int reject_broadcast,
1278 int receive_short_frames,
1279 int promiscuous, u32 __iomem *upsmr_register)
1280 {
1281 u32 value = 0;
1282
1283 value = in_be32(upsmr_register);
1284
1285 if (reject_broadcast)
1286 value |= UCC_GETH_UPSMR_BRO;
1287 else
1288 value &= ~UCC_GETH_UPSMR_BRO;
1289
1290 if (receive_short_frames)
1291 value |= UCC_GETH_UPSMR_RSH;
1292 else
1293 value &= ~UCC_GETH_UPSMR_RSH;
1294
1295 if (promiscuous)
1296 value |= UCC_GETH_UPSMR_PRO;
1297 else
1298 value &= ~UCC_GETH_UPSMR_PRO;
1299
1300 out_be32(upsmr_register, value);
1301
1302 return 0;
1303 }
1304
1305 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1306 u16 __iomem *mrblr_register)
1307 {
1308 /* max_rx_buf_len value must be a multiple of 128 */
1309 if ((max_rx_buf_len == 0)
1310 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1311 return -EINVAL;
1312
1313 out_be16(mrblr_register, max_rx_buf_len);
1314 return 0;
1315 }
1316
1317 static int init_min_frame_len(u16 min_frame_length,
1318 u16 __iomem *minflr_register,
1319 u16 __iomem *mrblr_register)
1320 {
1321 u16 mrblr_value = 0;
1322
1323 mrblr_value = in_be16(mrblr_register);
1324 if (min_frame_length >= (mrblr_value - 4))
1325 return -EINVAL;
1326
1327 out_be16(minflr_register, min_frame_length);
1328 return 0;
1329 }
1330
1331 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1332 {
1333 struct ucc_geth_info *ug_info;
1334 struct ucc_geth __iomem *ug_regs;
1335 struct ucc_fast __iomem *uf_regs;
1336 int ret_val;
1337 u32 upsmr, maccfg2, tbiBaseAddress;
1338 u16 value;
1339
1340 ugeth_vdbg("%s: IN", __func__);
1341
1342 ug_info = ugeth->ug_info;
1343 ug_regs = ugeth->ug_regs;
1344 uf_regs = ugeth->uccf->uf_regs;
1345
1346 /* Set MACCFG2 */
1347 maccfg2 = in_be32(&ug_regs->maccfg2);
1348 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1349 if ((ugeth->max_speed == SPEED_10) ||
1350 (ugeth->max_speed == SPEED_100))
1351 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1352 else if (ugeth->max_speed == SPEED_1000)
1353 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1354 maccfg2 |= ug_info->padAndCrc;
1355 out_be32(&ug_regs->maccfg2, maccfg2);
1356
1357 /* Set UPSMR */
1358 upsmr = in_be32(&uf_regs->upsmr);
1359 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1360 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1361 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1362 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1363 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1365 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1367 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1368 upsmr |= UCC_GETH_UPSMR_RPM;
1369 switch (ugeth->max_speed) {
1370 case SPEED_10:
1371 upsmr |= UCC_GETH_UPSMR_R10M;
1372 /* FALLTHROUGH */
1373 case SPEED_100:
1374 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1375 upsmr |= UCC_GETH_UPSMR_RMM;
1376 }
1377 }
1378 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1379 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1380 upsmr |= UCC_GETH_UPSMR_TBIM;
1381 }
1382 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1383 upsmr |= UCC_GETH_UPSMR_SGMM;
1384
1385 out_be32(&uf_regs->upsmr, upsmr);
1386
1387 /* Disable autonegotiation in tbi mode, because by default it
1388 comes up in autonegotiation mode. */
1389 /* Note that this depends on proper setting in utbipar register. */
1390 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1391 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1392 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1393 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1394 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1395 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1396 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1397 value &= ~0x1000; /* Turn off autonegotiation */
1398 ugeth->phydev->bus->write(ugeth->phydev->bus,
1399 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1400 }
1401
1402 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1403
1404 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1405 if (ret_val != 0) {
1406 if (netif_msg_probe(ugeth))
1407 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1408 __func__);
1409 return ret_val;
1410 }
1411
1412 return 0;
1413 }
1414
1415 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1416 {
1417 struct ucc_fast_private *uccf;
1418 u32 cecr_subblock;
1419 u32 temp;
1420 int i = 10;
1421
1422 uccf = ugeth->uccf;
1423
1424 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1425 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1426 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1427
1428 /* Issue host command */
1429 cecr_subblock =
1430 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1431 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1432 QE_CR_PROTOCOL_ETHERNET, 0);
1433
1434 /* Wait for command to complete */
1435 do {
1436 msleep(10);
1437 temp = in_be32(uccf->p_ucce);
1438 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1439
1440 uccf->stopped_tx = 1;
1441
1442 return 0;
1443 }
1444
1445 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1446 {
1447 struct ucc_fast_private *uccf;
1448 u32 cecr_subblock;
1449 u8 temp;
1450 int i = 10;
1451
1452 uccf = ugeth->uccf;
1453
1454 /* Clear acknowledge bit */
1455 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1456 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1457 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1458
1459 /* Keep issuing command and checking acknowledge bit until
1460 it is asserted, according to spec */
1461 do {
1462 /* Issue host command */
1463 cecr_subblock =
1464 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1465 ucc_num);
1466 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1467 QE_CR_PROTOCOL_ETHERNET, 0);
1468 msleep(10);
1469 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1470 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1471
1472 uccf->stopped_rx = 1;
1473
1474 return 0;
1475 }
1476
1477 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1478 {
1479 struct ucc_fast_private *uccf;
1480 u32 cecr_subblock;
1481
1482 uccf = ugeth->uccf;
1483
1484 cecr_subblock =
1485 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1486 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1487 uccf->stopped_tx = 0;
1488
1489 return 0;
1490 }
1491
1492 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1493 {
1494 struct ucc_fast_private *uccf;
1495 u32 cecr_subblock;
1496
1497 uccf = ugeth->uccf;
1498
1499 cecr_subblock =
1500 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1501 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1502 0);
1503 uccf->stopped_rx = 0;
1504
1505 return 0;
1506 }
1507
1508 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1509 {
1510 struct ucc_fast_private *uccf;
1511 int enabled_tx, enabled_rx;
1512
1513 uccf = ugeth->uccf;
1514
1515 /* check if the UCC number is in range. */
1516 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1517 if (netif_msg_probe(ugeth))
1518 ugeth_err("%s: ucc_num out of range.", __func__);
1519 return -EINVAL;
1520 }
1521
1522 enabled_tx = uccf->enabled_tx;
1523 enabled_rx = uccf->enabled_rx;
1524
1525 /* Get Tx and Rx going again, in case this channel was actively
1526 disabled. */
1527 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1528 ugeth_restart_tx(ugeth);
1529 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1530 ugeth_restart_rx(ugeth);
1531
1532 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1533
1534 return 0;
1535
1536 }
1537
1538 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1539 {
1540 struct ucc_fast_private *uccf;
1541
1542 uccf = ugeth->uccf;
1543
1544 /* check if the UCC number is in range. */
1545 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1546 if (netif_msg_probe(ugeth))
1547 ugeth_err("%s: ucc_num out of range.", __func__);
1548 return -EINVAL;
1549 }
1550
1551 /* Stop any transmissions */
1552 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1553 ugeth_graceful_stop_tx(ugeth);
1554
1555 /* Stop any receptions */
1556 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1557 ugeth_graceful_stop_rx(ugeth);
1558
1559 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1560
1561 return 0;
1562 }
1563
1564 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1565 {
1566 /* Prevent any further xmits, plus detach the device. */
1567 netif_device_detach(ugeth->ndev);
1568
1569 /* Wait for any current xmits to finish. */
1570 netif_tx_disable(ugeth->ndev);
1571
1572 /* Disable the interrupt to avoid NAPI rescheduling. */
1573 disable_irq(ugeth->ug_info->uf_info.irq);
1574
1575 /* Stop NAPI, and possibly wait for its completion. */
1576 napi_disable(&ugeth->napi);
1577 }
1578
1579 static void ugeth_activate(struct ucc_geth_private *ugeth)
1580 {
1581 napi_enable(&ugeth->napi);
1582 enable_irq(ugeth->ug_info->uf_info.irq);
1583 netif_device_attach(ugeth->ndev);
1584 }
1585
1586 /* Called every time the controller might need to be made
1587 * aware of new link state. The PHY code conveys this
1588 * information through variables in the ugeth structure, and this
1589 * function converts those variables into the appropriate
1590 * register values, and can bring down the device if needed.
1591 */
1592
1593 static void adjust_link(struct net_device *dev)
1594 {
1595 struct ucc_geth_private *ugeth = netdev_priv(dev);
1596 struct ucc_geth __iomem *ug_regs;
1597 struct ucc_fast __iomem *uf_regs;
1598 struct phy_device *phydev = ugeth->phydev;
1599 int new_state = 0;
1600
1601 ug_regs = ugeth->ug_regs;
1602 uf_regs = ugeth->uccf->uf_regs;
1603
1604 if (phydev->link) {
1605 u32 tempval = in_be32(&ug_regs->maccfg2);
1606 u32 upsmr = in_be32(&uf_regs->upsmr);
1607 /* Now we make sure that we can be in full duplex mode.
1608 * If not, we operate in half-duplex mode. */
1609 if (phydev->duplex != ugeth->oldduplex) {
1610 new_state = 1;
1611 if (!(phydev->duplex))
1612 tempval &= ~(MACCFG2_FDX);
1613 else
1614 tempval |= MACCFG2_FDX;
1615 ugeth->oldduplex = phydev->duplex;
1616 }
1617
1618 if (phydev->speed != ugeth->oldspeed) {
1619 new_state = 1;
1620 switch (phydev->speed) {
1621 case SPEED_1000:
1622 tempval = ((tempval &
1623 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1624 MACCFG2_INTERFACE_MODE_BYTE);
1625 break;
1626 case SPEED_100:
1627 case SPEED_10:
1628 tempval = ((tempval &
1629 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1630 MACCFG2_INTERFACE_MODE_NIBBLE);
1631 /* if reduced mode, re-set UPSMR.R10M */
1632 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1633 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1634 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1635 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1636 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1637 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1638 if (phydev->speed == SPEED_10)
1639 upsmr |= UCC_GETH_UPSMR_R10M;
1640 else
1641 upsmr &= ~UCC_GETH_UPSMR_R10M;
1642 }
1643 break;
1644 default:
1645 if (netif_msg_link(ugeth))
1646 ugeth_warn(
1647 "%s: Ack! Speed (%d) is not 10/100/1000!",
1648 dev->name, phydev->speed);
1649 break;
1650 }
1651 ugeth->oldspeed = phydev->speed;
1652 }
1653
1654 /*
1655 * To change the MAC configuration we need to disable the
1656 * controller. To do so, we have to either grab ugeth->lock,
1657 * which is a bad idea since 'graceful stop' commands might
1658 * take quite a while, or we can quiesce driver's activity.
1659 */
1660 ugeth_quiesce(ugeth);
1661 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1662
1663 out_be32(&ug_regs->maccfg2, tempval);
1664 out_be32(&uf_regs->upsmr, upsmr);
1665
1666 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1667 ugeth_activate(ugeth);
1668
1669 if (!ugeth->oldlink) {
1670 new_state = 1;
1671 ugeth->oldlink = 1;
1672 }
1673 } else if (ugeth->oldlink) {
1674 new_state = 1;
1675 ugeth->oldlink = 0;
1676 ugeth->oldspeed = 0;
1677 ugeth->oldduplex = -1;
1678 }
1679
1680 if (new_state && netif_msg_link(ugeth))
1681 phy_print_status(phydev);
1682 }
1683
1684 /* Initialize TBI PHY interface for communicating with the
1685 * SERDES lynx PHY on the chip. We communicate with this PHY
1686 * through the MDIO bus on each controller, treating it as a
1687 * "normal" PHY at the address found in the UTBIPA register. We assume
1688 * that the UTBIPA register is valid. Either the MDIO bus code will set
1689 * it to a value that doesn't conflict with other PHYs on the bus, or the
1690 * value doesn't matter, as there are no other PHYs on the bus.
1691 */
1692 static void uec_configure_serdes(struct net_device *dev)
1693 {
1694 struct ucc_geth_private *ugeth = netdev_priv(dev);
1695 struct ucc_geth_info *ug_info = ugeth->ug_info;
1696 struct phy_device *tbiphy;
1697
1698 if (!ug_info->tbi_node) {
1699 dev_warn(&dev->dev, "SGMII mode requires that the device "
1700 "tree specify a tbi-handle\n");
1701 return;
1702 }
1703
1704 tbiphy = of_phy_find_device(ug_info->tbi_node);
1705 if (!tbiphy) {
1706 dev_err(&dev->dev, "error: Could not get TBI device\n");
1707 return;
1708 }
1709
1710 /*
1711 * If the link is already up, we must already be ok, and don't need to
1712 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1713 * everything for us? Resetting it takes the link down and requires
1714 * several seconds for it to come back.
1715 */
1716 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1717 return;
1718
1719 /* Single clk mode, mii mode off(for serdes communication) */
1720 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1721
1722 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1723
1724 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1725 }
1726
1727 /* Configure the PHY for dev.
1728 * returns 0 if success. -1 if failure
1729 */
1730 static int init_phy(struct net_device *dev)
1731 {
1732 struct ucc_geth_private *priv = netdev_priv(dev);
1733 struct ucc_geth_info *ug_info = priv->ug_info;
1734 struct phy_device *phydev;
1735
1736 priv->oldlink = 0;
1737 priv->oldspeed = 0;
1738 priv->oldduplex = -1;
1739
1740 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1741 priv->phy_interface);
1742 if (!phydev)
1743 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1744 priv->phy_interface);
1745 if (!phydev) {
1746 dev_err(&dev->dev, "Could not attach to PHY\n");
1747 return -ENODEV;
1748 }
1749
1750 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1751 uec_configure_serdes(dev);
1752
1753 phydev->supported &= (ADVERTISED_10baseT_Half |
1754 ADVERTISED_10baseT_Full |
1755 ADVERTISED_100baseT_Half |
1756 ADVERTISED_100baseT_Full);
1757
1758 if (priv->max_speed == SPEED_1000)
1759 phydev->supported |= ADVERTISED_1000baseT_Full;
1760
1761 phydev->advertising = phydev->supported;
1762
1763 priv->phydev = phydev;
1764
1765 return 0;
1766 }
1767
1768 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1769 {
1770 #ifdef DEBUG
1771 ucc_fast_dump_regs(ugeth->uccf);
1772 dump_regs(ugeth);
1773 dump_bds(ugeth);
1774 #endif
1775 }
1776
1777 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1778 ugeth,
1779 enum enet_addr_type
1780 enet_addr_type)
1781 {
1782 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1783 struct ucc_fast_private *uccf;
1784 enum comm_dir comm_dir;
1785 struct list_head *p_lh;
1786 u16 i, num;
1787 u32 __iomem *addr_h;
1788 u32 __iomem *addr_l;
1789 u8 *p_counter;
1790
1791 uccf = ugeth->uccf;
1792
1793 p_82xx_addr_filt =
1794 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1795 ugeth->p_rx_glbl_pram->addressfiltering;
1796
1797 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1798 addr_h = &(p_82xx_addr_filt->gaddr_h);
1799 addr_l = &(p_82xx_addr_filt->gaddr_l);
1800 p_lh = &ugeth->group_hash_q;
1801 p_counter = &(ugeth->numGroupAddrInHash);
1802 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1803 addr_h = &(p_82xx_addr_filt->iaddr_h);
1804 addr_l = &(p_82xx_addr_filt->iaddr_l);
1805 p_lh = &ugeth->ind_hash_q;
1806 p_counter = &(ugeth->numIndAddrInHash);
1807 } else
1808 return -EINVAL;
1809
1810 comm_dir = 0;
1811 if (uccf->enabled_tx)
1812 comm_dir |= COMM_DIR_TX;
1813 if (uccf->enabled_rx)
1814 comm_dir |= COMM_DIR_RX;
1815 if (comm_dir)
1816 ugeth_disable(ugeth, comm_dir);
1817
1818 /* Clear the hash table. */
1819 out_be32(addr_h, 0x00000000);
1820 out_be32(addr_l, 0x00000000);
1821
1822 if (!p_lh)
1823 return 0;
1824
1825 num = *p_counter;
1826
1827 /* Delete all remaining CQ elements */
1828 for (i = 0; i < num; i++)
1829 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1830
1831 *p_counter = 0;
1832
1833 if (comm_dir)
1834 ugeth_enable(ugeth, comm_dir);
1835
1836 return 0;
1837 }
1838
1839 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1840 u8 paddr_num)
1841 {
1842 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1843 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1844 }
1845
1846 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1847 {
1848 u16 i, j;
1849 u8 __iomem *bd;
1850
1851 if (!ugeth)
1852 return;
1853
1854 if (ugeth->uccf) {
1855 ucc_fast_free(ugeth->uccf);
1856 ugeth->uccf = NULL;
1857 }
1858
1859 if (ugeth->p_thread_data_tx) {
1860 qe_muram_free(ugeth->thread_dat_tx_offset);
1861 ugeth->p_thread_data_tx = NULL;
1862 }
1863 if (ugeth->p_thread_data_rx) {
1864 qe_muram_free(ugeth->thread_dat_rx_offset);
1865 ugeth->p_thread_data_rx = NULL;
1866 }
1867 if (ugeth->p_exf_glbl_param) {
1868 qe_muram_free(ugeth->exf_glbl_param_offset);
1869 ugeth->p_exf_glbl_param = NULL;
1870 }
1871 if (ugeth->p_rx_glbl_pram) {
1872 qe_muram_free(ugeth->rx_glbl_pram_offset);
1873 ugeth->p_rx_glbl_pram = NULL;
1874 }
1875 if (ugeth->p_tx_glbl_pram) {
1876 qe_muram_free(ugeth->tx_glbl_pram_offset);
1877 ugeth->p_tx_glbl_pram = NULL;
1878 }
1879 if (ugeth->p_send_q_mem_reg) {
1880 qe_muram_free(ugeth->send_q_mem_reg_offset);
1881 ugeth->p_send_q_mem_reg = NULL;
1882 }
1883 if (ugeth->p_scheduler) {
1884 qe_muram_free(ugeth->scheduler_offset);
1885 ugeth->p_scheduler = NULL;
1886 }
1887 if (ugeth->p_tx_fw_statistics_pram) {
1888 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1889 ugeth->p_tx_fw_statistics_pram = NULL;
1890 }
1891 if (ugeth->p_rx_fw_statistics_pram) {
1892 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1893 ugeth->p_rx_fw_statistics_pram = NULL;
1894 }
1895 if (ugeth->p_rx_irq_coalescing_tbl) {
1896 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1897 ugeth->p_rx_irq_coalescing_tbl = NULL;
1898 }
1899 if (ugeth->p_rx_bd_qs_tbl) {
1900 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1901 ugeth->p_rx_bd_qs_tbl = NULL;
1902 }
1903 if (ugeth->p_init_enet_param_shadow) {
1904 return_init_enet_entries(ugeth,
1905 &(ugeth->p_init_enet_param_shadow->
1906 rxthread[0]),
1907 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1908 ugeth->ug_info->riscRx, 1);
1909 return_init_enet_entries(ugeth,
1910 &(ugeth->p_init_enet_param_shadow->
1911 txthread[0]),
1912 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1913 ugeth->ug_info->riscTx, 0);
1914 kfree(ugeth->p_init_enet_param_shadow);
1915 ugeth->p_init_enet_param_shadow = NULL;
1916 }
1917 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1918 bd = ugeth->p_tx_bd_ring[i];
1919 if (!bd)
1920 continue;
1921 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1922 if (ugeth->tx_skbuff[i][j]) {
1923 dma_unmap_single(ugeth->dev,
1924 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1925 (in_be32((u32 __iomem *)bd) &
1926 BD_LENGTH_MASK),
1927 DMA_TO_DEVICE);
1928 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1929 ugeth->tx_skbuff[i][j] = NULL;
1930 }
1931 }
1932
1933 kfree(ugeth->tx_skbuff[i]);
1934
1935 if (ugeth->p_tx_bd_ring[i]) {
1936 if (ugeth->ug_info->uf_info.bd_mem_part ==
1937 MEM_PART_SYSTEM)
1938 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1939 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1940 MEM_PART_MURAM)
1941 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1942 ugeth->p_tx_bd_ring[i] = NULL;
1943 }
1944 }
1945 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1946 if (ugeth->p_rx_bd_ring[i]) {
1947 /* Return existing data buffers in ring */
1948 bd = ugeth->p_rx_bd_ring[i];
1949 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1950 if (ugeth->rx_skbuff[i][j]) {
1951 dma_unmap_single(ugeth->dev,
1952 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1953 ugeth->ug_info->
1954 uf_info.max_rx_buf_length +
1955 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1956 DMA_FROM_DEVICE);
1957 dev_kfree_skb_any(
1958 ugeth->rx_skbuff[i][j]);
1959 ugeth->rx_skbuff[i][j] = NULL;
1960 }
1961 bd += sizeof(struct qe_bd);
1962 }
1963
1964 kfree(ugeth->rx_skbuff[i]);
1965
1966 if (ugeth->ug_info->uf_info.bd_mem_part ==
1967 MEM_PART_SYSTEM)
1968 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1969 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1970 MEM_PART_MURAM)
1971 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1972 ugeth->p_rx_bd_ring[i] = NULL;
1973 }
1974 }
1975 while (!list_empty(&ugeth->group_hash_q))
1976 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1977 (dequeue(&ugeth->group_hash_q)));
1978 while (!list_empty(&ugeth->ind_hash_q))
1979 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1980 (dequeue(&ugeth->ind_hash_q)));
1981 if (ugeth->ug_regs) {
1982 iounmap(ugeth->ug_regs);
1983 ugeth->ug_regs = NULL;
1984 }
1985
1986 skb_queue_purge(&ugeth->rx_recycle);
1987 }
1988
1989 static void ucc_geth_set_multi(struct net_device *dev)
1990 {
1991 struct ucc_geth_private *ugeth;
1992 struct dev_mc_list *dmi;
1993 struct ucc_fast __iomem *uf_regs;
1994 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1995 int i;
1996
1997 ugeth = netdev_priv(dev);
1998
1999 uf_regs = ugeth->uccf->uf_regs;
2000
2001 if (dev->flags & IFF_PROMISC) {
2002 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2003 } else {
2004 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2005
2006 p_82xx_addr_filt =
2007 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2008 p_rx_glbl_pram->addressfiltering;
2009
2010 if (dev->flags & IFF_ALLMULTI) {
2011 /* Catch all multicast addresses, so set the
2012 * filter to all 1's.
2013 */
2014 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2015 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2016 } else {
2017 /* Clear filter and add the addresses in the list.
2018 */
2019 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2020 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2021
2022 dmi = dev->mc_list;
2023
2024 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2025
2026 /* Only support group multicast for now.
2027 */
2028 if (!(dmi->dmi_addr[0] & 1))
2029 continue;
2030
2031 /* Ask CPM to run CRC and set bit in
2032 * filter mask.
2033 */
2034 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2035 }
2036 }
2037 }
2038 }
2039
2040 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2041 {
2042 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2043 struct phy_device *phydev = ugeth->phydev;
2044
2045 ugeth_vdbg("%s: IN", __func__);
2046
2047 /* Disable the controller */
2048 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2049
2050 /* Tell the kernel the link is down */
2051 phy_stop(phydev);
2052
2053 /* Mask all interrupts */
2054 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2055
2056 /* Clear all interrupts */
2057 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2058
2059 /* Disable Rx and Tx */
2060 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2061
2062 phy_disconnect(ugeth->phydev);
2063 ugeth->phydev = NULL;
2064
2065 ucc_geth_memclean(ugeth);
2066 }
2067
2068 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2069 {
2070 struct ucc_geth_info *ug_info;
2071 struct ucc_fast_info *uf_info;
2072 int i;
2073
2074 ug_info = ugeth->ug_info;
2075 uf_info = &ug_info->uf_info;
2076
2077 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2078 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2079 if (netif_msg_probe(ugeth))
2080 ugeth_err("%s: Bad memory partition value.",
2081 __func__);
2082 return -EINVAL;
2083 }
2084
2085 /* Rx BD lengths */
2086 for (i = 0; i < ug_info->numQueuesRx; i++) {
2087 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2088 (ug_info->bdRingLenRx[i] %
2089 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2090 if (netif_msg_probe(ugeth))
2091 ugeth_err
2092 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2093 __func__);
2094 return -EINVAL;
2095 }
2096 }
2097
2098 /* Tx BD lengths */
2099 for (i = 0; i < ug_info->numQueuesTx; i++) {
2100 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2101 if (netif_msg_probe(ugeth))
2102 ugeth_err
2103 ("%s: Tx BD ring length must be no smaller than 2.",
2104 __func__);
2105 return -EINVAL;
2106 }
2107 }
2108
2109 /* mrblr */
2110 if ((uf_info->max_rx_buf_length == 0) ||
2111 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2112 if (netif_msg_probe(ugeth))
2113 ugeth_err
2114 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2115 __func__);
2116 return -EINVAL;
2117 }
2118
2119 /* num Tx queues */
2120 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2121 if (netif_msg_probe(ugeth))
2122 ugeth_err("%s: number of tx queues too large.", __func__);
2123 return -EINVAL;
2124 }
2125
2126 /* num Rx queues */
2127 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2128 if (netif_msg_probe(ugeth))
2129 ugeth_err("%s: number of rx queues too large.", __func__);
2130 return -EINVAL;
2131 }
2132
2133 /* l2qt */
2134 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2135 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2136 if (netif_msg_probe(ugeth))
2137 ugeth_err
2138 ("%s: VLAN priority table entry must not be"
2139 " larger than number of Rx queues.",
2140 __func__);
2141 return -EINVAL;
2142 }
2143 }
2144
2145 /* l3qt */
2146 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2147 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2148 if (netif_msg_probe(ugeth))
2149 ugeth_err
2150 ("%s: IP priority table entry must not be"
2151 " larger than number of Rx queues.",
2152 __func__);
2153 return -EINVAL;
2154 }
2155 }
2156
2157 if (ug_info->cam && !ug_info->ecamptr) {
2158 if (netif_msg_probe(ugeth))
2159 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2160 __func__);
2161 return -EINVAL;
2162 }
2163
2164 if ((ug_info->numStationAddresses !=
2165 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2166 && ug_info->rxExtendedFiltering) {
2167 if (netif_msg_probe(ugeth))
2168 ugeth_err("%s: Number of station addresses greater than 1 "
2169 "not allowed in extended parsing mode.",
2170 __func__);
2171 return -EINVAL;
2172 }
2173
2174 /* Generate uccm_mask for receive */
2175 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2176 for (i = 0; i < ug_info->numQueuesRx; i++)
2177 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2178
2179 for (i = 0; i < ug_info->numQueuesTx; i++)
2180 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2181 /* Initialize the general fast UCC block. */
2182 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2183 if (netif_msg_probe(ugeth))
2184 ugeth_err("%s: Failed to init uccf.", __func__);
2185 return -ENOMEM;
2186 }
2187
2188 /* read the number of risc engines, update the riscTx and riscRx
2189 * if there are 4 riscs in QE
2190 */
2191 if (qe_get_num_of_risc() == 4) {
2192 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2193 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2194 }
2195
2196 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2197 if (!ugeth->ug_regs) {
2198 if (netif_msg_probe(ugeth))
2199 ugeth_err("%s: Failed to ioremap regs.", __func__);
2200 return -ENOMEM;
2201 }
2202
2203 skb_queue_head_init(&ugeth->rx_recycle);
2204
2205 return 0;
2206 }
2207
2208 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2209 {
2210 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2211 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2212 struct ucc_fast_private *uccf;
2213 struct ucc_geth_info *ug_info;
2214 struct ucc_fast_info *uf_info;
2215 struct ucc_fast __iomem *uf_regs;
2216 struct ucc_geth __iomem *ug_regs;
2217 int ret_val = -EINVAL;
2218 u32 remoder = UCC_GETH_REMODER_INIT;
2219 u32 init_enet_pram_offset, cecr_subblock, command;
2220 u32 ifstat, i, j, size, l2qt, l3qt, length;
2221 u16 temoder = UCC_GETH_TEMODER_INIT;
2222 u16 test;
2223 u8 function_code = 0;
2224 u8 __iomem *bd;
2225 u8 __iomem *endOfRing;
2226 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2227
2228 ugeth_vdbg("%s: IN", __func__);
2229 uccf = ugeth->uccf;
2230 ug_info = ugeth->ug_info;
2231 uf_info = &ug_info->uf_info;
2232 uf_regs = uccf->uf_regs;
2233 ug_regs = ugeth->ug_regs;
2234
2235 switch (ug_info->numThreadsRx) {
2236 case UCC_GETH_NUM_OF_THREADS_1:
2237 numThreadsRxNumerical = 1;
2238 break;
2239 case UCC_GETH_NUM_OF_THREADS_2:
2240 numThreadsRxNumerical = 2;
2241 break;
2242 case UCC_GETH_NUM_OF_THREADS_4:
2243 numThreadsRxNumerical = 4;
2244 break;
2245 case UCC_GETH_NUM_OF_THREADS_6:
2246 numThreadsRxNumerical = 6;
2247 break;
2248 case UCC_GETH_NUM_OF_THREADS_8:
2249 numThreadsRxNumerical = 8;
2250 break;
2251 default:
2252 if (netif_msg_ifup(ugeth))
2253 ugeth_err("%s: Bad number of Rx threads value.",
2254 __func__);
2255 return -EINVAL;
2256 break;
2257 }
2258
2259 switch (ug_info->numThreadsTx) {
2260 case UCC_GETH_NUM_OF_THREADS_1:
2261 numThreadsTxNumerical = 1;
2262 break;
2263 case UCC_GETH_NUM_OF_THREADS_2:
2264 numThreadsTxNumerical = 2;
2265 break;
2266 case UCC_GETH_NUM_OF_THREADS_4:
2267 numThreadsTxNumerical = 4;
2268 break;
2269 case UCC_GETH_NUM_OF_THREADS_6:
2270 numThreadsTxNumerical = 6;
2271 break;
2272 case UCC_GETH_NUM_OF_THREADS_8:
2273 numThreadsTxNumerical = 8;
2274 break;
2275 default:
2276 if (netif_msg_ifup(ugeth))
2277 ugeth_err("%s: Bad number of Tx threads value.",
2278 __func__);
2279 return -EINVAL;
2280 break;
2281 }
2282
2283 /* Calculate rx_extended_features */
2284 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2285 ug_info->ipAddressAlignment ||
2286 (ug_info->numStationAddresses !=
2287 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2288
2289 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2290 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2291 || (ug_info->vlanOperationNonTagged !=
2292 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2293
2294 init_default_reg_vals(&uf_regs->upsmr,
2295 &ug_regs->maccfg1, &ug_regs->maccfg2);
2296
2297 /* Set UPSMR */
2298 /* For more details see the hardware spec. */
2299 init_rx_parameters(ug_info->bro,
2300 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2301
2302 /* We're going to ignore other registers for now, */
2303 /* except as needed to get up and running */
2304
2305 /* Set MACCFG1 */
2306 /* For more details see the hardware spec. */
2307 init_flow_control_params(ug_info->aufc,
2308 ug_info->receiveFlowControl,
2309 ug_info->transmitFlowControl,
2310 ug_info->pausePeriod,
2311 ug_info->extensionField,
2312 &uf_regs->upsmr,
2313 &ug_regs->uempr, &ug_regs->maccfg1);
2314
2315 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2316
2317 /* Set IPGIFG */
2318 /* For more details see the hardware spec. */
2319 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2320 ug_info->nonBackToBackIfgPart2,
2321 ug_info->
2322 miminumInterFrameGapEnforcement,
2323 ug_info->backToBackInterFrameGap,
2324 &ug_regs->ipgifg);
2325 if (ret_val != 0) {
2326 if (netif_msg_ifup(ugeth))
2327 ugeth_err("%s: IPGIFG initialization parameter too large.",
2328 __func__);
2329 return ret_val;
2330 }
2331
2332 /* Set HAFDUP */
2333 /* For more details see the hardware spec. */
2334 ret_val = init_half_duplex_params(ug_info->altBeb,
2335 ug_info->backPressureNoBackoff,
2336 ug_info->noBackoff,
2337 ug_info->excessDefer,
2338 ug_info->altBebTruncation,
2339 ug_info->maxRetransmission,
2340 ug_info->collisionWindow,
2341 &ug_regs->hafdup);
2342 if (ret_val != 0) {
2343 if (netif_msg_ifup(ugeth))
2344 ugeth_err("%s: Half Duplex initialization parameter too large.",
2345 __func__);
2346 return ret_val;
2347 }
2348
2349 /* Set IFSTAT */
2350 /* For more details see the hardware spec. */
2351 /* Read only - resets upon read */
2352 ifstat = in_be32(&ug_regs->ifstat);
2353
2354 /* Clear UEMPR */
2355 /* For more details see the hardware spec. */
2356 out_be32(&ug_regs->uempr, 0);
2357
2358 /* Set UESCR */
2359 /* For more details see the hardware spec. */
2360 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2361 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2362 0, &uf_regs->upsmr, &ug_regs->uescr);
2363
2364 /* Allocate Tx bds */
2365 for (j = 0; j < ug_info->numQueuesTx; j++) {
2366 /* Allocate in multiple of
2367 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2368 according to spec */
2369 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2370 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2371 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2372 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2373 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2374 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2375 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2376 u32 align = 4;
2377 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2378 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2379 ugeth->tx_bd_ring_offset[j] =
2380 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2381
2382 if (ugeth->tx_bd_ring_offset[j] != 0)
2383 ugeth->p_tx_bd_ring[j] =
2384 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2385 align) & ~(align - 1));
2386 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2387 ugeth->tx_bd_ring_offset[j] =
2388 qe_muram_alloc(length,
2389 UCC_GETH_TX_BD_RING_ALIGNMENT);
2390 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2391 ugeth->p_tx_bd_ring[j] =
2392 (u8 __iomem *) qe_muram_addr(ugeth->
2393 tx_bd_ring_offset[j]);
2394 }
2395 if (!ugeth->p_tx_bd_ring[j]) {
2396 if (netif_msg_ifup(ugeth))
2397 ugeth_err
2398 ("%s: Can not allocate memory for Tx bd rings.",
2399 __func__);
2400 return -ENOMEM;
2401 }
2402 /* Zero unused end of bd ring, according to spec */
2403 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2404 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2405 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2406 }
2407
2408 /* Allocate Rx bds */
2409 for (j = 0; j < ug_info->numQueuesRx; j++) {
2410 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2411 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2412 u32 align = 4;
2413 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2414 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2415 ugeth->rx_bd_ring_offset[j] =
2416 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2417 if (ugeth->rx_bd_ring_offset[j] != 0)
2418 ugeth->p_rx_bd_ring[j] =
2419 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2420 align) & ~(align - 1));
2421 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2422 ugeth->rx_bd_ring_offset[j] =
2423 qe_muram_alloc(length,
2424 UCC_GETH_RX_BD_RING_ALIGNMENT);
2425 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2426 ugeth->p_rx_bd_ring[j] =
2427 (u8 __iomem *) qe_muram_addr(ugeth->
2428 rx_bd_ring_offset[j]);
2429 }
2430 if (!ugeth->p_rx_bd_ring[j]) {
2431 if (netif_msg_ifup(ugeth))
2432 ugeth_err
2433 ("%s: Can not allocate memory for Rx bd rings.",
2434 __func__);
2435 return -ENOMEM;
2436 }
2437 }
2438
2439 /* Init Tx bds */
2440 for (j = 0; j < ug_info->numQueuesTx; j++) {
2441 /* Setup the skbuff rings */
2442 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2443 ugeth->ug_info->bdRingLenTx[j],
2444 GFP_KERNEL);
2445
2446 if (ugeth->tx_skbuff[j] == NULL) {
2447 if (netif_msg_ifup(ugeth))
2448 ugeth_err("%s: Could not allocate tx_skbuff",
2449 __func__);
2450 return -ENOMEM;
2451 }
2452
2453 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2454 ugeth->tx_skbuff[j][i] = NULL;
2455
2456 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2457 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2458 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2459 /* clear bd buffer */
2460 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2461 /* set bd status and length */
2462 out_be32((u32 __iomem *)bd, 0);
2463 bd += sizeof(struct qe_bd);
2464 }
2465 bd -= sizeof(struct qe_bd);
2466 /* set bd status and length */
2467 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2468 }
2469
2470 /* Init Rx bds */
2471 for (j = 0; j < ug_info->numQueuesRx; j++) {
2472 /* Setup the skbuff rings */
2473 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2474 ugeth->ug_info->bdRingLenRx[j],
2475 GFP_KERNEL);
2476
2477 if (ugeth->rx_skbuff[j] == NULL) {
2478 if (netif_msg_ifup(ugeth))
2479 ugeth_err("%s: Could not allocate rx_skbuff",
2480 __func__);
2481 return -ENOMEM;
2482 }
2483
2484 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2485 ugeth->rx_skbuff[j][i] = NULL;
2486
2487 ugeth->skb_currx[j] = 0;
2488 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2489 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2490 /* set bd status and length */
2491 out_be32((u32 __iomem *)bd, R_I);
2492 /* clear bd buffer */
2493 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2494 bd += sizeof(struct qe_bd);
2495 }
2496 bd -= sizeof(struct qe_bd);
2497 /* set bd status and length */
2498 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2499 }
2500
2501 /*
2502 * Global PRAM
2503 */
2504 /* Tx global PRAM */
2505 /* Allocate global tx parameter RAM page */
2506 ugeth->tx_glbl_pram_offset =
2507 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2508 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2509 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2510 if (netif_msg_ifup(ugeth))
2511 ugeth_err
2512 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2513 __func__);
2514 return -ENOMEM;
2515 }
2516 ugeth->p_tx_glbl_pram =
2517 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2518 tx_glbl_pram_offset);
2519 /* Zero out p_tx_glbl_pram */
2520 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2521
2522 /* Fill global PRAM */
2523
2524 /* TQPTR */
2525 /* Size varies with number of Tx threads */
2526 ugeth->thread_dat_tx_offset =
2527 qe_muram_alloc(numThreadsTxNumerical *
2528 sizeof(struct ucc_geth_thread_data_tx) +
2529 32 * (numThreadsTxNumerical == 1),
2530 UCC_GETH_THREAD_DATA_ALIGNMENT);
2531 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2532 if (netif_msg_ifup(ugeth))
2533 ugeth_err
2534 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2535 __func__);
2536 return -ENOMEM;
2537 }
2538
2539 ugeth->p_thread_data_tx =
2540 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2541 thread_dat_tx_offset);
2542 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2543
2544 /* vtagtable */
2545 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2546 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2547 ug_info->vtagtable[i]);
2548
2549 /* iphoffset */
2550 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2551 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2552 ug_info->iphoffset[i]);
2553
2554 /* SQPTR */
2555 /* Size varies with number of Tx queues */
2556 ugeth->send_q_mem_reg_offset =
2557 qe_muram_alloc(ug_info->numQueuesTx *
2558 sizeof(struct ucc_geth_send_queue_qd),
2559 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2560 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2561 if (netif_msg_ifup(ugeth))
2562 ugeth_err
2563 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2564 __func__);
2565 return -ENOMEM;
2566 }
2567
2568 ugeth->p_send_q_mem_reg =
2569 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2570 send_q_mem_reg_offset);
2571 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2572
2573 /* Setup the table */
2574 /* Assume BD rings are already established */
2575 for (i = 0; i < ug_info->numQueuesTx; i++) {
2576 endOfRing =
2577 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2578 1) * sizeof(struct qe_bd);
2579 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2580 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2581 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2582 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2583 last_bd_completed_address,
2584 (u32) virt_to_phys(endOfRing));
2585 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2586 MEM_PART_MURAM) {
2587 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2588 (u32) immrbar_virt_to_phys(ugeth->
2589 p_tx_bd_ring[i]));
2590 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2591 last_bd_completed_address,
2592 (u32) immrbar_virt_to_phys(endOfRing));
2593 }
2594 }
2595
2596 /* schedulerbasepointer */
2597
2598 if (ug_info->numQueuesTx > 1) {
2599 /* scheduler exists only if more than 1 tx queue */
2600 ugeth->scheduler_offset =
2601 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2602 UCC_GETH_SCHEDULER_ALIGNMENT);
2603 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2604 if (netif_msg_ifup(ugeth))
2605 ugeth_err
2606 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2607 __func__);
2608 return -ENOMEM;
2609 }
2610
2611 ugeth->p_scheduler =
2612 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2613 scheduler_offset);
2614 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2615 ugeth->scheduler_offset);
2616 /* Zero out p_scheduler */
2617 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2618
2619 /* Set values in scheduler */
2620 out_be32(&ugeth->p_scheduler->mblinterval,
2621 ug_info->mblinterval);
2622 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2623 ug_info->nortsrbytetime);
2624 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2625 out_8(&ugeth->p_scheduler->strictpriorityq,
2626 ug_info->strictpriorityq);
2627 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2628 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2629 for (i = 0; i < NUM_TX_QUEUES; i++)
2630 out_8(&ugeth->p_scheduler->weightfactor[i],
2631 ug_info->weightfactor[i]);
2632
2633 /* Set pointers to cpucount registers in scheduler */
2634 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2635 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2636 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2637 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2638 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2639 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2640 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2641 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2642 }
2643
2644 /* schedulerbasepointer */
2645 /* TxRMON_PTR (statistics) */
2646 if (ug_info->
2647 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2648 ugeth->tx_fw_statistics_pram_offset =
2649 qe_muram_alloc(sizeof
2650 (struct ucc_geth_tx_firmware_statistics_pram),
2651 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2652 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2653 if (netif_msg_ifup(ugeth))
2654 ugeth_err
2655 ("%s: Can not allocate DPRAM memory for"
2656 " p_tx_fw_statistics_pram.",
2657 __func__);
2658 return -ENOMEM;
2659 }
2660 ugeth->p_tx_fw_statistics_pram =
2661 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2662 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2663 /* Zero out p_tx_fw_statistics_pram */
2664 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2665 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2666 }
2667
2668 /* temoder */
2669 /* Already has speed set */
2670
2671 if (ug_info->numQueuesTx > 1)
2672 temoder |= TEMODER_SCHEDULER_ENABLE;
2673 if (ug_info->ipCheckSumGenerate)
2674 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2675 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2676 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2677
2678 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2679
2680 /* Function code register value to be used later */
2681 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2682 /* Required for QE */
2683
2684 /* function code register */
2685 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2686
2687 /* Rx global PRAM */
2688 /* Allocate global rx parameter RAM page */
2689 ugeth->rx_glbl_pram_offset =
2690 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2691 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2692 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2693 if (netif_msg_ifup(ugeth))
2694 ugeth_err
2695 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2696 __func__);
2697 return -ENOMEM;
2698 }
2699 ugeth->p_rx_glbl_pram =
2700 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2701 rx_glbl_pram_offset);
2702 /* Zero out p_rx_glbl_pram */
2703 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2704
2705 /* Fill global PRAM */
2706
2707 /* RQPTR */
2708 /* Size varies with number of Rx threads */
2709 ugeth->thread_dat_rx_offset =
2710 qe_muram_alloc(numThreadsRxNumerical *
2711 sizeof(struct ucc_geth_thread_data_rx),
2712 UCC_GETH_THREAD_DATA_ALIGNMENT);
2713 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2714 if (netif_msg_ifup(ugeth))
2715 ugeth_err
2716 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2717 __func__);
2718 return -ENOMEM;
2719 }
2720
2721 ugeth->p_thread_data_rx =
2722 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2723 thread_dat_rx_offset);
2724 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2725
2726 /* typeorlen */
2727 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2728
2729 /* rxrmonbaseptr (statistics) */
2730 if (ug_info->
2731 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2732 ugeth->rx_fw_statistics_pram_offset =
2733 qe_muram_alloc(sizeof
2734 (struct ucc_geth_rx_firmware_statistics_pram),
2735 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2736 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2737 if (netif_msg_ifup(ugeth))
2738 ugeth_err
2739 ("%s: Can not allocate DPRAM memory for"
2740 " p_rx_fw_statistics_pram.", __func__);
2741 return -ENOMEM;
2742 }
2743 ugeth->p_rx_fw_statistics_pram =
2744 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2745 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2746 /* Zero out p_rx_fw_statistics_pram */
2747 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2748 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2749 }
2750
2751 /* intCoalescingPtr */
2752
2753 /* Size varies with number of Rx queues */
2754 ugeth->rx_irq_coalescing_tbl_offset =
2755 qe_muram_alloc(ug_info->numQueuesRx *
2756 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2757 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2758 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2759 if (netif_msg_ifup(ugeth))
2760 ugeth_err
2761 ("%s: Can not allocate DPRAM memory for"
2762 " p_rx_irq_coalescing_tbl.", __func__);
2763 return -ENOMEM;
2764 }
2765
2766 ugeth->p_rx_irq_coalescing_tbl =
2767 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2768 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2769 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2770 ugeth->rx_irq_coalescing_tbl_offset);
2771
2772 /* Fill interrupt coalescing table */
2773 for (i = 0; i < ug_info->numQueuesRx; i++) {
2774 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2775 interruptcoalescingmaxvalue,
2776 ug_info->interruptcoalescingmaxvalue[i]);
2777 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2778 interruptcoalescingcounter,
2779 ug_info->interruptcoalescingmaxvalue[i]);
2780 }
2781
2782 /* MRBLR */
2783 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2784 &ugeth->p_rx_glbl_pram->mrblr);
2785 /* MFLR */
2786 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2787 /* MINFLR */
2788 init_min_frame_len(ug_info->minFrameLength,
2789 &ugeth->p_rx_glbl_pram->minflr,
2790 &ugeth->p_rx_glbl_pram->mrblr);
2791 /* MAXD1 */
2792 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2793 /* MAXD2 */
2794 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2795
2796 /* l2qt */
2797 l2qt = 0;
2798 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2799 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2800 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2801
2802 /* l3qt */
2803 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2804 l3qt = 0;
2805 for (i = 0; i < 8; i++)
2806 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2807 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2808 }
2809
2810 /* vlantype */
2811 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2812
2813 /* vlantci */
2814 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2815
2816 /* ecamptr */
2817 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2818
2819 /* RBDQPTR */
2820 /* Size varies with number of Rx queues */
2821 ugeth->rx_bd_qs_tbl_offset =
2822 qe_muram_alloc(ug_info->numQueuesRx *
2823 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2824 sizeof(struct ucc_geth_rx_prefetched_bds)),
2825 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2826 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2827 if (netif_msg_ifup(ugeth))
2828 ugeth_err
2829 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2830 __func__);
2831 return -ENOMEM;
2832 }
2833
2834 ugeth->p_rx_bd_qs_tbl =
2835 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2836 rx_bd_qs_tbl_offset);
2837 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2838 /* Zero out p_rx_bd_qs_tbl */
2839 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2840 0,
2841 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2842 sizeof(struct ucc_geth_rx_prefetched_bds)));
2843
2844 /* Setup the table */
2845 /* Assume BD rings are already established */
2846 for (i = 0; i < ug_info->numQueuesRx; i++) {
2847 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2848 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2849 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2850 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2851 MEM_PART_MURAM) {
2852 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2853 (u32) immrbar_virt_to_phys(ugeth->
2854 p_rx_bd_ring[i]));
2855 }
2856 /* rest of fields handled by QE */
2857 }
2858
2859 /* remoder */
2860 /* Already has speed set */
2861
2862 if (ugeth->rx_extended_features)
2863 remoder |= REMODER_RX_EXTENDED_FEATURES;
2864 if (ug_info->rxExtendedFiltering)
2865 remoder |= REMODER_RX_EXTENDED_FILTERING;
2866 if (ug_info->dynamicMaxFrameLength)
2867 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2868 if (ug_info->dynamicMinFrameLength)
2869 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2870 remoder |=
2871 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2872 remoder |=
2873 ug_info->
2874 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2875 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2876 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2877 if (ug_info->ipCheckSumCheck)
2878 remoder |= REMODER_IP_CHECKSUM_CHECK;
2879 if (ug_info->ipAddressAlignment)
2880 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2881 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2882
2883 /* Note that this function must be called */
2884 /* ONLY AFTER p_tx_fw_statistics_pram */
2885 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2886 init_firmware_statistics_gathering_mode((ug_info->
2887 statisticsMode &
2888 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2889 (ug_info->statisticsMode &
2890 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2891 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2892 ugeth->tx_fw_statistics_pram_offset,
2893 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2894 ugeth->rx_fw_statistics_pram_offset,
2895 &ugeth->p_tx_glbl_pram->temoder,
2896 &ugeth->p_rx_glbl_pram->remoder);
2897
2898 /* function code register */
2899 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2900
2901 /* initialize extended filtering */
2902 if (ug_info->rxExtendedFiltering) {
2903 if (!ug_info->extendedFilteringChainPointer) {
2904 if (netif_msg_ifup(ugeth))
2905 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2906 __func__);
2907 return -EINVAL;
2908 }
2909
2910 /* Allocate memory for extended filtering Mode Global
2911 Parameters */
2912 ugeth->exf_glbl_param_offset =
2913 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2914 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2915 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2916 if (netif_msg_ifup(ugeth))
2917 ugeth_err
2918 ("%s: Can not allocate DPRAM memory for"
2919 " p_exf_glbl_param.", __func__);
2920 return -ENOMEM;
2921 }
2922
2923 ugeth->p_exf_glbl_param =
2924 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2925 exf_glbl_param_offset);
2926 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2927 ugeth->exf_glbl_param_offset);
2928 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2929 (u32) ug_info->extendedFilteringChainPointer);
2930
2931 } else { /* initialize 82xx style address filtering */
2932
2933 /* Init individual address recognition registers to disabled */
2934
2935 for (j = 0; j < NUM_OF_PADDRS; j++)
2936 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2937
2938 p_82xx_addr_filt =
2939 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2940 p_rx_glbl_pram->addressfiltering;
2941
2942 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2943 ENET_ADDR_TYPE_GROUP);
2944 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2945 ENET_ADDR_TYPE_INDIVIDUAL);
2946 }
2947
2948 /*
2949 * Initialize UCC at QE level
2950 */
2951
2952 command = QE_INIT_TX_RX;
2953
2954 /* Allocate shadow InitEnet command parameter structure.
2955 * This is needed because after the InitEnet command is executed,
2956 * the structure in DPRAM is released, because DPRAM is a premium
2957 * resource.
2958 * This shadow structure keeps a copy of what was done so that the
2959 * allocated resources can be released when the channel is freed.
2960 */
2961 if (!(ugeth->p_init_enet_param_shadow =
2962 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2963 if (netif_msg_ifup(ugeth))
2964 ugeth_err
2965 ("%s: Can not allocate memory for"
2966 " p_UccInitEnetParamShadows.", __func__);
2967 return -ENOMEM;
2968 }
2969 /* Zero out *p_init_enet_param_shadow */
2970 memset((char *)ugeth->p_init_enet_param_shadow,
2971 0, sizeof(struct ucc_geth_init_pram));
2972
2973 /* Fill shadow InitEnet command parameter structure */
2974
2975 ugeth->p_init_enet_param_shadow->resinit1 =
2976 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2977 ugeth->p_init_enet_param_shadow->resinit2 =
2978 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2979 ugeth->p_init_enet_param_shadow->resinit3 =
2980 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2981 ugeth->p_init_enet_param_shadow->resinit4 =
2982 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2983 ugeth->p_init_enet_param_shadow->resinit5 =
2984 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2985 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2986 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2987 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2988 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2989
2990 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2991 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2992 if ((ug_info->largestexternallookupkeysize !=
2993 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2994 && (ug_info->largestexternallookupkeysize !=
2995 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2996 && (ug_info->largestexternallookupkeysize !=
2997 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2998 if (netif_msg_ifup(ugeth))
2999 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3000 __func__);
3001 return -EINVAL;
3002 }
3003 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3004 ug_info->largestexternallookupkeysize;
3005 size = sizeof(struct ucc_geth_thread_rx_pram);
3006 if (ug_info->rxExtendedFiltering) {
3007 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3008 if (ug_info->largestexternallookupkeysize ==
3009 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3010 size +=
3011 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3012 if (ug_info->largestexternallookupkeysize ==
3013 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3014 size +=
3015 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3016 }
3017
3018 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3019 p_init_enet_param_shadow->rxthread[0]),
3020 (u8) (numThreadsRxNumerical + 1)
3021 /* Rx needs one extra for terminator */
3022 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3023 ug_info->riscRx, 1)) != 0) {
3024 if (netif_msg_ifup(ugeth))
3025 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3026 __func__);
3027 return ret_val;
3028 }
3029
3030 ugeth->p_init_enet_param_shadow->txglobal =
3031 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3032 if ((ret_val =
3033 fill_init_enet_entries(ugeth,
3034 &(ugeth->p_init_enet_param_shadow->
3035 txthread[0]), numThreadsTxNumerical,
3036 sizeof(struct ucc_geth_thread_tx_pram),
3037 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3038 ug_info->riscTx, 0)) != 0) {
3039 if (netif_msg_ifup(ugeth))
3040 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3041 __func__);
3042 return ret_val;
3043 }
3044
3045 /* Load Rx bds with buffers */
3046 for (i = 0; i < ug_info->numQueuesRx; i++) {
3047 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3048 if (netif_msg_ifup(ugeth))
3049 ugeth_err("%s: Can not fill Rx bds with buffers.",
3050 __func__);
3051 return ret_val;
3052 }
3053 }
3054
3055 /* Allocate InitEnet command parameter structure */
3056 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3057 if (IS_ERR_VALUE(init_enet_pram_offset)) {
3058 if (netif_msg_ifup(ugeth))
3059 ugeth_err
3060 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3061 __func__);
3062 return -ENOMEM;
3063 }
3064 p_init_enet_pram =
3065 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3066
3067 /* Copy shadow InitEnet command parameter structure into PRAM */
3068 out_8(&p_init_enet_pram->resinit1,
3069 ugeth->p_init_enet_param_shadow->resinit1);
3070 out_8(&p_init_enet_pram->resinit2,
3071 ugeth->p_init_enet_param_shadow->resinit2);
3072 out_8(&p_init_enet_pram->resinit3,
3073 ugeth->p_init_enet_param_shadow->resinit3);
3074 out_8(&p_init_enet_pram->resinit4,
3075 ugeth->p_init_enet_param_shadow->resinit4);
3076 out_be16(&p_init_enet_pram->resinit5,
3077 ugeth->p_init_enet_param_shadow->resinit5);
3078 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3079 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3080 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3081 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3082 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3083 out_be32(&p_init_enet_pram->rxthread[i],
3084 ugeth->p_init_enet_param_shadow->rxthread[i]);
3085 out_be32(&p_init_enet_pram->txglobal,
3086 ugeth->p_init_enet_param_shadow->txglobal);
3087 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3088 out_be32(&p_init_enet_pram->txthread[i],
3089 ugeth->p_init_enet_param_shadow->txthread[i]);
3090
3091 /* Issue QE command */
3092 cecr_subblock =
3093 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3094 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3095 init_enet_pram_offset);
3096
3097 /* Free InitEnet command parameter */
3098 qe_muram_free(init_enet_pram_offset);
3099
3100 return 0;
3101 }
3102
3103 /* This is called by the kernel when a frame is ready for transmission. */
3104 /* It is pointed to by the dev->hard_start_xmit function pointer */
3105 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3106 {
3107 struct ucc_geth_private *ugeth = netdev_priv(dev);
3108 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3109 struct ucc_fast_private *uccf;
3110 #endif
3111 u8 __iomem *bd; /* BD pointer */
3112 u32 bd_status;
3113 u8 txQ = 0;
3114 unsigned long flags;
3115
3116 ugeth_vdbg("%s: IN", __func__);
3117
3118 spin_lock_irqsave(&ugeth->lock, flags);
3119
3120 dev->stats.tx_bytes += skb->len;
3121
3122 /* Start from the next BD that should be filled */
3123 bd = ugeth->txBd[txQ];
3124 bd_status = in_be32((u32 __iomem *)bd);
3125 /* Save the skb pointer so we can free it later */
3126 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3127
3128 /* Update the current skb pointer (wrapping if this was the last) */
3129 ugeth->skb_curtx[txQ] =
3130 (ugeth->skb_curtx[txQ] +
3131 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3132
3133 /* set up the buffer descriptor */
3134 out_be32(&((struct qe_bd __iomem *)bd)->buf,
3135 dma_map_single(ugeth->dev, skb->data,
3136 skb->len, DMA_TO_DEVICE));
3137
3138 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3139
3140 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3141
3142 /* set bd status and length */
3143 out_be32((u32 __iomem *)bd, bd_status);
3144
3145 dev->trans_start = jiffies;
3146
3147 /* Move to next BD in the ring */
3148 if (!(bd_status & T_W))
3149 bd += sizeof(struct qe_bd);
3150 else
3151 bd = ugeth->p_tx_bd_ring[txQ];
3152
3153 /* If the next BD still needs to be cleaned up, then the bds
3154 are full. We need to tell the kernel to stop sending us stuff. */
3155 if (bd == ugeth->confBd[txQ]) {
3156 if (!netif_queue_stopped(dev))
3157 netif_stop_queue(dev);
3158 }
3159
3160 ugeth->txBd[txQ] = bd;
3161
3162 if (ugeth->p_scheduler) {
3163 ugeth->cpucount[txQ]++;
3164 /* Indicate to QE that there are more Tx bds ready for
3165 transmission */
3166 /* This is done by writing a running counter of the bd
3167 count to the scheduler PRAM. */
3168 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3169 }
3170
3171 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3172 uccf = ugeth->uccf;
3173 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3174 #endif
3175 spin_unlock_irqrestore(&ugeth->lock, flags);
3176
3177 return NETDEV_TX_OK;
3178 }
3179
3180 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3181 {
3182 struct sk_buff *skb;
3183 u8 __iomem *bd;
3184 u16 length, howmany = 0;
3185 u32 bd_status;
3186 u8 *bdBuffer;
3187 struct net_device *dev;
3188
3189 ugeth_vdbg("%s: IN", __func__);
3190
3191 dev = ugeth->ndev;
3192
3193 /* collect received buffers */
3194 bd = ugeth->rxBd[rxQ];
3195
3196 bd_status = in_be32((u32 __iomem *)bd);
3197
3198 /* while there are received buffers and BD is full (~R_E) */
3199 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3200 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3201 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3202 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3203
3204 /* determine whether buffer is first, last, first and last
3205 (single buffer frame) or middle (not first and not last) */
3206 if (!skb ||
3207 (!(bd_status & (R_F | R_L))) ||
3208 (bd_status & R_ERRORS_FATAL)) {
3209 if (netif_msg_rx_err(ugeth))
3210 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3211 __func__, __LINE__, (u32) skb);
3212 if (skb) {
3213 skb->data = skb->head + NET_SKB_PAD;
3214 __skb_queue_head(&ugeth->rx_recycle, skb);
3215 }
3216
3217 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3218 dev->stats.rx_dropped++;
3219 } else {
3220 dev->stats.rx_packets++;
3221 howmany++;
3222
3223 /* Prep the skb for the packet */
3224 skb_put(skb, length);
3225
3226 /* Tell the skb what kind of packet this is */
3227 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3228
3229 dev->stats.rx_bytes += length;
3230 /* Send the packet up the stack */
3231 netif_receive_skb(skb);
3232 }
3233
3234 skb = get_new_skb(ugeth, bd);
3235 if (!skb) {
3236 if (netif_msg_rx_err(ugeth))
3237 ugeth_warn("%s: No Rx Data Buffer", __func__);
3238 dev->stats.rx_dropped++;
3239 break;
3240 }
3241
3242 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3243
3244 /* update to point at the next skb */
3245 ugeth->skb_currx[rxQ] =
3246 (ugeth->skb_currx[rxQ] +
3247 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3248
3249 if (bd_status & R_W)
3250 bd = ugeth->p_rx_bd_ring[rxQ];
3251 else
3252 bd += sizeof(struct qe_bd);
3253
3254 bd_status = in_be32((u32 __iomem *)bd);
3255 }
3256
3257 ugeth->rxBd[rxQ] = bd;
3258 return howmany;
3259 }
3260
3261 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3262 {
3263 /* Start from the next BD that should be filled */
3264 struct ucc_geth_private *ugeth = netdev_priv(dev);
3265 u8 __iomem *bd; /* BD pointer */
3266 u32 bd_status;
3267
3268 bd = ugeth->confBd[txQ];
3269 bd_status = in_be32((u32 __iomem *)bd);
3270
3271 /* Normal processing. */
3272 while ((bd_status & T_R) == 0) {
3273 struct sk_buff *skb;
3274
3275 /* BD contains already transmitted buffer. */
3276 /* Handle the transmitted buffer and release */
3277 /* the BD to be used with the current frame */
3278
3279 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3280 if (!skb)
3281 break;
3282
3283 dev->stats.tx_packets++;
3284
3285 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3286 skb_recycle_check(skb,
3287 ugeth->ug_info->uf_info.max_rx_buf_length +
3288 UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3289 __skb_queue_head(&ugeth->rx_recycle, skb);
3290 else
3291 dev_kfree_skb(skb);
3292
3293 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3294 ugeth->skb_dirtytx[txQ] =
3295 (ugeth->skb_dirtytx[txQ] +
3296 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3297
3298 /* We freed a buffer, so now we can restart transmission */
3299 if (netif_queue_stopped(dev))
3300 netif_wake_queue(dev);
3301
3302 /* Advance the confirmation BD pointer */
3303 if (!(bd_status & T_W))
3304 bd += sizeof(struct qe_bd);
3305 else
3306 bd = ugeth->p_tx_bd_ring[txQ];
3307 bd_status = in_be32((u32 __iomem *)bd);
3308 }
3309 ugeth->confBd[txQ] = bd;
3310 return 0;
3311 }
3312
3313 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3314 {
3315 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3316 struct ucc_geth_info *ug_info;
3317 int howmany, i;
3318
3319 ug_info = ugeth->ug_info;
3320
3321 /* Tx event processing */
3322 spin_lock(&ugeth->lock);
3323 for (i = 0; i < ug_info->numQueuesTx; i++)
3324 ucc_geth_tx(ugeth->ndev, i);
3325 spin_unlock(&ugeth->lock);
3326
3327 howmany = 0;
3328 for (i = 0; i < ug_info->numQueuesRx; i++)
3329 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3330
3331 if (howmany < budget) {
3332 napi_complete(napi);
3333 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3334 }
3335
3336 return howmany;
3337 }
3338
3339 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3340 {
3341 struct net_device *dev = info;
3342 struct ucc_geth_private *ugeth = netdev_priv(dev);
3343 struct ucc_fast_private *uccf;
3344 struct ucc_geth_info *ug_info;
3345 register u32 ucce;
3346 register u32 uccm;
3347
3348 ugeth_vdbg("%s: IN", __func__);
3349
3350 uccf = ugeth->uccf;
3351 ug_info = ugeth->ug_info;
3352
3353 /* read and clear events */
3354 ucce = (u32) in_be32(uccf->p_ucce);
3355 uccm = (u32) in_be32(uccf->p_uccm);
3356 ucce &= uccm;
3357 out_be32(uccf->p_ucce, ucce);
3358
3359 /* check for receive events that require processing */
3360 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3361 if (napi_schedule_prep(&ugeth->napi)) {
3362 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3363 out_be32(uccf->p_uccm, uccm);
3364 __napi_schedule(&ugeth->napi);
3365 }
3366 }
3367
3368 /* Errors and other events */
3369 if (ucce & UCCE_OTHER) {
3370 if (ucce & UCC_GETH_UCCE_BSY)
3371 dev->stats.rx_errors++;
3372 if (ucce & UCC_GETH_UCCE_TXE)
3373 dev->stats.tx_errors++;
3374 }
3375
3376 return IRQ_HANDLED;
3377 }
3378
3379 #ifdef CONFIG_NET_POLL_CONTROLLER
3380 /*
3381 * Polling 'interrupt' - used by things like netconsole to send skbs
3382 * without having to re-enable interrupts. It's not called while
3383 * the interrupt routine is executing.
3384 */
3385 static void ucc_netpoll(struct net_device *dev)
3386 {
3387 struct ucc_geth_private *ugeth = netdev_priv(dev);
3388 int irq = ugeth->ug_info->uf_info.irq;
3389
3390 disable_irq(irq);
3391 ucc_geth_irq_handler(irq, dev);
3392 enable_irq(irq);
3393 }
3394 #endif /* CONFIG_NET_POLL_CONTROLLER */
3395
3396 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3397 {
3398 struct ucc_geth_private *ugeth = netdev_priv(dev);
3399 struct sockaddr *addr = p;
3400
3401 if (!is_valid_ether_addr(addr->sa_data))
3402 return -EADDRNOTAVAIL;
3403
3404 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3405
3406 /*
3407 * If device is not running, we will set mac addr register
3408 * when opening the device.
3409 */
3410 if (!netif_running(dev))
3411 return 0;
3412
3413 spin_lock_irq(&ugeth->lock);
3414 init_mac_station_addr_regs(dev->dev_addr[0],
3415 dev->dev_addr[1],
3416 dev->dev_addr[2],
3417 dev->dev_addr[3],
3418 dev->dev_addr[4],
3419 dev->dev_addr[5],
3420 &ugeth->ug_regs->macstnaddr1,
3421 &ugeth->ug_regs->macstnaddr2);
3422 spin_unlock_irq(&ugeth->lock);
3423
3424 return 0;
3425 }
3426
3427 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3428 {
3429 struct net_device *dev = ugeth->ndev;
3430 int err;
3431
3432 err = ucc_struct_init(ugeth);
3433 if (err) {
3434 if (netif_msg_ifup(ugeth))
3435 ugeth_err("%s: Cannot configure internal struct, "
3436 "aborting.", dev->name);
3437 goto err;
3438 }
3439
3440 err = ucc_geth_startup(ugeth);
3441 if (err) {
3442 if (netif_msg_ifup(ugeth))
3443 ugeth_err("%s: Cannot configure net device, aborting.",
3444 dev->name);
3445 goto err;
3446 }
3447
3448 err = adjust_enet_interface(ugeth);
3449 if (err) {
3450 if (netif_msg_ifup(ugeth))
3451 ugeth_err("%s: Cannot configure net device, aborting.",
3452 dev->name);
3453 goto err;
3454 }
3455
3456 /* Set MACSTNADDR1, MACSTNADDR2 */
3457 /* For more details see the hardware spec. */
3458 init_mac_station_addr_regs(dev->dev_addr[0],
3459 dev->dev_addr[1],
3460 dev->dev_addr[2],
3461 dev->dev_addr[3],
3462 dev->dev_addr[4],
3463 dev->dev_addr[5],
3464 &ugeth->ug_regs->macstnaddr1,
3465 &ugeth->ug_regs->macstnaddr2);
3466
3467 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3468 if (err) {
3469 if (netif_msg_ifup(ugeth))
3470 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3471 goto err;
3472 }
3473
3474 return 0;
3475 err:
3476 ucc_geth_stop(ugeth);
3477 return err;
3478 }
3479
3480 /* Called when something needs to use the ethernet device */
3481 /* Returns 0 for success. */
3482 static int ucc_geth_open(struct net_device *dev)
3483 {
3484 struct ucc_geth_private *ugeth = netdev_priv(dev);
3485 int err;
3486
3487 ugeth_vdbg("%s: IN", __func__);
3488
3489 /* Test station address */
3490 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3491 if (netif_msg_ifup(ugeth))
3492 ugeth_err("%s: Multicast address used for station "
3493 "address - is this what you wanted?",
3494 __func__);
3495 return -EINVAL;
3496 }
3497
3498 err = init_phy(dev);
3499 if (err) {
3500 if (netif_msg_ifup(ugeth))
3501 ugeth_err("%s: Cannot initialize PHY, aborting.",
3502 dev->name);
3503 return err;
3504 }
3505
3506 err = ucc_geth_init_mac(ugeth);
3507 if (err) {
3508 if (netif_msg_ifup(ugeth))
3509 ugeth_err("%s: Cannot initialize MAC, aborting.",
3510 dev->name);
3511 goto err;
3512 }
3513
3514 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3515 0, "UCC Geth", dev);
3516 if (err) {
3517 if (netif_msg_ifup(ugeth))
3518 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3519 dev->name);
3520 goto err;
3521 }
3522
3523 phy_start(ugeth->phydev);
3524 napi_enable(&ugeth->napi);
3525 netif_start_queue(dev);
3526
3527 device_set_wakeup_capable(&dev->dev,
3528 qe_alive_during_sleep() || ugeth->phydev->irq);
3529 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3530
3531 return err;
3532
3533 err:
3534 ucc_geth_stop(ugeth);
3535 return err;
3536 }
3537
3538 /* Stops the kernel queue, and halts the controller */
3539 static int ucc_geth_close(struct net_device *dev)
3540 {
3541 struct ucc_geth_private *ugeth = netdev_priv(dev);
3542
3543 ugeth_vdbg("%s: IN", __func__);
3544
3545 napi_disable(&ugeth->napi);
3546
3547 ucc_geth_stop(ugeth);
3548
3549 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3550
3551 netif_stop_queue(dev);
3552
3553 return 0;
3554 }
3555
3556 /* Reopen device. This will reset the MAC and PHY. */
3557 static void ucc_geth_timeout_work(struct work_struct *work)
3558 {
3559 struct ucc_geth_private *ugeth;
3560 struct net_device *dev;
3561
3562 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3563 dev = ugeth->ndev;
3564
3565 ugeth_vdbg("%s: IN", __func__);
3566
3567 dev->stats.tx_errors++;
3568
3569 ugeth_dump_regs(ugeth);
3570
3571 if (dev->flags & IFF_UP) {
3572 /*
3573 * Must reset MAC *and* PHY. This is done by reopening
3574 * the device.
3575 */
3576 ucc_geth_close(dev);
3577 ucc_geth_open(dev);
3578 }
3579
3580 netif_tx_schedule_all(dev);
3581 }
3582
3583 /*
3584 * ucc_geth_timeout gets called when a packet has not been
3585 * transmitted after a set amount of time.
3586 */
3587 static void ucc_geth_timeout(struct net_device *dev)
3588 {
3589 struct ucc_geth_private *ugeth = netdev_priv(dev);
3590
3591 netif_carrier_off(dev);
3592 schedule_work(&ugeth->timeout_work);
3593 }
3594
3595
3596 #ifdef CONFIG_PM
3597
3598 static int ucc_geth_suspend(struct of_device *ofdev, pm_message_t state)
3599 {
3600 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3601 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3602
3603 if (!netif_running(ndev))
3604 return 0;
3605
3606 napi_disable(&ugeth->napi);
3607
3608 /*
3609 * Disable the controller, otherwise we'll wakeup on any network
3610 * activity.
3611 */
3612 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3613
3614 if (ugeth->wol_en & WAKE_MAGIC) {
3615 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3616 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3617 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3618 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3619 phy_stop(ugeth->phydev);
3620 }
3621
3622 return 0;
3623 }
3624
3625 static int ucc_geth_resume(struct of_device *ofdev)
3626 {
3627 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3628 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3629 int err;
3630
3631 if (!netif_running(ndev))
3632 return 0;
3633
3634 if (qe_alive_during_sleep()) {
3635 if (ugeth->wol_en & WAKE_MAGIC) {
3636 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3637 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3638 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3639 }
3640 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3641 } else {
3642 /*
3643 * Full reinitialization is required if QE shuts down
3644 * during sleep.
3645 */
3646 ucc_geth_memclean(ugeth);
3647
3648 err = ucc_geth_init_mac(ugeth);
3649 if (err) {
3650 ugeth_err("%s: Cannot initialize MAC, aborting.",
3651 ndev->name);
3652 return err;
3653 }
3654 }
3655
3656 ugeth->oldlink = 0;
3657 ugeth->oldspeed = 0;
3658 ugeth->oldduplex = -1;
3659
3660 phy_stop(ugeth->phydev);
3661 phy_start(ugeth->phydev);
3662
3663 napi_enable(&ugeth->napi);
3664 netif_start_queue(ndev);
3665
3666 return 0;
3667 }
3668
3669 #else
3670 #define ucc_geth_suspend NULL
3671 #define ucc_geth_resume NULL
3672 #endif
3673
3674 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3675 {
3676 if (strcasecmp(phy_connection_type, "mii") == 0)
3677 return PHY_INTERFACE_MODE_MII;
3678 if (strcasecmp(phy_connection_type, "gmii") == 0)
3679 return PHY_INTERFACE_MODE_GMII;
3680 if (strcasecmp(phy_connection_type, "tbi") == 0)
3681 return PHY_INTERFACE_MODE_TBI;
3682 if (strcasecmp(phy_connection_type, "rmii") == 0)
3683 return PHY_INTERFACE_MODE_RMII;
3684 if (strcasecmp(phy_connection_type, "rgmii") == 0)
3685 return PHY_INTERFACE_MODE_RGMII;
3686 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3687 return PHY_INTERFACE_MODE_RGMII_ID;
3688 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3689 return PHY_INTERFACE_MODE_RGMII_TXID;
3690 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3691 return PHY_INTERFACE_MODE_RGMII_RXID;
3692 if (strcasecmp(phy_connection_type, "rtbi") == 0)
3693 return PHY_INTERFACE_MODE_RTBI;
3694 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3695 return PHY_INTERFACE_MODE_SGMII;
3696
3697 return PHY_INTERFACE_MODE_MII;
3698 }
3699
3700 static const struct net_device_ops ucc_geth_netdev_ops = {
3701 .ndo_open = ucc_geth_open,
3702 .ndo_stop = ucc_geth_close,
3703 .ndo_start_xmit = ucc_geth_start_xmit,
3704 .ndo_validate_addr = eth_validate_addr,
3705 .ndo_set_mac_address = ucc_geth_set_mac_addr,
3706 .ndo_change_mtu = eth_change_mtu,
3707 .ndo_set_multicast_list = ucc_geth_set_multi,
3708 .ndo_tx_timeout = ucc_geth_timeout,
3709 #ifdef CONFIG_NET_POLL_CONTROLLER
3710 .ndo_poll_controller = ucc_netpoll,
3711 #endif
3712 };
3713
3714 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3715 {
3716 struct device *device = &ofdev->dev;
3717 struct device_node *np = ofdev->node;
3718 struct net_device *dev = NULL;
3719 struct ucc_geth_private *ugeth = NULL;
3720 struct ucc_geth_info *ug_info;
3721 struct resource res;
3722 int err, ucc_num, max_speed = 0;
3723 const unsigned int *prop;
3724 const char *sprop;
3725 const void *mac_addr;
3726 phy_interface_t phy_interface;
3727 static const int enet_to_speed[] = {
3728 SPEED_10, SPEED_10, SPEED_10,
3729 SPEED_100, SPEED_100, SPEED_100,
3730 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3731 };
3732 static const phy_interface_t enet_to_phy_interface[] = {
3733 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3734 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3735 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3736 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3737 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3738 PHY_INTERFACE_MODE_SGMII,
3739 };
3740
3741 ugeth_vdbg("%s: IN", __func__);
3742
3743 prop = of_get_property(np, "cell-index", NULL);
3744 if (!prop) {
3745 prop = of_get_property(np, "device-id", NULL);
3746 if (!prop)
3747 return -ENODEV;
3748 }
3749
3750 ucc_num = *prop - 1;
3751 if ((ucc_num < 0) || (ucc_num > 7))
3752 return -ENODEV;
3753
3754 ug_info = &ugeth_info[ucc_num];
3755 if (ug_info == NULL) {
3756 if (netif_msg_probe(&debug))
3757 ugeth_err("%s: [%d] Missing additional data!",
3758 __func__, ucc_num);
3759 return -ENODEV;
3760 }
3761
3762 ug_info->uf_info.ucc_num = ucc_num;
3763
3764 sprop = of_get_property(np, "rx-clock-name", NULL);
3765 if (sprop) {
3766 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3767 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3768 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3769 printk(KERN_ERR
3770 "ucc_geth: invalid rx-clock-name property\n");
3771 return -EINVAL;
3772 }
3773 } else {
3774 prop = of_get_property(np, "rx-clock", NULL);
3775 if (!prop) {
3776 /* If both rx-clock-name and rx-clock are missing,
3777 we want to tell people to use rx-clock-name. */
3778 printk(KERN_ERR
3779 "ucc_geth: missing rx-clock-name property\n");
3780 return -EINVAL;
3781 }
3782 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3783 printk(KERN_ERR
3784 "ucc_geth: invalid rx-clock propperty\n");
3785 return -EINVAL;
3786 }
3787 ug_info->uf_info.rx_clock = *prop;
3788 }
3789
3790 sprop = of_get_property(np, "tx-clock-name", NULL);
3791 if (sprop) {
3792 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3793 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3794 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3795 printk(KERN_ERR
3796 "ucc_geth: invalid tx-clock-name property\n");
3797 return -EINVAL;
3798 }
3799 } else {
3800 prop = of_get_property(np, "tx-clock", NULL);
3801 if (!prop) {
3802 printk(KERN_ERR
3803 "ucc_geth: mising tx-clock-name property\n");
3804 return -EINVAL;
3805 }
3806 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3807 printk(KERN_ERR
3808 "ucc_geth: invalid tx-clock property\n");
3809 return -EINVAL;
3810 }
3811 ug_info->uf_info.tx_clock = *prop;
3812 }
3813
3814 err = of_address_to_resource(np, 0, &res);
3815 if (err)
3816 return -EINVAL;
3817
3818 ug_info->uf_info.regs = res.start;
3819 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3820
3821 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3822
3823 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3824 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3825
3826 /* get the phy interface type, or default to MII */
3827 prop = of_get_property(np, "phy-connection-type", NULL);
3828 if (!prop) {
3829 /* handle interface property present in old trees */
3830 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3831 if (prop != NULL) {
3832 phy_interface = enet_to_phy_interface[*prop];
3833 max_speed = enet_to_speed[*prop];
3834 } else
3835 phy_interface = PHY_INTERFACE_MODE_MII;
3836 } else {
3837 phy_interface = to_phy_interface((const char *)prop);
3838 }
3839
3840 /* get speed, or derive from PHY interface */
3841 if (max_speed == 0)
3842 switch (phy_interface) {
3843 case PHY_INTERFACE_MODE_GMII:
3844 case PHY_INTERFACE_MODE_RGMII:
3845 case PHY_INTERFACE_MODE_RGMII_ID:
3846 case PHY_INTERFACE_MODE_RGMII_RXID:
3847 case PHY_INTERFACE_MODE_RGMII_TXID:
3848 case PHY_INTERFACE_MODE_TBI:
3849 case PHY_INTERFACE_MODE_RTBI:
3850 case PHY_INTERFACE_MODE_SGMII:
3851 max_speed = SPEED_1000;
3852 break;
3853 default:
3854 max_speed = SPEED_100;
3855 break;
3856 }
3857
3858 if (max_speed == SPEED_1000) {
3859 /* configure muram FIFOs for gigabit operation */
3860 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3861 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3862 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3863 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3864 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3865 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3866 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3867
3868 /* If QE's snum number is 46 which means we need to support
3869 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3870 * more Threads to Rx.
3871 */
3872 if (qe_get_num_of_snums() == 46)
3873 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3874 else
3875 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3876 }
3877
3878 if (netif_msg_probe(&debug))
3879 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3880 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3881 ug_info->uf_info.irq);
3882
3883 /* Create an ethernet device instance */
3884 dev = alloc_etherdev(sizeof(*ugeth));
3885
3886 if (dev == NULL)
3887 return -ENOMEM;
3888
3889 ugeth = netdev_priv(dev);
3890 spin_lock_init(&ugeth->lock);
3891
3892 /* Create CQs for hash tables */
3893 INIT_LIST_HEAD(&ugeth->group_hash_q);
3894 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3895
3896 dev_set_drvdata(device, dev);
3897
3898 /* Set the dev->base_addr to the gfar reg region */
3899 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3900
3901 SET_NETDEV_DEV(dev, device);
3902
3903 /* Fill in the dev structure */
3904 uec_set_ethtool_ops(dev);
3905 dev->netdev_ops = &ucc_geth_netdev_ops;
3906 dev->watchdog_timeo = TX_TIMEOUT;
3907 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3908 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3909 dev->mtu = 1500;
3910
3911 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3912 ugeth->phy_interface = phy_interface;
3913 ugeth->max_speed = max_speed;
3914
3915 err = register_netdev(dev);
3916 if (err) {
3917 if (netif_msg_probe(ugeth))
3918 ugeth_err("%s: Cannot register net device, aborting.",
3919 dev->name);
3920 free_netdev(dev);
3921 return err;
3922 }
3923
3924 mac_addr = of_get_mac_address(np);
3925 if (mac_addr)
3926 memcpy(dev->dev_addr, mac_addr, 6);
3927
3928 ugeth->ug_info = ug_info;
3929 ugeth->dev = device;
3930 ugeth->ndev = dev;
3931 ugeth->node = np;
3932
3933 return 0;
3934 }
3935
3936 static int ucc_geth_remove(struct of_device* ofdev)
3937 {
3938 struct device *device = &ofdev->dev;
3939 struct net_device *dev = dev_get_drvdata(device);
3940 struct ucc_geth_private *ugeth = netdev_priv(dev);
3941
3942 unregister_netdev(dev);
3943 free_netdev(dev);
3944 ucc_geth_memclean(ugeth);
3945 dev_set_drvdata(device, NULL);
3946
3947 return 0;
3948 }
3949
3950 static struct of_device_id ucc_geth_match[] = {
3951 {
3952 .type = "network",
3953 .compatible = "ucc_geth",
3954 },
3955 {},
3956 };
3957
3958 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3959
3960 static struct of_platform_driver ucc_geth_driver = {
3961 .name = DRV_NAME,
3962 .match_table = ucc_geth_match,
3963 .probe = ucc_geth_probe,
3964 .remove = ucc_geth_remove,
3965 .suspend = ucc_geth_suspend,
3966 .resume = ucc_geth_resume,
3967 };
3968
3969 static int __init ucc_geth_init(void)
3970 {
3971 int i, ret;
3972
3973 if (netif_msg_drv(&debug))
3974 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3975 for (i = 0; i < 8; i++)
3976 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3977 sizeof(ugeth_primary_info));
3978
3979 ret = of_register_platform_driver(&ucc_geth_driver);
3980
3981 return ret;
3982 }
3983
3984 static void __exit ucc_geth_exit(void)
3985 {
3986 of_unregister_platform_driver(&ucc_geth_driver);
3987 }
3988
3989 module_init(ucc_geth_init);
3990 module_exit(ucc_geth_exit);
3991
3992 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3993 MODULE_DESCRIPTION(DRV_DESC);
3994 MODULE_VERSION(DRV_VERSION);
3995 MODULE_LICENSE("GPL");
Linux with added FPC-III support