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[media] rtl2832: claim copyright and module author
[linux/fpc-iii.git] / drivers / media / dvb-frontends / rtl2832.c
blobe5f7d7925c850d510263c49ff9c9079eaf53b959
1 /*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22 #include "rtl2832_priv.h"
23
24 #define REG_MASK(b) (BIT(b + 1) - 1)
25
26 static const struct rtl2832_reg_entry registers[] = {
27 [DVBT_SOFT_RST] = {0x101, 2, 2},
28 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
29 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
30 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
31 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
32 [DVBT_AD_EN_REG] = {0x008, 7, 7},
33 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
34 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
35 [DVBT_MGD_THD0] = {0x195, 7, 0},
36 [DVBT_MGD_THD1] = {0x196, 7, 0},
37 [DVBT_MGD_THD2] = {0x197, 7, 0},
38 [DVBT_MGD_THD3] = {0x198, 7, 0},
39 [DVBT_MGD_THD4] = {0x199, 7, 0},
40 [DVBT_MGD_THD5] = {0x19a, 7, 0},
41 [DVBT_MGD_THD6] = {0x19b, 7, 0},
42 [DVBT_MGD_THD7] = {0x19c, 7, 0},
43 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
44 [DVBT_AD_AV_REF] = {0x009, 6, 0},
45 [DVBT_REG_PI] = {0x00a, 2, 0},
46 [DVBT_PIP_ON] = {0x021, 3, 3},
47 [DVBT_SCALE1_B92] = {0x292, 7, 0},
48 [DVBT_SCALE1_B93] = {0x293, 7, 0},
49 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
50 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
51 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
52 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
53 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
54 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
55 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
56 [DVBT_KB_P1] = {0x164, 3, 1},
57 [DVBT_KB_P2] = {0x164, 6, 4},
58 [DVBT_KB_P3] = {0x165, 2, 0},
59 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
60 [DVBT_AD_AVI] = {0x009, 1, 0},
61 [DVBT_AD_AVQ] = {0x009, 3, 2},
62 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
63 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
64 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
65 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
66 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
67 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
68 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
69 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
70 [DVBT_SPEC_INV] = {0x115, 0, 0},
71 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
72 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
73 [DVBT_FSM_STAGE] = {0x351, 6, 3},
74 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
75 [DVBT_RX_HIER] = {0x33c, 6, 4},
76 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
77 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
78 [DVBT_GI_IDX] = {0x351, 1, 0},
79 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
80 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
81 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
82 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
83 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
84 [DVBT_DAGC_VAL] = {0x305, 7, 0},
85 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
86 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
87 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
88 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
89 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
90 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
91 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
92 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
93 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
94 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
95 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
96 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
97 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
98 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
99 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
100 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
101 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
102 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
103 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
104 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
105 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
106 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
107 [DVBT_VTOP1] = {0x106, 5, 0},
108 [DVBT_VTOP2] = {0x1c9, 5, 0},
109 [DVBT_VTOP3] = {0x1ca, 5, 0},
110 [DVBT_KRF1] = {0x1cb, 7, 0},
111 [DVBT_KRF2] = {0x107, 7, 0},
112 [DVBT_KRF3] = {0x1cd, 7, 0},
113 [DVBT_KRF4] = {0x1ce, 7, 0},
114 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
115 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
116 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
117 [DVBT_THD_UP1] = {0x1dd, 7, 0},
118 [DVBT_THD_DW1] = {0x1de, 7, 0},
119 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
120 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
121 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
122 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
123 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
124 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
125 [DVBT_ERR_DUR] = {0x17c, 0, 0},
126 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
127 [DVBT_ERR_LVL] = {0x17c, 2, 2},
128 [DVBT_VAL_LVL] = {0x17c, 3, 3},
129 [DVBT_SERIAL] = {0x17c, 4, 4},
130 [DVBT_SER_LSB] = {0x17c, 5, 5},
131 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
132 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
133 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
134 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
135 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
136 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
137 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
138 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
139 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
140 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
141 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
142 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
143 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
144 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
145 [DVBT_SM_PASS] = {0x193, 11, 0},
146 [DVBT_AD7_SETTING] = {0x011, 15, 0},
147 [DVBT_RSSI_R] = {0x301, 6, 0},
148 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
149 [DVBT_REG_MON] = {0x00d, 1, 0},
150 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
151 [DVBT_REG_GPE] = {0x00d, 7, 7},
152 [DVBT_REG_GPO] = {0x010, 0, 0},
153 [DVBT_REG_4MSEL] = {0x013, 0, 0},
154 };
155
156 /* Our regmap is bypassing I2C adapter lock, thus we do it! */
157 int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
158 const void *val, size_t val_count)
159 {
160 struct rtl2832_dev *dev = i2c_get_clientdata(client);
161 int ret;
162
163 i2c_lock_adapter(client->adapter);
164 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
165 i2c_unlock_adapter(client->adapter);
166 return ret;
167 }
168
169 int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
170 unsigned int mask, unsigned int val)
171 {
172 struct rtl2832_dev *dev = i2c_get_clientdata(client);
173 int ret;
174
175 i2c_lock_adapter(client->adapter);
176 ret = regmap_update_bits(dev->regmap, reg, mask, val);
177 i2c_unlock_adapter(client->adapter);
178 return ret;
179 }
180
181 int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg, void *val,
182 size_t val_count)
183 {
184 struct rtl2832_dev *dev = i2c_get_clientdata(client);
185 int ret;
186
187 i2c_lock_adapter(client->adapter);
188 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
189 i2c_unlock_adapter(client->adapter);
190 return ret;
191 }
192
193 static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
194 {
195 struct i2c_client *client = dev->client;
196 int ret, i;
197 u16 reg_start_addr;
198 u8 msb, lsb, reading[4], len;
199 u32 reading_tmp, mask;
200
201 reg_start_addr = registers[reg].start_address;
202 msb = registers[reg].msb;
203 lsb = registers[reg].lsb;
204 len = (msb >> 3) + 1;
205 mask = REG_MASK(msb - lsb);
206
207 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
208 if (ret)
209 goto err;
210
211 reading_tmp = 0;
212 for (i = 0; i < len; i++)
213 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
214
215 *val = (reading_tmp >> lsb) & mask;
216
217 return 0;
218 err:
219 dev_dbg(&client->dev, "failed=%d\n", ret);
220 return ret;
221 }
222
223 static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
224 {
225 struct i2c_client *client = dev->client;
226 int ret, i;
227 u16 reg_start_addr;
228 u8 msb, lsb, reading[4], writing[4], len;
229 u32 reading_tmp, writing_tmp, mask;
230
231 reg_start_addr = registers[reg].start_address;
232 msb = registers[reg].msb;
233 lsb = registers[reg].lsb;
234 len = (msb >> 3) + 1;
235 mask = REG_MASK(msb - lsb);
236
237 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
238 if (ret)
239 goto err;
240
241 reading_tmp = 0;
242 for (i = 0; i < len; i++)
243 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
244
245 writing_tmp = reading_tmp & ~(mask << lsb);
246 writing_tmp |= ((val & mask) << lsb);
247
248 for (i = 0; i < len; i++)
249 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
250
251 ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
252 if (ret)
253 goto err;
254
255 return 0;
256 err:
257 dev_dbg(&client->dev, "failed=%d\n", ret);
258 return ret;
259 }
260
261 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
262 {
263 struct rtl2832_dev *dev = fe->demodulator_priv;
264 struct i2c_client *client = dev->client;
265 int ret;
266 u64 pset_iffreq;
267 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
268
269 /*
270 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
271 * / CrystalFreqHz)
272 */
273 pset_iffreq = if_freq % dev->pdata->clk;
274 pset_iffreq *= 0x400000;
275 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
276 pset_iffreq = -pset_iffreq;
277 pset_iffreq = pset_iffreq & 0x3fffff;
278 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
279 if_freq, (unsigned)pset_iffreq);
280
281 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
282 if (ret)
283 goto err;
284
285 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
286 if (ret)
287 goto err;
288
289 return 0;
290 err:
291 dev_dbg(&client->dev, "failed=%d\n", ret);
292 return ret;
293 }
294
295 static int rtl2832_init(struct dvb_frontend *fe)
296 {
297 struct rtl2832_dev *dev = fe->demodulator_priv;
298 struct i2c_client *client = dev->client;
299 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
300 const struct rtl2832_reg_value *init;
301 int i, ret, len;
302 /* initialization values for the demodulator registers */
303 struct rtl2832_reg_value rtl2832_initial_regs[] = {
304 {DVBT_AD_EN_REG, 0x1},
305 {DVBT_AD_EN_REG1, 0x1},
306 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
307 {DVBT_MGD_THD0, 0x10},
308 {DVBT_MGD_THD1, 0x20},
309 {DVBT_MGD_THD2, 0x20},
310 {DVBT_MGD_THD3, 0x40},
311 {DVBT_MGD_THD4, 0x22},
312 {DVBT_MGD_THD5, 0x32},
313 {DVBT_MGD_THD6, 0x37},
314 {DVBT_MGD_THD7, 0x39},
315 {DVBT_EN_BK_TRK, 0x0},
316 {DVBT_EN_CACQ_NOTCH, 0x0},
317 {DVBT_AD_AV_REF, 0x2a},
318 {DVBT_REG_PI, 0x6},
319 {DVBT_PIP_ON, 0x0},
320 {DVBT_CDIV_PH0, 0x8},
321 {DVBT_CDIV_PH1, 0x8},
322 {DVBT_SCALE1_B92, 0x4},
323 {DVBT_SCALE1_B93, 0xb0},
324 {DVBT_SCALE1_BA7, 0x78},
325 {DVBT_SCALE1_BA9, 0x28},
326 {DVBT_SCALE1_BAA, 0x59},
327 {DVBT_SCALE1_BAB, 0x83},
328 {DVBT_SCALE1_BAC, 0xd4},
329 {DVBT_SCALE1_BB0, 0x65},
330 {DVBT_SCALE1_BB1, 0x43},
331 {DVBT_KB_P1, 0x1},
332 {DVBT_KB_P2, 0x4},
333 {DVBT_KB_P3, 0x7},
334 {DVBT_K1_CR_STEP12, 0xa},
335 {DVBT_REG_GPE, 0x1},
336 {DVBT_SERIAL, 0x0},
337 {DVBT_CDIV_PH0, 0x9},
338 {DVBT_CDIV_PH1, 0x9},
339 {DVBT_MPEG_IO_OPT_2_2, 0x0},
340 {DVBT_MPEG_IO_OPT_1_0, 0x0},
341 {DVBT_TRK_KS_P2, 0x4},
342 {DVBT_TRK_KS_I2, 0x7},
343 {DVBT_TR_THD_SET2, 0x6},
344 {DVBT_TRK_KC_I2, 0x5},
345 {DVBT_CR_THD_SET2, 0x1},
346 };
347
348 dev_dbg(&client->dev, "\n");
349
350 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
351 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
352 rtl2832_initial_regs[i].value);
353 if (ret)
354 goto err;
355 }
356
357 /* load tuner specific settings */
358 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
359 dev->pdata->tuner);
360 switch (dev->pdata->tuner) {
361 case RTL2832_TUNER_FC0012:
362 case RTL2832_TUNER_FC0013:
363 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
364 init = rtl2832_tuner_init_fc0012;
365 break;
366 case RTL2832_TUNER_TUA9001:
367 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
368 init = rtl2832_tuner_init_tua9001;
369 break;
370 case RTL2832_TUNER_E4000:
371 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
372 init = rtl2832_tuner_init_e4000;
373 break;
374 case RTL2832_TUNER_R820T:
375 case RTL2832_TUNER_R828D:
376 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
377 init = rtl2832_tuner_init_r820t;
378 break;
379 default:
380 ret = -EINVAL;
381 goto err;
382 }
383
384 for (i = 0; i < len; i++) {
385 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
386 if (ret)
387 goto err;
388 }
389
390 /* init stats here in order signal app which stats are supported */
391 c->strength.len = 1;
392 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
393 c->cnr.len = 1;
394 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
395 c->post_bit_error.len = 1;
396 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
397 c->post_bit_count.len = 1;
398 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
399 /* start statistics polling */
400 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
401 dev->sleeping = false;
402
403 return 0;
404 err:
405 dev_dbg(&client->dev, "failed=%d\n", ret);
406 return ret;
407 }
408
409 static int rtl2832_sleep(struct dvb_frontend *fe)
410 {
411 struct rtl2832_dev *dev = fe->demodulator_priv;
412 struct i2c_client *client = dev->client;
413
414 dev_dbg(&client->dev, "\n");
415 dev->sleeping = true;
416 /* stop statistics polling */
417 cancel_delayed_work_sync(&dev->stat_work);
418 dev->fe_status = 0;
419 return 0;
420 }
421
422 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
423 struct dvb_frontend_tune_settings *s)
424 {
425 struct rtl2832_dev *dev = fe->demodulator_priv;
426 struct i2c_client *client = dev->client;
427
428 dev_dbg(&client->dev, "\n");
429 s->min_delay_ms = 1000;
430 s->step_size = fe->ops.info.frequency_stepsize * 2;
431 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
432 return 0;
433 }
434
435 static int rtl2832_set_frontend(struct dvb_frontend *fe)
436 {
437 struct rtl2832_dev *dev = fe->demodulator_priv;
438 struct i2c_client *client = dev->client;
439 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
440 int ret, i, j;
441 u64 bw_mode, num, num2;
442 u32 resamp_ratio, cfreq_off_ratio;
443 static u8 bw_params[3][32] = {
444 /* 6 MHz bandwidth */
445 {
446 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
447 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
448 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
449 0x19, 0xe0,
450 },
451
452 /* 7 MHz bandwidth */
453 {
454 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
455 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
456 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
457 0x19, 0x10,
458 },
459
460 /* 8 MHz bandwidth */
461 {
462 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
463 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
464 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
465 0x19, 0xe0,
466 },
467 };
468
469 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
470 c->frequency, c->bandwidth_hz, c->inversion);
471
472 /* program tuner */
473 if (fe->ops.tuner_ops.set_params)
474 fe->ops.tuner_ops.set_params(fe);
475
476 /* PIP mode related */
477 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
478 if (ret)
479 goto err;
480
481 /* If the frontend has get_if_frequency(), use it */
482 if (fe->ops.tuner_ops.get_if_frequency) {
483 u32 if_freq;
484
485 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
486 if (ret)
487 goto err;
488
489 ret = rtl2832_set_if(fe, if_freq);
490 if (ret)
491 goto err;
492 }
493
494 switch (c->bandwidth_hz) {
495 case 6000000:
496 i = 0;
497 bw_mode = 48000000;
498 break;
499 case 7000000:
500 i = 1;
501 bw_mode = 56000000;
502 break;
503 case 8000000:
504 i = 2;
505 bw_mode = 64000000;
506 break;
507 default:
508 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
509 c->bandwidth_hz);
510 ret = -EINVAL;
511 goto err;
512 }
513
514 for (j = 0; j < sizeof(bw_params[0]); j++) {
515 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
516 if (ret)
517 goto err;
518 }
519
520 /* calculate and set resample ratio
521 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
522 * / ConstWithBandwidthMode)
523 */
524 num = dev->pdata->clk * 7;
525 num *= 0x400000;
526 num = div_u64(num, bw_mode);
527 resamp_ratio = num & 0x3ffffff;
528 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
529 if (ret)
530 goto err;
531
532 /* calculate and set cfreq off ratio
533 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
534 * / (CrystalFreqHz * 7))
535 */
536 num = bw_mode << 20;
537 num2 = dev->pdata->clk * 7;
538 num = div_u64(num, num2);
539 num = -num;
540 cfreq_off_ratio = num & 0xfffff;
541 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
542 if (ret)
543 goto err;
544
545 /* soft reset */
546 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
547 if (ret)
548 goto err;
549
550 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
551 if (ret)
552 goto err;
553
554 return 0;
555 err:
556 dev_dbg(&client->dev, "failed=%d\n", ret);
557 return ret;
558 }
559
560 static int rtl2832_get_frontend(struct dvb_frontend *fe)
561 {
562 struct rtl2832_dev *dev = fe->demodulator_priv;
563 struct i2c_client *client = dev->client;
564 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
565 int ret;
566 u8 buf[3];
567
568 if (dev->sleeping)
569 return 0;
570
571 ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
572 if (ret)
573 goto err;
574
575 ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
576 if (ret)
577 goto err;
578
579 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
580
581 switch ((buf[0] >> 2) & 3) {
582 case 0:
583 c->modulation = QPSK;
584 break;
585 case 1:
586 c->modulation = QAM_16;
587 break;
588 case 2:
589 c->modulation = QAM_64;
590 break;
591 }
592
593 switch ((buf[2] >> 2) & 1) {
594 case 0:
595 c->transmission_mode = TRANSMISSION_MODE_2K;
596 break;
597 case 1:
598 c->transmission_mode = TRANSMISSION_MODE_8K;
599 }
600
601 switch ((buf[2] >> 0) & 3) {
602 case 0:
603 c->guard_interval = GUARD_INTERVAL_1_32;
604 break;
605 case 1:
606 c->guard_interval = GUARD_INTERVAL_1_16;
607 break;
608 case 2:
609 c->guard_interval = GUARD_INTERVAL_1_8;
610 break;
611 case 3:
612 c->guard_interval = GUARD_INTERVAL_1_4;
613 break;
614 }
615
616 switch ((buf[0] >> 4) & 7) {
617 case 0:
618 c->hierarchy = HIERARCHY_NONE;
619 break;
620 case 1:
621 c->hierarchy = HIERARCHY_1;
622 break;
623 case 2:
624 c->hierarchy = HIERARCHY_2;
625 break;
626 case 3:
627 c->hierarchy = HIERARCHY_4;
628 break;
629 }
630
631 switch ((buf[1] >> 3) & 7) {
632 case 0:
633 c->code_rate_HP = FEC_1_2;
634 break;
635 case 1:
636 c->code_rate_HP = FEC_2_3;
637 break;
638 case 2:
639 c->code_rate_HP = FEC_3_4;
640 break;
641 case 3:
642 c->code_rate_HP = FEC_5_6;
643 break;
644 case 4:
645 c->code_rate_HP = FEC_7_8;
646 break;
647 }
648
649 switch ((buf[1] >> 0) & 7) {
650 case 0:
651 c->code_rate_LP = FEC_1_2;
652 break;
653 case 1:
654 c->code_rate_LP = FEC_2_3;
655 break;
656 case 2:
657 c->code_rate_LP = FEC_3_4;
658 break;
659 case 3:
660 c->code_rate_LP = FEC_5_6;
661 break;
662 case 4:
663 c->code_rate_LP = FEC_7_8;
664 break;
665 }
666
667 return 0;
668 err:
669 dev_dbg(&client->dev, "failed=%d\n", ret);
670 return ret;
671 }
672
673 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
674 {
675 struct rtl2832_dev *dev = fe->demodulator_priv;
676 struct i2c_client *client = dev->client;
677 int ret;
678 u32 tmp;
679
680 dev_dbg(&client->dev, "\n");
681
682 *status = 0;
683 if (dev->sleeping)
684 return 0;
685
686 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
687 if (ret)
688 goto err;
689
690 if (tmp == 11) {
691 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
692 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
693 } else if (tmp == 10) {
694 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
695 FE_HAS_VITERBI;
696 }
697
698 dev->fe_status = *status;
699 return 0;
700 err:
701 dev_dbg(&client->dev, "failed=%d\n", ret);
702 return ret;
703 }
704
705 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
706 {
707 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
708
709 /* report SNR in resolution of 0.1 dB */
710 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
711 *snr = div_s64(c->cnr.stat[0].svalue, 100);
712 else
713 *snr = 0;
714
715 return 0;
716 }
717
718 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
719 {
720 struct rtl2832_dev *dev = fe->demodulator_priv;
721
722 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
723 dev->post_bit_error_prev = dev->post_bit_error;
724
725 return 0;
726 }
727
728 static void rtl2832_stat_work(struct work_struct *work)
729 {
730 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
731 struct i2c_client *client = dev->client;
732 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
733 int ret, tmp;
734 u8 u8tmp, buf[2];
735 u16 u16tmp;
736
737 dev_dbg(&client->dev, "\n");
738
739 /* signal strength */
740 if (dev->fe_status & FE_HAS_SIGNAL) {
741 /* read digital AGC */
742 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
743 if (ret)
744 goto err;
745
746 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
747
748 u8tmp = ~u8tmp;
749 u16tmp = u8tmp << 8 | u8tmp << 0;
750
751 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
752 c->strength.stat[0].uvalue = u16tmp;
753 } else {
754 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
755 }
756
757 /* CNR */
758 if (dev->fe_status & FE_HAS_VITERBI) {
759 unsigned hierarchy, constellation;
760 #define CONSTELLATION_NUM 3
761 #define HIERARCHY_NUM 4
762 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
763 {85387325, 85387325, 85387325, 85387325},
764 {86676178, 86676178, 87167949, 87795660},
765 {87659938, 87659938, 87885178, 88241743},
766 };
767
768 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
769 if (ret)
770 goto err;
771
772 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
773 if (constellation > CONSTELLATION_NUM - 1)
774 goto err_schedule_delayed_work;
775
776 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
777 if (hierarchy > HIERARCHY_NUM - 1)
778 goto err_schedule_delayed_work;
779
780 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
781 if (ret)
782 goto err;
783
784 u16tmp = buf[0] << 8 | buf[1] << 0;
785 if (u16tmp)
786 tmp = (constant[constellation][hierarchy] -
787 intlog10(u16tmp)) / ((1 << 24) / 10000);
788 else
789 tmp = 0;
790
791 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
792
793 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
794 c->cnr.stat[0].svalue = tmp;
795 } else {
796 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
797 }
798
799 /* BER */
800 if (dev->fe_status & FE_HAS_LOCK) {
801 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
802 if (ret)
803 goto err;
804
805 u16tmp = buf[0] << 8 | buf[1] << 0;
806 dev->post_bit_error += u16tmp;
807 dev->post_bit_count += 1000000;
808
809 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
810
811 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
812 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
813 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
814 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
815 } else {
816 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
817 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
818 }
819
820 err_schedule_delayed_work:
821 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
822 return;
823 err:
824 dev_dbg(&client->dev, "failed=%d\n", ret);
825 }
826
827 /*
828 * I2C gate/mux/repeater logic
829 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
830 * adapter lock is already taken by tuner driver.
831 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
832 * is delayed here a little bit in order to see if there is sequence of I2C
833 * messages sent to same I2C bus.
834 */
835 static void rtl2832_i2c_gate_work(struct work_struct *work)
836 {
837 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
838 struct i2c_client *client = dev->client;
839 int ret;
840
841 /* close gate */
842 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
843 if (ret)
844 goto err;
845
846 return;
847 err:
848 dev_dbg(&client->dev, "failed=%d\n", ret);
849 }
850
851 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
852 {
853 struct rtl2832_dev *dev = mux_priv;
854 struct i2c_client *client = dev->client;
855 int ret;
856
857 /* terminate possible gate closing */
858 cancel_delayed_work(&dev->i2c_gate_work);
859
860 /*
861 * chan_id 1 is muxed adapter demod provides and chan_id 0 is demod
862 * itself. We need open gate when request is for chan_id 1. On that case
863 * I2C adapter lock is already taken and due to that we will use
864 * regmap_update_bits() which does not lock again I2C adapter.
865 */
866 if (chan_id == 1)
867 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
868 else
869 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
870 if (ret)
871 goto err;
872
873 return 0;
874 err:
875 dev_dbg(&client->dev, "failed=%d\n", ret);
876 return ret;
877 }
878
879 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
880 u32 chan_id)
881 {
882 struct rtl2832_dev *dev = mux_priv;
883
884 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
885 return 0;
886 }
887
888 static struct dvb_frontend_ops rtl2832_ops = {
889 .delsys = { SYS_DVBT },
890 .info = {
891 .name = "Realtek RTL2832 (DVB-T)",
892 .frequency_min = 174000000,
893 .frequency_max = 862000000,
894 .frequency_stepsize = 166667,
895 .caps = FE_CAN_FEC_1_2 |
896 FE_CAN_FEC_2_3 |
897 FE_CAN_FEC_3_4 |
898 FE_CAN_FEC_5_6 |
899 FE_CAN_FEC_7_8 |
900 FE_CAN_FEC_AUTO |
901 FE_CAN_QPSK |
902 FE_CAN_QAM_16 |
903 FE_CAN_QAM_64 |
904 FE_CAN_QAM_AUTO |
905 FE_CAN_TRANSMISSION_MODE_AUTO |
906 FE_CAN_GUARD_INTERVAL_AUTO |
907 FE_CAN_HIERARCHY_AUTO |
908 FE_CAN_RECOVER |
909 FE_CAN_MUTE_TS
910 },
911
912 .init = rtl2832_init,
913 .sleep = rtl2832_sleep,
914
915 .get_tune_settings = rtl2832_get_tune_settings,
916
917 .set_frontend = rtl2832_set_frontend,
918 .get_frontend = rtl2832_get_frontend,
919
920 .read_status = rtl2832_read_status,
921 .read_snr = rtl2832_read_snr,
922 .read_ber = rtl2832_read_ber,
923 };
924
925 static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
926 {
927 switch (reg) {
928 case 0x305:
929 case 0x33c:
930 case 0x34e:
931 case 0x351:
932 case 0x40c ... 0x40d:
933 return true;
934 default:
935 break;
936 }
937
938 return false;
939 }
940
941 /*
942 * We implement own I2C access routines for regmap in order to get manual access
943 * to I2C adapter lock, which is needed for I2C mux adapter.
944 */
945 static int rtl2832_regmap_read(void *context, const void *reg_buf,
946 size_t reg_size, void *val_buf, size_t val_size)
947 {
948 struct i2c_client *client = context;
949 int ret;
950 struct i2c_msg msg[2] = {
951 {
952 .addr = client->addr,
953 .flags = 0,
954 .len = reg_size,
955 .buf = (u8 *)reg_buf,
956 }, {
957 .addr = client->addr,
958 .flags = I2C_M_RD,
959 .len = val_size,
960 .buf = val_buf,
961 }
962 };
963
964 ret = __i2c_transfer(client->adapter, msg, 2);
965 if (ret != 2) {
966 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
967 if (ret >= 0)
968 ret = -EREMOTEIO;
969 return ret;
970 }
971 return 0;
972 }
973
974 static int rtl2832_regmap_write(void *context, const void *data, size_t count)
975 {
976 struct i2c_client *client = context;
977 int ret;
978 struct i2c_msg msg[1] = {
979 {
980 .addr = client->addr,
981 .flags = 0,
982 .len = count,
983 .buf = (u8 *)data,
984 }
985 };
986
987 ret = __i2c_transfer(client->adapter, msg, 1);
988 if (ret != 1) {
989 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
990 if (ret >= 0)
991 ret = -EREMOTEIO;
992 return ret;
993 }
994 return 0;
995 }
996
997 static int rtl2832_regmap_gather_write(void *context, const void *reg,
998 size_t reg_len, const void *val,
999 size_t val_len)
1000 {
1001 struct i2c_client *client = context;
1002 int ret;
1003 u8 buf[256];
1004 struct i2c_msg msg[1] = {
1005 {
1006 .addr = client->addr,
1007 .flags = 0,
1008 .len = 1 + val_len,
1009 .buf = buf,
1010 }
1011 };
1012
1013 buf[0] = *(u8 const *)reg;
1014 memcpy(&buf[1], val, val_len);
1015
1016 ret = __i2c_transfer(client->adapter, msg, 1);
1017 if (ret != 1) {
1018 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1019 if (ret >= 0)
1020 ret = -EREMOTEIO;
1021 return ret;
1022 }
1023 return 0;
1024 }
1025
1026 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1027 {
1028 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1029
1030 dev_dbg(&client->dev, "\n");
1031 return &dev->fe;
1032 }
1033
1034 static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
1035 {
1036 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1037
1038 dev_dbg(&client->dev, "\n");
1039 return dev->i2c_adapter_tuner;
1040 }
1041
1042 static int rtl2832_enable_slave_ts(struct i2c_client *client)
1043 {
1044 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1045 int ret;
1046
1047 dev_dbg(&client->dev, "\n");
1048
1049 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
1050 if (ret)
1051 goto err;
1052
1053 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1054 if (ret)
1055 goto err;
1056
1057 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
1058 if (ret)
1059 goto err;
1060
1061 ret = rtl2832_bulk_write(client, 0x022, "\x01", 1);
1062 if (ret)
1063 goto err;
1064
1065 ret = rtl2832_bulk_write(client, 0x026, "\x1f", 1);
1066 if (ret)
1067 goto err;
1068
1069 ret = rtl2832_bulk_write(client, 0x027, "\xff", 1);
1070 if (ret)
1071 goto err;
1072
1073 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
1074 if (ret)
1075 goto err;
1076
1077 /* soft reset */
1078 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1079 if (ret)
1080 goto err;
1081
1082 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1083 if (ret)
1084 goto err;
1085
1086 return 0;
1087 err:
1088 dev_dbg(&client->dev, "failed=%d\n", ret);
1089 return ret;
1090 }
1091
1092 static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1093 {
1094 struct rtl2832_dev *dev = fe->demodulator_priv;
1095 struct i2c_client *client = dev->client;
1096 int ret;
1097 u8 u8tmp;
1098
1099 dev_dbg(&client->dev, "onoff=%d\n", onoff);
1100
1101 /* enable / disable PID filter */
1102 if (onoff)
1103 u8tmp = 0x80;
1104 else
1105 u8tmp = 0x00;
1106
1107 ret = rtl2832_update_bits(client, 0x061, 0xc0, u8tmp);
1108 if (ret)
1109 goto err;
1110
1111 return 0;
1112 err:
1113 dev_dbg(&client->dev, "failed=%d\n", ret);
1114 return ret;
1115 }
1116
1117 static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
1118 int onoff)
1119 {
1120 struct rtl2832_dev *dev = fe->demodulator_priv;
1121 struct i2c_client *client = dev->client;
1122 int ret;
1123 u8 buf[4];
1124
1125 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1126 index, pid, onoff);
1127
1128 /* skip invalid PIDs (0x2000) */
1129 if (pid > 0x1fff || index > 32)
1130 return 0;
1131
1132 if (onoff)
1133 set_bit(index, &dev->filters);
1134 else
1135 clear_bit(index, &dev->filters);
1136
1137 /* enable / disable PIDs */
1138 buf[0] = (dev->filters >> 0) & 0xff;
1139 buf[1] = (dev->filters >> 8) & 0xff;
1140 buf[2] = (dev->filters >> 16) & 0xff;
1141 buf[3] = (dev->filters >> 24) & 0xff;
1142 ret = rtl2832_bulk_write(client, 0x062, buf, 4);
1143 if (ret)
1144 goto err;
1145
1146 /* add PID */
1147 buf[0] = (pid >> 8) & 0xff;
1148 buf[1] = (pid >> 0) & 0xff;
1149 ret = rtl2832_bulk_write(client, 0x066 + 2 * index, buf, 2);
1150 if (ret)
1151 goto err;
1152
1153 return 0;
1154 err:
1155 dev_dbg(&client->dev, "failed=%d\n", ret);
1156 return ret;
1157 }
1158
1159 static int rtl2832_probe(struct i2c_client *client,
1160 const struct i2c_device_id *id)
1161 {
1162 struct rtl2832_platform_data *pdata = client->dev.platform_data;
1163 struct i2c_adapter *i2c = client->adapter;
1164 struct rtl2832_dev *dev;
1165 int ret;
1166 u8 tmp;
1167 static const struct regmap_bus regmap_bus = {
1168 .read = rtl2832_regmap_read,
1169 .write = rtl2832_regmap_write,
1170 .gather_write = rtl2832_regmap_gather_write,
1171 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1172 };
1173 static const struct regmap_range_cfg regmap_range_cfg[] = {
1174 {
1175 .selector_reg = 0x00,
1176 .selector_mask = 0xff,
1177 .selector_shift = 0,
1178 .window_start = 0,
1179 .window_len = 0x100,
1180 .range_min = 0 * 0x100,
1181 .range_max = 5 * 0x100,
1182 },
1183 };
1184 static const struct regmap_config regmap_config = {
1185 .reg_bits = 8,
1186 .val_bits = 8,
1187 .volatile_reg = rtl2832_volatile_reg,
1188 .max_register = 5 * 0x100,
1189 .ranges = regmap_range_cfg,
1190 .num_ranges = ARRAY_SIZE(regmap_range_cfg),
1191 .cache_type = REGCACHE_RBTREE,
1192 };
1193
1194 dev_dbg(&client->dev, "\n");
1195
1196 /* allocate memory for the internal state */
1197 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1198 if (dev == NULL) {
1199 ret = -ENOMEM;
1200 goto err;
1201 }
1202
1203 /* setup the state */
1204 i2c_set_clientdata(client, dev);
1205 dev->client = client;
1206 dev->pdata = client->dev.platform_data;
1207 dev->sleeping = true;
1208 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1209 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
1210 /* create regmap */
1211 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
1212 &regmap_config);
1213 if (IS_ERR(dev->regmap)) {
1214 ret = PTR_ERR(dev->regmap);
1215 goto err_kfree;
1216 }
1217 /* create muxed i2c adapter for demod itself */
1218 dev->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, dev, 0, 0, 0,
1219 rtl2832_select, NULL);
1220 if (dev->i2c_adapter == NULL) {
1221 ret = -ENODEV;
1222 goto err_regmap_exit;
1223 }
1224
1225 /* check if the demod is there */
1226 ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
1227 if (ret)
1228 goto err_i2c_del_mux_adapter;
1229
1230 /* create muxed i2c adapter for demod tuner bus */
1231 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
1232 0, 1, 0, rtl2832_select, rtl2832_deselect);
1233 if (dev->i2c_adapter_tuner == NULL) {
1234 ret = -ENODEV;
1235 goto err_i2c_del_mux_adapter;
1236 }
1237
1238 /* create dvb_frontend */
1239 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1240 dev->fe.demodulator_priv = dev;
1241
1242 /* setup callbacks */
1243 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1244 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
1245 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
1246 pdata->pid_filter = rtl2832_pid_filter;
1247 pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
1248 pdata->bulk_read = rtl2832_bulk_read;
1249 pdata->bulk_write = rtl2832_bulk_write;
1250 pdata->update_bits = rtl2832_update_bits;
1251
1252 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1253 return 0;
1254 err_i2c_del_mux_adapter:
1255 i2c_del_mux_adapter(dev->i2c_adapter);
1256 err_regmap_exit:
1257 regmap_exit(dev->regmap);
1258 err_kfree:
1259 kfree(dev);
1260 err:
1261 dev_dbg(&client->dev, "failed=%d\n", ret);
1262 return ret;
1263 }
1264
1265 static int rtl2832_remove(struct i2c_client *client)
1266 {
1267 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1268
1269 dev_dbg(&client->dev, "\n");
1270
1271 cancel_delayed_work_sync(&dev->i2c_gate_work);
1272
1273 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
1274
1275 i2c_del_mux_adapter(dev->i2c_adapter);
1276
1277 regmap_exit(dev->regmap);
1278
1279 kfree(dev);
1280
1281 return 0;
1282 }
1283
1284 static const struct i2c_device_id rtl2832_id_table[] = {
1285 {"rtl2832", 0},
1286 {}
1287 };
1288 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1289
1290 static struct i2c_driver rtl2832_driver = {
1291 .driver = {
1292 .owner = THIS_MODULE,
1293 .name = "rtl2832",
1294 },
1295 .probe = rtl2832_probe,
1296 .remove = rtl2832_remove,
1297 .id_table = rtl2832_id_table,
1298 };
1299
1300 module_i2c_driver(rtl2832_driver);
1301
1302 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1303 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1304 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1305 MODULE_LICENSE("GPL");
Linux with added FPC-III support