| blob | 2cf5ef3fc50dbfdc7207a1a0399682716ce8cf77 |
1 /*
2 * Low-level SLB routines
3 *
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
5 *
6 * Based on earlier C version:
7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
8 * Copyright (c) 2001 Dave Engebretsen
9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
17 #include <asm/processor.h>
18 #include <asm/ppc_asm.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cputable.h>
21 #include <asm/page.h>
22 #include <asm/mmu.h>
23 #include <asm/pgtable.h>
24 #include <asm/firmware.h>
26 /*
27 * This macro generates asm code to compute the VSID scramble
28 * function. Used in slb_allocate() and do_stab_bolted. The function
29 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
30 *
31 * rt = register containing the proto-VSID and into which the
32 * VSID will be stored
33 * rx = scratch register (clobbered)
34 * rf = flags
35 *
36 * - rt and rx must be different registers
37 * - The answer will end up in the low VSID_BITS bits of rt. The higher
38 * bits may contain other garbage, so you may need to mask the
39 * result.
40 */
41 #define ASM_VSID_SCRAMBLE(rt, rx, rf, size) \
42 lis rx,VSID_MULTIPLIER_##size@h; \
43 ori rx,rx,VSID_MULTIPLIER_##size@l; \
44 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
45 /* \
46 * powermac get slb fault before feature fixup, so make 65 bit part \
47 * the default part of feature fixup \
48 */ \
49 BEGIN_MMU_FTR_SECTION \
50 srdi rx,rt,VSID_BITS_65_##size; \
51 clrldi rt,rt,(64-VSID_BITS_65_##size); \
52 add rt,rt,rx; \
53 addi rx,rt,1; \
54 srdi rx,rx,VSID_BITS_65_##size; \
55 add rt,rt,rx; \
56 rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_65_##size)); \
57 MMU_FTR_SECTION_ELSE \
58 srdi rx,rt,VSID_BITS_##size; \
59 clrldi rt,rt,(64-VSID_BITS_##size); \
60 add rt,rt,rx; /* add high and low bits */ \
61 addi rx,rt,1; \
62 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
63 add rt,rt,rx; \
64 rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_##size)); \
65 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_68_BIT_VA)
68 /* void slb_allocate(unsigned long ea);
69 *
70 * Create an SLB entry for the given EA (user or kernel).
71 * r3 = faulting address, r13 = PACA
72 * r9, r10, r11 are clobbered by this function
73 * r3 is preserved.
74 * No other registers are examined or changed.
75 */
76 _GLOBAL(slb_allocate)
77 /*
78 * check for bad kernel/user address
79 * (ea & ~REGION_MASK) >= PGTABLE_RANGE
80 */
81 rldicr. r9,r3,4,(63 - H_PGTABLE_EADDR_SIZE - 4)
82 bne- 8f
84 srdi r9,r3,60 /* get region */
85 srdi r10,r3,SID_SHIFT /* get esid */
86 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
88 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
89 blt cr7,0f /* user or kernel? */
91 /* Check if hitting the linear mapping or some other kernel space
92 */
93 bne cr7,1f
95 /* Linear mapping encoding bits, the "li" instruction below will
96 * be patched by the kernel at boot
97 */
98 .globl slb_miss_kernel_load_linear
99 slb_miss_kernel_load_linear:
100 li r11,0
101 /*
102 * context = (ea >> 60) - (0xc - 1)
103 * r9 = region id.
104 */
105 subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
107 BEGIN_FTR_SECTION
108 b .Lslb_finish_load
109 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
110 b .Lslb_finish_load_1T
112 1:
113 #ifdef CONFIG_SPARSEMEM_VMEMMAP
114 cmpldi cr0,r9,0xf
115 bne 1f
116 /* Check virtual memmap region. To be patched at kernel boot */
117 .globl slb_miss_kernel_load_vmemmap
118 slb_miss_kernel_load_vmemmap:
119 li r11,0
120 b 6f
121 1:
122 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
124 /*
125 * r10 contains the ESID, which is the original faulting EA shifted
126 * right by 28 bits. We need to compare that with (H_VMALLOC_END >> 28)
127 * which is 0xd00038000. That can't be used as an immediate, even if we
128 * ignored the 0xd, so we have to load it into a register, and we only
129 * have one register free. So we must load all of (H_VMALLOC_END >> 28)
130 * into a register and compare ESID against that.
131 */
132 lis r11,(H_VMALLOC_END >> 32)@h // r11 = 0xffffffffd0000000
133 ori r11,r11,(H_VMALLOC_END >> 32)@l // r11 = 0xffffffffd0003800
134 // Rotate left 4, then mask with 0xffffffff0
135 rldic r11,r11,4,28 // r11 = 0xd00038000
136 cmpld r10,r11 // if r10 >= r11
137 bge 5f // goto io_mapping
139 /*
140 * vmalloc mapping gets the encoding from the PACA as the mapping
141 * can be demoted from 64K -> 4K dynamically on some machines.
142 */
143 lhz r11,PACAVMALLOCSLLP(r13)
144 b 6f
145 5:
146 /* IO mapping */
147 .globl slb_miss_kernel_load_io
148 slb_miss_kernel_load_io:
149 li r11,0
150 6:
151 /*
152 * context = (ea >> 60) - (0xc - 1)
153 * r9 = region id.
154 */
155 subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
157 BEGIN_FTR_SECTION
158 b .Lslb_finish_load
159 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
160 b .Lslb_finish_load_1T
162 0: /*
163 * For userspace addresses, make sure this is region 0.
164 */
165 cmpdi r9, 0
166 bne- 8f
167 /*
168 * user space make sure we are within the allowed limit
169 */
170 ld r11,PACA_SLB_ADDR_LIMIT(r13)
171 cmpld r3,r11
172 bge- 8f
174 /* when using slices, we extract the psize off the slice bitmaps
175 * and then we need to get the sllp encoding off the mmu_psize_defs
176 * array.
177 *
178 * XXX This is a bit inefficient especially for the normal case,
179 * so we should try to implement a fast path for the standard page
180 * size using the old sllp value so we avoid the array. We cannot
181 * really do dynamic patching unfortunately as processes might flip
182 * between 4k and 64k standard page size
183 */
184 #ifdef CONFIG_PPC_MM_SLICES
185 /* r10 have esid */
186 cmpldi r10,16
187 /* below SLICE_LOW_TOP */
188 blt 5f
189 /*
190 * Handle hpsizes,
191 * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
192 */
193 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
194 addi r9,r11,PACAHIGHSLICEPSIZE
195 lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
196 /* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
197 rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
198 b 6f
200 5:
201 /*
202 * Handle lpsizes
203 * r9 is get_paca()->context.low_slices_psize, r11 is index
204 */
205 ld r9,PACALOWSLICESPSIZE(r13)
206 mr r11,r10
207 6:
208 sldi r11,r11,2 /* index * 4 */
209 /* Extract the psize and multiply to get an array offset */
210 srd r9,r9,r11
211 andi. r9,r9,0xf
212 mulli r9,r9,MMUPSIZEDEFSIZE
214 /* Now get to the array and obtain the sllp
215 */
216 ld r11,PACATOC(r13)
217 ld r11,mmu_psize_defs@got(r11)
218 add r11,r11,r9
219 ld r11,MMUPSIZESLLP(r11)
220 ori r11,r11,SLB_VSID_USER
221 #else
222 /* paca context sllp already contains the SLB_VSID_USER bits */
223 lhz r11,PACACONTEXTSLLP(r13)
224 #endif /* CONFIG_PPC_MM_SLICES */
226 ld r9,PACACONTEXTID(r13)
227 BEGIN_FTR_SECTION
228 cmpldi r10,0x1000
229 bge .Lslb_finish_load_1T
230 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
231 b .Lslb_finish_load
233 8: /* invalid EA - return an error indication */
234 crset 4*cr0+eq /* indicate failure */
235 blr
237 /*
238 * Finish loading of an SLB entry and return
239 *
240 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
241 */
242 .Lslb_finish_load:
243 rldimi r10,r9,ESID_BITS,0
244 ASM_VSID_SCRAMBLE(r10,r9,r11,256M)
245 /* r3 = EA, r11 = VSID data */
246 /*
247 * Find a slot, round robin. Previously we tried to find a
248 * free slot first but that took too long. Unfortunately we
249 * dont have any LRU information to help us choose a slot.
250 */
252 mr r9,r3
254 /* slb_finish_load_1T continues here. r9=EA with non-ESID bits clear */
255 7: ld r10,PACASTABRR(r13)
256 addi r10,r10,1
257 /* This gets soft patched on boot. */
258 .globl slb_compare_rr_to_size
259 slb_compare_rr_to_size:
260 cmpldi r10,0
262 blt+ 4f
263 li r10,SLB_NUM_BOLTED
265 4:
266 std r10,PACASTABRR(r13)
268 3:
269 rldimi r9,r10,0,36 /* r9 = EA[0:35] | entry */
270 oris r10,r9,SLB_ESID_V@h /* r10 = r9 | SLB_ESID_V */
272 /* r9 = ESID data, r11 = VSID data */
274 /*
275 * No need for an isync before or after this slbmte. The exception
276 * we enter with and the rfid we exit with are context synchronizing.
277 */
278 slbmte r11,r10
280 /* we're done for kernel addresses */
281 crclr 4*cr0+eq /* set result to "success" */
282 bgelr cr7
284 /* Update the slb cache */
285 lhz r9,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
286 cmpldi r9,SLB_CACHE_ENTRIES
287 bge 1f
289 /* still room in the slb cache */
290 sldi r11,r9,2 /* r11 = offset * sizeof(u32) */
291 srdi r10,r10,28 /* get the 36 bits of the ESID */
292 add r11,r11,r13 /* r11 = (u32 *)paca + offset */
293 stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
294 addi r9,r9,1 /* offset++ */
295 b 2f
296 1: /* offset >= SLB_CACHE_ENTRIES */
297 li r9,SLB_CACHE_ENTRIES+1
298 2:
299 sth r9,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
300 crclr 4*cr0+eq /* set result to "success" */
301 blr
303 /*
304 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
305 *
306 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
307 */
308 .Lslb_finish_load_1T:
309 srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
310 rldimi r10,r9,ESID_BITS_1T,0
311 ASM_VSID_SCRAMBLE(r10,r9,r11,1T)
313 li r10,MMU_SEGSIZE_1T
314 rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
316 /* r3 = EA, r11 = VSID data */
317 clrrdi r9,r3,SID_SHIFT_1T /* clear out non-ESID bits */
318 b 7b
321 _ASM_NOKPROBE_SYMBOL(slb_allocate)
322 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_linear)
323 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_io)
324 _ASM_NOKPROBE_SYMBOL(slb_compare_rr_to_size)
325 #ifdef CONFIG_SPARSEMEM_VMEMMAP
326 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_vmemmap)
327 #endif